diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
| commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
| tree | dbe4c8482b37e854302410318fc474f507310724 /tests/long/fs | |
| parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
| download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz | |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/long/fs')
15 files changed, 26703 insertions, 26687 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 4852a1186..75078a9be 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.893228 # Number of seconds simulated -sim_ticks 1893227633000 # Number of ticks simulated -final_tick 1893227633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1893227678500 # Number of ticks simulated +final_tick 1893227678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25790 # Simulator instruction rate (inst/s) -host_op_rate 25790 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 869674472 # Simulator tick rate (ticks/s) -host_mem_usage 393476 # Number of bytes of host memory used -host_seconds 2176.94 # Real time elapsed on the host -sim_insts 56143729 # Number of instructions simulated -sim_ops 56143729 # Number of ops (including micro ops) simulated +host_inst_rate 31053 # Simulator instruction rate (inst/s) +host_op_rate 31053 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1047239405 # Simulator tick rate (ticks/s) +host_mem_usage 384600 # Number of bytes of host memory used +host_seconds 1807.83 # Real time elapsed on the host +sim_insts 56138739 # Number of instructions simulated +sim_ops 56138739 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1046400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24860352 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25908864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7567040 # Number of bytes written to this memory -system.physmem.bytes_written::total 7567040 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25907712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1046400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1046400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory +system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16350 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 388443 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404826 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118235 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118235 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 553315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13131201 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404808 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 552707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13131200 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13685023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 553315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 553315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3996899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3996899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3996899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 553315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13131201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13684414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3996629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3996629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3996629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13131200 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17681922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404826 # Number of read requests accepted -system.physmem.writeReqs 118235 # Number of write requests accepted -system.physmem.readBursts 404826 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118235 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25901888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 7565888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25908864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7567040 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17681043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404808 # Number of read requests accepted +system.physmem.writeReqs 118227 # Number of write requests accepted +system.physmem.readBursts 404808 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue +system.physmem.bytesWritten 7564480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25907712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25487 # Per bank write bursts system.physmem.perBankRdBursts::1 25708 # Per bank write bursts -system.physmem.perBankRdBursts::2 25813 # Per bank write bursts -system.physmem.perBankRdBursts::3 25780 # Per bank write bursts -system.physmem.perBankRdBursts::4 25224 # Per bank write bursts +system.physmem.perBankRdBursts::2 25811 # Per bank write bursts +system.physmem.perBankRdBursts::3 25775 # Per bank write bursts +system.physmem.perBankRdBursts::4 25223 # Per bank write bursts system.physmem.perBankRdBursts::5 24955 # Per bank write bursts system.physmem.perBankRdBursts::6 24789 # Per bank write bursts -system.physmem.perBankRdBursts::7 24580 # Per bank write bursts -system.physmem.perBankRdBursts::8 25111 # Per bank write bursts +system.physmem.perBankRdBursts::7 24582 # Per bank write bursts +system.physmem.perBankRdBursts::8 25110 # Per bank write bursts system.physmem.perBankRdBursts::9 25258 # Per bank write bursts -system.physmem.perBankRdBursts::10 25520 # Per bank write bursts +system.physmem.perBankRdBursts::10 25516 # Per bank write bursts system.physmem.perBankRdBursts::11 24876 # Per bank write bursts -system.physmem.perBankRdBursts::12 24529 # Per bank write bursts -system.physmem.perBankRdBursts::13 25563 # Per bank write bursts -system.physmem.perBankRdBursts::14 25801 # Per bank write bursts +system.physmem.perBankRdBursts::12 24528 # Per bank write bursts +system.physmem.perBankRdBursts::13 25560 # Per bank write bursts +system.physmem.perBankRdBursts::14 25799 # Per bank write bursts system.physmem.perBankRdBursts::15 25723 # Per bank write bursts -system.physmem.perBankWrBursts::0 7828 # Per bank write bursts -system.physmem.perBankWrBursts::1 7672 # Per bank write bursts -system.physmem.perBankWrBursts::2 8070 # Per bank write bursts -system.physmem.perBankWrBursts::3 7747 # Per bank write bursts -system.physmem.perBankWrBursts::4 7316 # Per bank write bursts -system.physmem.perBankWrBursts::5 6943 # Per bank write bursts -system.physmem.perBankWrBursts::6 6787 # Per bank write bursts -system.physmem.perBankWrBursts::7 6421 # Per bank write bursts -system.physmem.perBankWrBursts::8 7240 # Per bank write bursts -system.physmem.perBankWrBursts::9 6874 # Per bank write bursts -system.physmem.perBankWrBursts::10 7389 # Per bank write bursts -system.physmem.perBankWrBursts::11 6891 # Per bank write bursts -system.physmem.perBankWrBursts::12 7084 # Per bank write bursts -system.physmem.perBankWrBursts::13 8012 # Per bank write bursts -system.physmem.perBankWrBursts::14 7998 # Per bank write bursts -system.physmem.perBankWrBursts::15 7945 # Per bank write bursts +system.physmem.perBankWrBursts::0 7831 # Per bank write bursts +system.physmem.perBankWrBursts::1 7673 # Per bank write bursts +system.physmem.perBankWrBursts::2 8069 # Per bank write bursts +system.physmem.perBankWrBursts::3 7745 # Per bank write bursts +system.physmem.perBankWrBursts::4 7318 # Per bank write bursts +system.physmem.perBankWrBursts::5 6942 # Per bank write bursts +system.physmem.perBankWrBursts::6 6789 # Per bank write bursts +system.physmem.perBankWrBursts::7 6426 # Per bank write bursts +system.physmem.perBankWrBursts::8 7239 # Per bank write bursts +system.physmem.perBankWrBursts::9 6872 # Per bank write bursts +system.physmem.perBankWrBursts::10 7384 # Per bank write bursts +system.physmem.perBankWrBursts::11 6889 # Per bank write bursts +system.physmem.perBankWrBursts::12 7081 # Per bank write bursts +system.physmem.perBankWrBursts::13 8010 # Per bank write bursts +system.physmem.perBankWrBursts::14 7995 # Per bank write bursts +system.physmem.perBankWrBursts::15 7932 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 56 # Number of times write queue was full causing retry -system.physmem.totGap 1893218679000 # Total gap between requests +system.physmem.numWrRetry 72 # Number of times write queue was full causing retry +system.physmem.totGap 1893218795000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404826 # Read request sizes (log2) +system.physmem.readPktSize::6 404808 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118235 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118227 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -149,205 +149,206 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 528.007825 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 321.906071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.488828 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14518 22.90% 22.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11005 17.36% 40.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4663 7.36% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3176 5.01% 52.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2328 3.67% 56.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2299 3.63% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1937 3.06% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1572 2.48% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21887 34.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63385 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.176964 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2915.674794 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5241 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 189 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63391 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 527.918474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 322.301426 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.348187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14401 22.72% 22.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11109 17.52% 40.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4782 7.54% 47.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3159 4.98% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2221 3.50% 56.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2316 3.65% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1932 3.05% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1599 2.52% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21872 34.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63391 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5234 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.317348 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2918.457754 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5231 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5244 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5244 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.543288 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.756988 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.319215 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4714 89.89% 89.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 44 0.84% 90.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 176 3.36% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 4 0.08% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 4 0.08% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 12 0.23% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 7 0.13% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 2 0.04% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 32 0.61% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.10% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 158 3.01% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 14 0.27% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 6 0.11% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 4 0.08% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 11 0.21% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 14 0.27% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 9 0.17% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5234 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5234 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.582155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.722612 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.927693 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4724 90.26% 90.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 39 0.75% 91.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 163 3.11% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 4 0.08% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.06% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 11 0.21% 94.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.15% 94.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 33 0.63% 95.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 144 2.75% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 23 0.44% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 9 0.17% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.06% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 7 0.13% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 10 0.19% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 14 0.27% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.19% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 5 0.10% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5244 # Writes before turning the bus around for reads -system.physmem.totQLat 5894702000 # Total ticks spent queuing -system.physmem.totMemAccLat 13483145750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023585000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14565.00 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-359 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5234 # Writes before turning the bus around for reads +system.physmem.totQLat 5912751750 # Total ticks spent queuing +system.physmem.totMemAccLat 13500876750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14610.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33315.00 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33360.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing -system.physmem.readRowHits 363769 # Number of row buffer hits during reads -system.physmem.writeRowHits 95780 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes -system.physmem.avgGap 3619498.83 # Average gap between requests -system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 221604180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 117785415 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1444679040 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 306852480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4717362000.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4796151000 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 296411520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10938570180 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 5566653120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 443189598645 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 471596477220 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.096553 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1881819292000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 462054000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2003948000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1843451492500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 14496450250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8825649500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 23988038750 # Time in different power states -system.physmem_1.actEnergy 230964720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122760660 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1445000340 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 310240260 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4792348080.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4813778250 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 297177120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11174584380 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 5627937120 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 443035577925 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 471852130095 # Total energy per rank (pJ) -system.physmem_1.averagePower 249.231588 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1881891335250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 468372250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2035962000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1842731534750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 14656099500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8829934000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 24505730500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15259378 # Number of BP lookups -system.cpu.branchPred.condPredicted 13119579 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 525820 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12061992 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4569562 # Number of BTB hits +system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing +system.physmem.readRowHits 363798 # Number of row buffer hits during reads +system.physmem.writeRowHits 95706 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.95 # Row buffer hit rate for writes +system.physmem.avgGap 3619678.98 # Average gap between requests +system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 222139680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 118070040 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1444636200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4706913120.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4768209600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 303610560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10937646210 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 5541404160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 443214367815 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 471564552855 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.079684 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1881862215000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 479498250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1999510000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1843562153500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 14430696500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8769616250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23986204000 # Time in different power states +system.physmem_1.actEnergy 230472060 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122498805 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 310078440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4819392240.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4890695190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 314585760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11137759530 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 5641159680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 443008801920 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 471922426215 # Total energy per rank (pJ) +system.physmem_1.averagePower 249.268712 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1881676600250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 514596250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2047516000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1842563195250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 14690458500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8987140500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24424772000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 15251875 # Number of BP lookups +system.cpu.branchPred.condPredicted 13114549 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 526465 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12070936 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4577345 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.883975 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 862888 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32219 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6522078 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 538261 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5983817 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 225046 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 37.920382 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 863154 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33512 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6526029 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 541717 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5984312 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 221941 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9322510 # DTB read hits -system.cpu.dtb.read_misses 17386 # DTB read misses +system.cpu.dtb.read_hits 9319487 # DTB read hits +system.cpu.dtb.read_misses 17755 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764595 # DTB read accesses -system.cpu.dtb.write_hits 6393584 # DTB write hits -system.cpu.dtb.write_misses 2379 # DTB write misses +system.cpu.dtb.read_accesses 764786 # DTB read accesses +system.cpu.dtb.write_hits 6392965 # DTB write hits +system.cpu.dtb.write_misses 2560 # DTB write misses system.cpu.dtb.write_acv 158 # DTB write access violations -system.cpu.dtb.write_accesses 298734 # DTB write accesses -system.cpu.dtb.data_hits 15716094 # DTB hits -system.cpu.dtb.data_misses 19765 # DTB misses +system.cpu.dtb.write_accesses 298884 # DTB write accesses +system.cpu.dtb.data_hits 15712452 # DTB hits +system.cpu.dtb.data_misses 20315 # DTB misses system.cpu.dtb.data_acv 369 # DTB access violations -system.cpu.dtb.data_accesses 1063329 # DTB accesses -system.cpu.itb.fetch_hits 4018414 # ITB hits -system.cpu.itb.fetch_misses 6313 # ITB misses -system.cpu.itb.fetch_acv 710 # ITB acv -system.cpu.itb.fetch_accesses 4024727 # ITB accesses +system.cpu.dtb.data_accesses 1063670 # DTB accesses +system.cpu.itb.fetch_hits 4023125 # ITB hits +system.cpu.itb.fetch_misses 6293 # ITB misses +system.cpu.itb.fetch_acv 687 # ITB acv +system.cpu.itb.fetch_accesses 4029418 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -360,88 +361,88 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12750 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281835914.509804 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 440008281.220830 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6375 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 224500 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12752 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281784609.786700 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439970621.768515 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 121000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 96523678000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796703955000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 193068084 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 96569006500 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1796658672000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 193159059 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56143729 # Number of instructions committed -system.cpu.committedOps 56143729 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2983109 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 6375 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593387182 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.438818 # CPI: cycles per instruction -system.cpu.ipc 0.290798 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199033 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36198718 64.48% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60825 0.11% 70.28% # Class of committed instruction +system.cpu.committedInsts 56138739 # Number of instructions committed +system.cpu.committedOps 56138739 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2973387 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593296298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.440745 # CPI: cycles per instruction +system.cpu.ipc 0.290635 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 3199075 5.70% 5.70% # Class of committed instruction +system.cpu.op_class_0::IntAlu 36194440 64.47% 70.17% # Class of committed instruction +system.cpu.op_class_0::IntMult 60814 0.11% 70.28% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::MemRead 9175039 16.34% 86.70% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6234994 11.11% 97.80% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::MemRead 9174678 16.34% 86.70% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6234348 11.11% 97.80% # Class of committed instruction system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 950928 1.69% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 951192 1.69% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56143729 # Class of committed instruction +system.cpu.op_class_0::total 56138739 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211453 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74770 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211522 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74796 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105857 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182663 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73403 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105900 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182732 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73429 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73403 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148842 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837707081000 97.07% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 86418000 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 712034000 0.04% 97.11% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54721100500 2.89% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1893226633500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981717 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73429 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148894 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837688968000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 86405500 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 711997500 0.04% 97.11% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54739315500 2.89% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1893226686500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693417 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814845 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693381 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814822 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed @@ -449,7 +450,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175496 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::swpipl 175565 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -458,31 +459,31 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192387 # number of callpals executed +system.cpu.kern.callpal::total 192456 # number of callpals executed system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::user 1736 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::kernel 1904 +system.cpu.kern.mode_good::user 1736 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324596 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324085 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 37288586500 1.97% 1.97% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4317914500 0.23% 2.20% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1851620122500 97.80% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392375 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 37303090500 1.97% 1.97% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4315388500 0.23% 2.20% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1851608197500 97.80% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85319079 # Number of cycles that the object actually ticked -system.cpu.idleCycles 107749005 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394486 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.980102 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13946466 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1394998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.997481 # Average number of references to valid blocks. +system.cpu.tickCycles 85358190 # Number of cycles that the object actually ticked +system.cpu.idleCycles 107800869 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1394352 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13943564 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1394864 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.996361 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.980102 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -490,369 +491,369 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63927467 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63927467 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7985618 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7985618 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5578297 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5578297 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183538 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183538 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198978 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198978 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13563915 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13563915 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13563915 # number of overall hits -system.cpu.dcache.overall_hits::total 13563915 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096590 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096590 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573634 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573634 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16462 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16462 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1670224 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1670224 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1670224 # number of overall misses -system.cpu.dcache.overall_misses::total 1670224 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33587119500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33587119500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25315634500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25315634500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222567500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 222567500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 58902754000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 58902754000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 58902754000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 58902754000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9082208 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9082208 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6151931 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6151931 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200000 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200000 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198978 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198978 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15234139 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15234139 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15234139 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15234139 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120740 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120740 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093245 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082310 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082310 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109637 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109637 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109637 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109637 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30628.693951 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30628.693951 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44132.032794 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44132.032794 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13520.076540 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13520.076540 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35266.379839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35266.379839 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63916074 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63916074 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7983580 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7983580 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5577346 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5577346 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183586 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183586 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199016 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199016 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13560926 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13560926 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13560926 # number of overall hits +system.cpu.dcache.overall_hits::total 13560926 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1096421 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1096421 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573901 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573901 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16452 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16452 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1670322 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1670322 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1670322 # number of overall misses +system.cpu.dcache.overall_misses::total 1670322 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33580747500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33580747500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25364054000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25364054000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223095000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223095000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 58944801500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 58944801500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 58944801500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 58944801500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9080001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9080001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151247 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151247 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199016 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199016 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15231248 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15231248 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15231248 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15231248 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120751 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120751 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093298 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093298 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082244 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082244 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.109664 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.109664 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.109664 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109664 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30627.603357 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30627.603357 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44195.870019 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44195.870019 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.357403 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.357403 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35289.484004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35289.484004 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 837775 # number of writebacks -system.cpu.dcache.writebacks::total 837775 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21966 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21966 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269674 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269674 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 837673 # number of writebacks +system.cpu.dcache.writebacks::total 837673 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269878 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269878 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 291640 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 291640 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 291640 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 291640 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074624 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074624 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303960 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 303960 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16459 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16459 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378584 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378584 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378584 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378584 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 291859 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 291859 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 291859 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 291859 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074440 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074440 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304023 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304023 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16449 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16449 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378463 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378463 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378463 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378463 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32024640000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32024640000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12912591500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12912591500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205405000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205405000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44937231500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44937231500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44937231500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44937231500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534181500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534181500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534181500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534181500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049409 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049409 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082295 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082295 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090493 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090493 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29800.786135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29800.786135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42481.219568 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42481.219568 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.798287 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.798287 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221382.611833 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221382.611833 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92682.987978 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92682.987978 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1476860 # number of replacements -system.cpu.icache.tags.tagsinuse 509.256241 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19221452 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1477371 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.010579 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 36168783500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.256241 # Average occupied blocks per requestor +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32016506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32016506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12938125500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12938125500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205942500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205942500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44954631500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44954631500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44954631500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44954631500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534159000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534159000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534159000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534159000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118330 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118330 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049425 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049425 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082229 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082229 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090502 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090502 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29798.319124 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29798.319124 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42556.403627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42556.403627 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12520.062010 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12520.062010 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.365079 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.365079 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92681.628708 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92681.628708 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1477259 # number of replacements +system.cpu.icache.tags.tagsinuse 509.256262 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 19240724 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1477770 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.020107 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 36168160500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.256262 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 22176547 # Number of tag accesses -system.cpu.icache.tags.data_accesses 22176547 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 19221455 # 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average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70727.555578 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70727.555578 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208879.653680 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208879.653680 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.559174 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.559174 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5743935 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871442 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80087.132447 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80087.132447 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88703.565531 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88703.565531 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70709.710125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70709.710125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87447.290521 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87447.290521 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5744469 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871707 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2575661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2575864 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 914498 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1476860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 819632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 303970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 303970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4431899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8649734 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189078592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142951868 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 332030460 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 340255 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4923648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3229187 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001046 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032331 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 914388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1477259 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 819593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477946 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4433097 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217440 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8650537 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189129664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142936828 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 332066492 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 340239 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4923200 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3229438 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001049 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032373 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3225808 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3379 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3226050 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3388 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3229187 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5199690500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3229438 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5200254500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 292383 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2216461215 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2217065706 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2104266491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2104067991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -971,7 +972,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51175 # Transaction distribution @@ -1002,46 +1003,46 @@ system.iobus.pkt_size_system.bridge.master::total 44348 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5413000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5413500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 807000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 792000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 181000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15127500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15611000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5984000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5971500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216248283 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216263272 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.299538 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.299521 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1735874305000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.299538 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081221 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081221 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1735874841000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.299521 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081220 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081220 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1052,12 +1053,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 29884383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 29884383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931902900 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4931902900 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4961787283 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4961787283 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4961787283 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4961787283 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948356889 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4948356889 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4978241272 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4978241272 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4978241272 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4978241272 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1076,17 +1077,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 172742.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 172742.098266 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118692.310839 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118692.310839 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118916.411815 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118916.411815 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119088.296327 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119088.296327 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119310.755470 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119310.755470 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1846 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 14 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 111.625000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 131.857143 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1100,12 +1101,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 21234383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 21234383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851851307 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2851851307 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2873085690 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2873085690 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2873085690 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2873085690 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868303297 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2868303297 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2889537680 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2889537680 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2889537680 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2889537680 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1116,74 +1117,74 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 122742.098266 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 122742.098266 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68633.310238 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68633.310238 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 827515 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 381393 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69029.247617 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69029.247617 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 827499 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 381391 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 524 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295677 # Transaction distribution +system.membus.trans_dist::ReadResp 295651 # Transaction distribution system.membus.trans_dist::WriteReq 9623 # Transaction distribution system.membus.trans_dist::WriteResp 9623 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118235 # Transaction distribution -system.membus.trans_dist::CleanEvict 262254 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution +system.membus.trans_dist::CleanEvict 262247 # Transaction distribution system.membus.trans_dist::UpgradeReq 138 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 116510 # Transaction distribution -system.membus.trans_dist::ReadExResp 116510 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288770 # Transaction distribution -system.membus.trans_dist::BadAddressError 23 # Transaction distribution +system.membus.trans_dist::ReadExReq 116518 # Transaction distribution +system.membus.trans_dist::ReadExResp 116518 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution +system.membus.trans_dist::BadAddressError 24 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 127 # Transaction distribution +system.membus.trans_dist::InvalidateResp 124 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148837 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181989 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181940 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265414 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1265365 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30818176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30862524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860860 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33520252 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 561 # Total snoops (count) +system.membus.pkt_size::total 33518588 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 558 # Total snoops (count) system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 463523 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001461 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038189 # Request fanout histogram +system.membus.snoop_fanout::samples 463506 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001454 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038105 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 462846 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 674 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 463523 # Request fanout histogram -system.membus.reqLayer0.occupancy 29930000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 463506 # Request fanout histogram +system.membus.reqLayer0.occupancy 30386000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319547835 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319436087 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 29000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160176250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160035750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1081022 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1079521 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1215,28 +1216,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 53cfb4ebd..1e6aa4a0d 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.909484 # Number of seconds simulated -sim_ticks 1909483951500 # Number of ticks simulated -final_tick 1909483951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.910457 # Number of seconds simulated +sim_ticks 1910457097500 # Number of ticks simulated +final_tick 1910457097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164890 # Simulator instruction rate (inst/s) -host_op_rate 164890 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5556117262 # Simulator tick rate (ticks/s) -host_mem_usage 341236 # Number of bytes of host memory used -host_seconds 343.67 # Real time elapsed on the host -sim_insts 56668174 # Number of instructions simulated -sim_ops 56668174 # Number of ops (including micro ops) simulated +host_inst_rate 237868 # Simulator instruction rate (inst/s) +host_op_rate 237868 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8017235800 # Simulator tick rate (ticks/s) +host_mem_usage 340828 # Number of bytes of host memory used +host_seconds 238.29 # Real time elapsed on the host +sim_insts 56682446 # Number of instructions simulated +sim_ops 56682446 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24440064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 856512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24438912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 120704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 888384 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26307904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 978624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7910400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7910400 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 381876 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26305472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 856512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 120704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7909632 # Number of bytes written to this memory +system.physmem.bytes_written::total 7909632 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 381858 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1886 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13881 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411061 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123600 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123600 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 449127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12799303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 465181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13777494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4142690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4142690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4142690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12799303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 465181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17920184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411061 # Number of read requests accepted -system.physmem.writeReqs 123600 # Number of write requests accepted -system.physmem.readBursts 411061 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123600 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26300672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue -system.physmem.bytesWritten 7909120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26307904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7910400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 411023 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123588 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123588 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 448328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12792180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 465011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13769203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 448328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 511509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4140178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4140178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4140178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 448328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12792180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 465011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17909381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411023 # Number of read requests accepted +system.physmem.writeReqs 123588 # Number of write requests accepted +system.physmem.readBursts 411023 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123588 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26298624 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue +system.physmem.bytesWritten 7907712 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26305472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7909632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26241 # Per bank write bursts -system.physmem.perBankRdBursts::1 25988 # Per bank write bursts -system.physmem.perBankRdBursts::2 25972 # Per bank write bursts -system.physmem.perBankRdBursts::3 25684 # Per bank write bursts -system.physmem.perBankRdBursts::4 25579 # Per bank write bursts -system.physmem.perBankRdBursts::5 25567 # Per bank write bursts -system.physmem.perBankRdBursts::6 25634 # Per bank write bursts -system.physmem.perBankRdBursts::7 25346 # Per bank write bursts -system.physmem.perBankRdBursts::8 25590 # Per bank write bursts -system.physmem.perBankRdBursts::9 25694 # Per bank write bursts -system.physmem.perBankRdBursts::10 25928 # Per bank write bursts -system.physmem.perBankRdBursts::11 25514 # Per bank write bursts +system.physmem.perBankRdBursts::0 26243 # Per bank write bursts +system.physmem.perBankRdBursts::1 25982 # Per bank write bursts +system.physmem.perBankRdBursts::2 25968 # Per bank write bursts +system.physmem.perBankRdBursts::3 25688 # Per bank write bursts +system.physmem.perBankRdBursts::4 25576 # Per bank write bursts +system.physmem.perBankRdBursts::5 25569 # Per bank write bursts +system.physmem.perBankRdBursts::6 25629 # Per bank write bursts +system.physmem.perBankRdBursts::7 25342 # Per bank write bursts +system.physmem.perBankRdBursts::8 25591 # Per bank write bursts +system.physmem.perBankRdBursts::9 25697 # Per bank write bursts +system.physmem.perBankRdBursts::10 25920 # Per bank write bursts +system.physmem.perBankRdBursts::11 25515 # Per bank write bursts system.physmem.perBankRdBursts::12 26076 # Per bank write bursts -system.physmem.perBankRdBursts::13 25422 # Per bank write bursts -system.physmem.perBankRdBursts::14 25093 # Per bank write bursts -system.physmem.perBankRdBursts::15 25620 # Per bank write bursts -system.physmem.perBankWrBursts::0 8582 # Per bank write bursts -system.physmem.perBankWrBursts::1 8090 # Per bank write bursts -system.physmem.perBankWrBursts::2 7941 # Per bank write bursts -system.physmem.perBankWrBursts::3 7423 # Per bank write bursts -system.physmem.perBankWrBursts::4 7276 # Per bank write bursts -system.physmem.perBankWrBursts::5 7412 # Per bank write bursts -system.physmem.perBankWrBursts::6 7548 # Per bank write bursts -system.physmem.perBankWrBursts::7 7160 # Per bank write bursts -system.physmem.perBankWrBursts::8 7532 # Per bank write bursts -system.physmem.perBankWrBursts::9 7637 # Per bank write bursts -system.physmem.perBankWrBursts::10 7817 # Per bank write bursts -system.physmem.perBankWrBursts::11 7733 # Per bank write bursts -system.physmem.perBankWrBursts::12 8265 # Per bank write bursts -system.physmem.perBankWrBursts::13 7849 # Per bank write bursts -system.physmem.perBankWrBursts::14 7512 # Per bank write bursts -system.physmem.perBankWrBursts::15 7803 # Per bank write bursts +system.physmem.perBankRdBursts::13 25417 # Per bank write bursts +system.physmem.perBankRdBursts::14 25094 # Per bank write bursts +system.physmem.perBankRdBursts::15 25609 # Per bank write bursts +system.physmem.perBankWrBursts::0 8586 # Per bank write bursts +system.physmem.perBankWrBursts::1 8089 # Per bank write bursts +system.physmem.perBankWrBursts::2 7939 # Per bank write bursts +system.physmem.perBankWrBursts::3 7426 # Per bank write bursts +system.physmem.perBankWrBursts::4 7272 # Per bank write bursts +system.physmem.perBankWrBursts::5 7413 # Per bank write bursts +system.physmem.perBankWrBursts::6 7547 # Per bank write bursts +system.physmem.perBankWrBursts::7 7156 # Per bank write bursts +system.physmem.perBankWrBursts::8 7533 # Per bank write bursts +system.physmem.perBankWrBursts::9 7641 # Per bank write bursts +system.physmem.perBankWrBursts::10 7810 # Per bank write bursts +system.physmem.perBankWrBursts::11 7729 # Per bank write bursts +system.physmem.perBankWrBursts::12 8256 # Per bank write bursts +system.physmem.perBankWrBursts::13 7847 # Per bank write bursts +system.physmem.perBankWrBursts::14 7516 # Per bank write bursts +system.physmem.perBankWrBursts::15 7798 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 80 # Number of times write queue was full causing retry -system.physmem.totGap 1909479571500 # Total gap between requests +system.physmem.numWrRetry 69 # Number of times write queue was full causing retry +system.physmem.totGap 1910452747500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411061 # Read request sizes (log2) +system.physmem.readPktSize::6 411023 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123600 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 316679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123588 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 316637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see @@ -159,205 +159,206 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 213 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.481590 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 324.184214 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.960810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14447 22.45% 22.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11484 17.84% 40.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5025 7.81% 48.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2916 4.53% 52.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2241 3.48% 56.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1886 2.93% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1937 3.01% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1616 2.51% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22814 35.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64366 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5520 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.445833 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2823.039428 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5517 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 160 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 532.249522 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 325.147595 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.887517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14293 22.24% 22.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11517 17.92% 40.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5102 7.94% 48.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2862 4.45% 52.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2222 3.46% 56.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1875 2.92% 58.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1935 3.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1643 2.56% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22818 35.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64267 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5506 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.626952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2826.578445 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5503 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5520 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5520 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.387681 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.753213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.953412 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4982 90.25% 90.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 46 0.83% 91.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 181 3.28% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 8 0.14% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.05% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 15 0.27% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 3 0.05% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1 0.02% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 37 0.67% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.11% 95.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 147 2.66% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 11 0.20% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 11 0.20% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 13 0.24% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 5 0.09% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.07% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 8 0.14% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 11 0.20% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 8 0.14% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 6 0.11% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5520 # Writes before turning the bus around for reads -system.physmem.totQLat 8180795500 # Total ticks spent queuing -system.physmem.totMemAccLat 15886070500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2054740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19907.13 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5506 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5506 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.440610 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.769678 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.128904 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4988 90.59% 90.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 40 0.73% 91.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 160 2.91% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 10 0.18% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 4 0.07% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 18 0.33% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 5 0.09% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 6 0.11% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 35 0.64% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 137 2.49% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 15 0.27% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 13 0.24% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 8 0.15% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.05% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 5 0.09% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.05% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.16% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 10 0.18% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 9 0.16% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 8 0.15% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5506 # Writes before turning the bus around for reads +system.physmem.totQLat 8133947000 # Total ticks spent queuing +system.physmem.totMemAccLat 15838622000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2054580000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19794.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38657.13 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38544.67 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.22 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing -system.physmem.readRowHits 370615 # Number of row buffer hits during reads -system.physmem.writeRowHits 99546 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.54 # Row buffer hit rate for writes -system.physmem.avgGap 3571383.68 # Average gap between requests -system.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229044060 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 121739805 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1470918540 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 320675040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3850719600.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4272567240 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 246889440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8425769640 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4664365920 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 449143940805 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 472747584480 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.578716 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1899455525250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 389729500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1635812000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1868844860000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 12146835250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7989359750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 18477355000 # Time in different power states -system.physmem_1.actEnergy 230536320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122529165 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1463250180 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 324412560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3755450400.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4276202130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 236380800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8298087360 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4412246880 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 449354887095 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 472475862540 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.436414 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1899482388000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 371395250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1595272000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1869798792500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11490281750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8030486500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 18197723500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 16749334 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14325553 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 462257 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10374415 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4757954 # Number of BTB hits +system.physmem.avgRdQLen 2.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.12 # Average write queue length when enqueuing +system.physmem.readRowHits 370641 # Number of row buffer hits during reads +system.physmem.writeRowHits 99565 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.56 # Row buffer hit rate for writes +system.physmem.avgGap 3573538.04 # Average gap between requests +system.physmem.pageHitRate 87.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 228629940 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 121519695 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 320654160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3862397760.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4332596790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 252811200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8421848610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4670504160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 449339904270 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 473022982485 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.596757 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1900281265750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 402747000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1640746000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1869662817000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 12162830000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8118960750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 18468996750 # Time in different power states +system.physmem_1.actEnergy 230243580 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122373570 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1463121660 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 324318600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3740699040.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4231975260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230624160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8237523150 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4445714880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 449624008125 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 472652324325 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.402742 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1900567958250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 356565750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1589032000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1870929942000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11577456000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7939162500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 18064939250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 16804357 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14368910 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 476654 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10787243 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4777357 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 45.862384 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 926589 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 34524 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4807269 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 496703 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 4310566 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 206845 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 44.287099 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 929095 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33008 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5112942 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 499455 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 4613487 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 206250 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9423503 # DTB read hits -system.cpu0.dtb.read_misses 34044 # DTB read misses -system.cpu0.dtb.read_acv 602 # DTB read access violations -system.cpu0.dtb.read_accesses 567323 # DTB read accesses -system.cpu0.dtb.write_hits 5707426 # DTB write hits -system.cpu0.dtb.write_misses 8375 # DTB write misses -system.cpu0.dtb.write_acv 432 # DTB write access violations -system.cpu0.dtb.write_accesses 185068 # DTB write accesses -system.cpu0.dtb.data_hits 15130929 # DTB hits -system.cpu0.dtb.data_misses 42419 # DTB misses -system.cpu0.dtb.data_acv 1034 # DTB access violations -system.cpu0.dtb.data_accesses 752391 # DTB accesses -system.cpu0.itb.fetch_hits 1309826 # ITB hits -system.cpu0.itb.fetch_misses 6979 # ITB misses -system.cpu0.itb.fetch_acv 608 # ITB acv -system.cpu0.itb.fetch_accesses 1316805 # ITB accesses +system.cpu0.dtb.read_hits 9429395 # DTB read hits +system.cpu0.dtb.read_misses 34826 # DTB read misses +system.cpu0.dtb.read_acv 601 # DTB read access violations +system.cpu0.dtb.read_accesses 567385 # DTB read accesses +system.cpu0.dtb.write_hits 5710239 # DTB write hits +system.cpu0.dtb.write_misses 8500 # DTB write misses +system.cpu0.dtb.write_acv 413 # DTB write access violations +system.cpu0.dtb.write_accesses 185113 # DTB write accesses +system.cpu0.dtb.data_hits 15139634 # DTB hits +system.cpu0.dtb.data_misses 43326 # DTB misses +system.cpu0.dtb.data_acv 1014 # DTB access violations +system.cpu0.dtb.data_accesses 752498 # DTB accesses +system.cpu0.itb.fetch_hits 1313411 # ITB hits +system.cpu0.itb.fetch_misses 6916 # ITB misses +system.cpu0.itb.fetch_acv 613 # ITB acv +system.cpu0.itb.fetch_accesses 1320327 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -370,152 +371,152 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 12955 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6478 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 285544950.833745 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 440803858.104390 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6477 99.98% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 12957 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6479 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 285646442.815249 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 440880288.422179 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6479 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 39000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6478 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 59723759999 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849760191501 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 119453997 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6479 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 59753794500 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1850703303000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 119514068 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25744550 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 73396662 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16749334 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6181246 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 86853986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1333740 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 29854 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 138979 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 426939 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8448706 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 314842 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 113861488 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.644614 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.955082 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25767559 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 73719684 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16804357 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6205907 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 86932839 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1362768 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30191 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 137457 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 417781 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8508507 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 323806 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 113967656 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.646847 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.957898 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 100232411 88.03% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 886423 0.78% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1866278 1.64% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 772305 0.68% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2608424 2.29% 93.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 580288 0.51% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 680998 0.60% 94.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 835244 0.73% 95.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5399117 4.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 100279992 87.99% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 883136 0.77% 88.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1879288 1.65% 90.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 773699 0.68% 91.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2621733 2.30% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 582123 0.51% 93.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 690580 0.61% 94.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 840992 0.74% 95.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5416113 4.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 113861488 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.140216 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.614435 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20674409 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 82009104 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8737077 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1802336 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 638561 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 612096 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 28873 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 63730808 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 85670 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 638561 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21537349 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 55655987 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17571911 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9607617 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8850061 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 61287779 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 195487 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2001492 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 247198 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4966656 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 41332689 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 73998496 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 73867344 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 122420 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33806898 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7525791 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1421231 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 231053 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12310515 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9804371 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6066029 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1436076 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 935297 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 54210960 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1853678 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52617678 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 75373 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9354795 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4029114 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1289525 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 113861488 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.462120 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.203620 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 113967656 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.140606 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.616829 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20688539 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 82043348 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8777506 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1804992 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 653270 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 4633985 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 29119 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 64001211 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 84558 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 653270 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21557209 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 55702323 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17600356 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9645124 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8809372 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 61498566 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 199219 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2004403 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 243805 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4929982 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 41484246 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 74256527 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 74125426 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 122370 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33821902 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7662344 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1423361 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 232902 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12334048 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9834851 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6076556 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1449838 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 941199 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 54338035 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1857223 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52670686 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 76725 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9465955 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4150833 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1293033 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 113967656 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.462155 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.203590 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 92467205 81.21% 81.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9144132 8.03% 89.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3819872 3.35% 92.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2741139 2.41% 95.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2853722 2.51% 97.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1412384 1.24% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 945124 0.83% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 360447 0.32% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 117463 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 92547755 81.21% 81.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9157312 8.04% 89.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3826452 3.36% 92.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2741793 2.41% 95.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2858470 2.51% 97.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1410754 1.24% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 945179 0.83% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 363161 0.32% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 116780 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 113861488 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 113967656 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 167498 16.72% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 489097 48.82% 65.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 297116 29.66% 95.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 26550 2.65% 97.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 21561 2.15% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 167135 16.69% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 489044 48.84% 65.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 297041 29.67% 95.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 26511 2.65% 97.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 21568 2.15% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2541 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36104376 68.62% 68.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 55717 0.11% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2539 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36140522 68.62% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 55958 0.11% 68.73% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 25404 0.05% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25396 0.05% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued @@ -543,444 +544,444 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9732272 18.50% 87.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5684196 10.80% 98.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 122332 0.23% 98.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 110816 0.21% 98.52% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 778757 1.48% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9743290 18.50% 87.28% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5689891 10.80% 98.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 122252 0.23% 98.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 110721 0.21% 98.52% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 778850 1.48% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52617678 # Type of FU issued -system.cpu0.iq.rate 0.440485 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1001822 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019040 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 219604859 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65162997 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50893555 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 569180 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 274272 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 257685 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53309029 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 307930 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 608555 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52670686 # Type of FU issued +system.cpu0.iq.rate 0.440707 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1001299 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019011 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 219818324 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65405263 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50914307 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 568728 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 273845 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 257541 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53361731 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 307715 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 607759 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1940010 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3457 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18333 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 663404 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1969497 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4520 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18416 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 673256 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18340 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 362661 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18394 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367969 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 638561 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 52164612 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1031418 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 59600447 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 153776 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9804371 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6066029 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1643055 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39666 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 791016 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18333 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 179892 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 504278 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 684170 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51936356 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9483037 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 681322 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 653270 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 52238307 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1038475 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 59749161 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 168806 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9834851 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6076556 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1644704 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40383 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 797635 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18416 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 191736 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 507842 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 699578 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51971663 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9489993 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 699023 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3535809 # number of nop insts executed -system.cpu0.iew.exec_refs 15215766 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8258108 # Number of branches executed -system.cpu0.iew.exec_stores 5732729 # Number of stores executed -system.cpu0.iew.exec_rate 0.434781 # Inst execution rate -system.cpu0.iew.wb_sent 51332154 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51151240 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26231692 # num instructions producing a value -system.cpu0.iew.wb_consumers 36261297 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.428209 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723407 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9848757 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 564153 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 610679 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 112148809 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.442210 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.364760 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3553903 # number of nop insts executed +system.cpu0.iew.exec_refs 15226009 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8258878 # Number of branches executed +system.cpu0.iew.exec_stores 5736016 # Number of stores executed +system.cpu0.iew.exec_rate 0.434858 # Inst execution rate +system.cpu0.iew.wb_sent 51356635 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51171848 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26241416 # num instructions producing a value +system.cpu0.iew.wb_consumers 36276103 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.428166 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723380 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9976632 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 564190 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 625296 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 112216183 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.442120 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.363987 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 94602668 84.35% 84.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6980008 6.22% 90.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3776982 3.37% 93.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2002013 1.79% 95.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1561505 1.39% 97.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 569175 0.51% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 418696 0.37% 98.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 452906 0.40% 98.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1784856 1.59% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 94653327 84.35% 84.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6985358 6.22% 90.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3782709 3.37% 93.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2004229 1.79% 95.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1568389 1.40% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 570810 0.51% 97.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 418508 0.37% 98.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 451920 0.40% 98.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1780933 1.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 112148809 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49593272 # Number of instructions committed -system.cpu0.commit.committedOps 49593272 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 112216183 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49613021 # Number of instructions committed +system.cpu0.commit.committedOps 49613021 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13266986 # Number of memory references committed -system.cpu0.commit.loads 7864361 # Number of loads committed -system.cpu0.commit.membars 192313 # Number of memory barriers committed -system.cpu0.commit.branches 7507748 # Number of branches committed -system.cpu0.commit.fp_insts 248828 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45902219 # Number of committed integer instructions. -system.cpu0.commit.function_calls 632222 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2885965 5.82% 5.82% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32382704 65.30% 71.12% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 54404 0.11% 71.23% # Class of committed instruction +system.cpu0.commit.refs 13268654 # Number of memory references committed +system.cpu0.commit.loads 7865354 # Number of loads committed +system.cpu0.commit.membars 192328 # Number of memory barriers committed +system.cpu0.commit.branches 7511599 # Number of branches committed +system.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45921534 # Number of committed integer instructions. +system.cpu0.commit.function_calls 632359 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2886254 5.82% 5.82% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32400169 65.31% 71.12% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54625 0.11% 71.23% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 24932 0.05% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7943457 16.02% 87.30% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5299157 10.69% 97.98% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemRead 113217 0.23% 98.21% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemWrite 109412 0.22% 98.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 778757 1.57% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7944499 16.01% 87.30% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5299897 10.68% 97.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 113183 0.23% 98.21% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 109348 0.22% 98.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 778850 1.57% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 49593272 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1784856 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 169631516 # The number of ROB reads -system.cpu0.rob.rob_writes 120597460 # The number of ROB writes -system.cpu0.timesIdled 479927 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5592509 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3698912124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46709842 # Number of Instructions Simulated -system.cpu0.committedOps 46709842 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.557362 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.557362 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.391028 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.391028 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67996788 # number of integer regfile reads -system.cpu0.int_regfile_writes 37259313 # number of integer regfile writes -system.cpu0.fp_regfile_reads 121463 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130119 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1657761 # number of misc regfile reads -system.cpu0.misc_regfile_writes 782234 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1252644 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.062362 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10655904 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1253074 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.503811 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.062362 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988403 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988403 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 49613021 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1780933 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 169850432 # The number of ROB reads +system.cpu0.rob.rob_writes 120933247 # The number of ROB writes +system.cpu0.timesIdled 478916 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5546412 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3700805346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46729302 # Number of Instructions Simulated +system.cpu0.committedOps 46729302 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.557583 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.557583 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.390994 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.390994 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68048969 # number of integer regfile reads +system.cpu0.int_regfile_writes 37279666 # number of integer regfile writes +system.cpu0.fp_regfile_reads 121382 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130068 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1658488 # number of misc regfile reads +system.cpu0.misc_regfile_writes 782262 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1253915 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.032819 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10656048 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1254345 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.495309 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 28054500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.032819 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988345 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988345 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56905298 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56905298 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6776069 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6776069 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3521167 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3521167 # 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number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194913 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 194913 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182958 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 182958 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13533054 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13533054 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13533054 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13533054 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186313 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.186313 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323561 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323561 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104585 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104585 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016567 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016567 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239105 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.239105 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239105 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.239105 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26774.664028 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26774.664028 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50460.624067 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50460.624067 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18821.363748 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18821.363748 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5625.041241 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5625.041241 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39103.453137 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39103.453137 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4484959 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5749 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 107356 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 120 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.776510 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 47.908333 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 737573 # number of writebacks -system.cpu0.dcache.writebacks::total 737573 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 550277 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 550277 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432731 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1432731 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5546 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5546 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983008 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1983008 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983008 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1983008 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001264 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1001264 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251546 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251546 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3031 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3031 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1252810 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1252810 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1252810 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1252810 # number of overall MSHR misses +system.cpu0.dcache.tags.tag_accesses 56914873 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56914873 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6773563 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6773563 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3523907 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3523907 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174492 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174492 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179921 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 179921 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10297470 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10297470 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10297470 # number of overall hits +system.cpu0.dcache.overall_hits::total 10297470 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1555944 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1555944 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1682220 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1682220 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19936 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19936 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3029 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3029 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3238164 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3238164 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3238164 # number of overall misses +system.cpu0.dcache.overall_misses::total 3238164 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41483749500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41483749500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85008982052 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 85008982052 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 398193000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 398193000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17043500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 17043500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 126492731552 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 126492731552 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 126492731552 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 126492731552 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8329507 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8329507 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5206127 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5206127 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194428 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 194428 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182950 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 182950 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13535634 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13535634 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13535634 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13535634 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186799 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.186799 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323123 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323123 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.102537 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.102537 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016556 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016556 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239233 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.239233 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239233 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.239233 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26661.466929 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26661.466929 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50533.807737 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50533.807737 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19973.565409 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19973.565409 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.774513 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.774513 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39063.102286 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39063.102286 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39063.102286 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39063.102286 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4473141 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2637 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 108649 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 100 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.170568 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 26.370000 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 737996 # 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number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1002620 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251616 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251616 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14611 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14611 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3029 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3029 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1254236 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1254236 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1254236 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1254236 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9910 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16887 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31631751000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31631751000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13189939409 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13189939409 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172118000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172118000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14018500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14018500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44821690409 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 44821690409 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44821690409 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 44821690409 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557150500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557150500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557150500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557150500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120234 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120234 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048324 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048324 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076131 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076131 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016567 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016567 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092574 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092574 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31591.818941 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31591.818941 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52435.496525 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52435.496525 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11599.029584 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11599.029584 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4625.041241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4625.041241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223183.388276 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223183.388276 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92210.013620 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92210.013620 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 892272 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.350681 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7503325 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 892783 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.404422 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30334536500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.350681 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994826 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994826 # Average percentage of cache occupancy +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9909 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9909 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16886 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16886 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31595131000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31595131000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13207477923 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13207477923 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 169739500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 169739500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14014500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14014500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44802608923 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 44802608923 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44802608923 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 44802608923 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557264500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557264500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557264500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557264500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120370 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075149 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075149 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016556 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016556 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092662 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092662 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092662 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092662 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31512.568072 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31512.568072 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52490.612374 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52490.612374 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11617.240435 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11617.240435 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.774513 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.774513 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223199.727677 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223199.727677 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92222.225512 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92222.225512 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 891919 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.368701 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7561136 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892430 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.472526 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30335024500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.368701 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994861 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994861 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9341754 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9341754 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7503325 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7503325 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7503325 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7503325 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7503325 # number of overall hits -system.cpu0.icache.overall_hits::total 7503325 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 945376 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 945376 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 945376 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 945376 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 945376 # number of overall misses -system.cpu0.icache.overall_misses::total 945376 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858102494 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13858102494 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13858102494 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13858102494 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13858102494 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13858102494 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8448701 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8448701 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8448701 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8448701 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8448701 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8448701 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111896 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.111896 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111896 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.111896 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111896 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.111896 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14658.826217 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14658.826217 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14658.826217 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14658.826217 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6578 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9401165 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9401165 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 7561136 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7561136 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7561136 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7561136 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7561136 # number of overall hits +system.cpu0.icache.overall_hits::total 7561136 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 947367 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 947367 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 947367 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 947367 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 947367 # number of overall misses +system.cpu0.icache.overall_misses::total 947367 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858743493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13858743493 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13858743493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13858743493 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13858743493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13858743493 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8508503 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8508503 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8508503 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8508503 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8508503 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8508503 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111344 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111344 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111344 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111344 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111344 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111344 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14628.695630 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14628.695630 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14628.695630 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14628.695630 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14628.695630 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14628.695630 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 7760 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 245 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 263 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.848980 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.505703 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 892272 # number of writebacks -system.cpu0.icache.writebacks::total 892272 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52323 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 52323 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 52323 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 52323 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 52323 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 52323 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 893053 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 893053 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 893053 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 893053 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 893053 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 893053 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12259429995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12259429995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12259429995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12259429995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12259429995 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12259429995 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105703 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105703 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105703 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13727.550319 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency -system.cpu1.branchPred.lookups 4441555 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3820450 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 114047 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2322340 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 883836 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 891919 # number of writebacks +system.cpu0.icache.writebacks::total 891919 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54705 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54705 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54705 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54705 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54705 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54705 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 892662 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 892662 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 892662 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 892662 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 892662 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 892662 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12247880494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12247880494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12247880494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12247880494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12247880494 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12247880494 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.104914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.104914 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.104914 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13720.624933 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13720.624933 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13720.624933 # average overall mshr miss latency +system.cpu1.branchPred.lookups 4440494 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3820633 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 114977 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2284731 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 882766 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 38.057993 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 229553 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8671 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 1262341 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 163265 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1099076 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 40828 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 38.637634 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 229523 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8540 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 1232926 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 164040 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1068886 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2431988 # DTB read hits -system.cpu1.dtb.read_misses 15687 # DTB read misses -system.cpu1.dtb.read_acv 78 # DTB read access violations -system.cpu1.dtb.read_accesses 432427 # DTB read accesses -system.cpu1.dtb.write_hits 1439876 # DTB write hits -system.cpu1.dtb.write_misses 3853 # DTB write misses -system.cpu1.dtb.write_acv 69 # DTB write access violations -system.cpu1.dtb.write_accesses 163205 # DTB write accesses -system.cpu1.dtb.data_hits 3871864 # DTB hits -system.cpu1.dtb.data_misses 19540 # DTB misses +system.cpu1.dtb.read_hits 2425125 # DTB read hits +system.cpu1.dtb.read_misses 16040 # DTB read misses +system.cpu1.dtb.read_acv 82 # DTB read access violations +system.cpu1.dtb.read_accesses 432289 # DTB read accesses +system.cpu1.dtb.write_hits 1438640 # DTB write hits +system.cpu1.dtb.write_misses 3531 # DTB write misses +system.cpu1.dtb.write_acv 65 # DTB write access violations +system.cpu1.dtb.write_accesses 162605 # DTB write accesses +system.cpu1.dtb.data_hits 3863765 # DTB hits +system.cpu1.dtb.data_misses 19571 # DTB misses system.cpu1.dtb.data_acv 147 # DTB access violations -system.cpu1.dtb.data_accesses 595632 # DTB accesses -system.cpu1.itb.fetch_hits 677957 # ITB hits -system.cpu1.itb.fetch_misses 3440 # ITB misses -system.cpu1.itb.fetch_acv 149 # ITB acv -system.cpu1.itb.fetch_accesses 681397 # ITB accesses +system.cpu1.dtb.data_accesses 594894 # DTB accesses +system.cpu1.itb.fetch_hits 679335 # ITB hits +system.cpu1.itb.fetch_misses 3486 # ITB misses +system.cpu1.itb.fetch_acv 144 # ITB acv +system.cpu1.itb.fetch_accesses 682821 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -993,584 +994,585 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5092 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2546 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 746545753.142184 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 396892720.756326 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2546 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 350000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2546 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 8778464000 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1900705487500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 17559475 # number of cpu cycles simulated +system.cpu1.numPwrStateTransitions 5088 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2544 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 747516916.077044 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 396242813.132808 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2544 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 975504000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2544 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 8774063000 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1901683034500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 17550671 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 7089129 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17628986 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4441555 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1276654 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9239971 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 379390 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 67759 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 51232 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1981137 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 84838 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 16664835 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.057855 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.464288 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7093737 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17628277 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4440494 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1276329 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9234250 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 381282 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 26389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 68063 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 51076 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1982953 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 84304 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 16664213 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.057852 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.464693 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 13565594 81.40% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 195508 1.17% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 331371 1.99% 84.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 236250 1.42% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 403775 2.42% 88.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 149802 0.90% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 175422 1.05% 90.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 211560 1.27% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1395553 8.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 13566532 81.41% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 196080 1.18% 82.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 329765 1.98% 84.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 235529 1.41% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 402874 2.42% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 150126 0.90% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 175137 1.05% 90.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 212228 1.27% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1395942 8.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 16664835 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.252943 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.003959 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5800433 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8202202 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2197206 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 282756 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 182237 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 153534 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7597 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 14400936 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 23892 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 182237 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5989487 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 906248 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6023778 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2292128 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1270955 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13634993 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3736 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 109479 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 34532 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 648624 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 9050025 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 16251882 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 16185746 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59544 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7082137 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1967880 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 511648 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 53659 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2285085 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2543631 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1545283 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 323334 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 171078 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 11953372 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 586667 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 11470583 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27894 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2581702 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1224765 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 432970 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 16664835 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.688311 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.414763 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 16664213 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.253010 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.004422 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5803889 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8198941 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2195429 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 282754 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 183199 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 845965 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7619 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 14397519 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 23764 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 183199 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5993501 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 917111 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6016357 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2289218 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1264825 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13624374 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3775 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 108540 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 34178 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 643759 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 9046149 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 16244839 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 16178929 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59321 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7078981 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1967160 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 511491 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 53621 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2283119 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2539964 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1543921 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 323106 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 168966 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11939663 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 585885 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 11455956 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 28942 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2572399 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1228155 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 432246 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 16664213 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.687459 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.414504 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11964424 71.79% 71.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2022081 12.13% 83.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 866450 5.20% 89.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 621081 3.73% 92.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 573042 3.44% 96.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 300412 1.80% 98.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 196836 1.18% 99.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 86957 0.52% 99.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 33552 0.20% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11970475 71.83% 71.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2021121 12.13% 83.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 863574 5.18% 89.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 618225 3.71% 92.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 572472 3.44% 96.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 300775 1.80% 98.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 197233 1.18% 99.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 86853 0.52% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 33485 0.20% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 16664835 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 16664213 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 33610 10.34% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 173421 53.34% 63.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 102626 31.57% 95.25% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 8052 2.48% 97.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 7405 2.28% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 33486 10.24% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 173880 53.16% 63.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 104341 31.90% 95.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 7997 2.44% 97.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 7375 2.25% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7105969 61.95% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 17120 0.15% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 14007 0.12% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2511504 21.90% 84.18% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1426032 12.43% 96.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 45143 0.39% 97.00% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 43776 0.38% 97.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 299906 2.61% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 4756 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7097834 61.96% 62.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17086 0.15% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2506692 21.88% 84.17% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1424790 12.44% 96.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 45041 0.39% 97.00% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 43535 0.38% 97.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 299845 2.62% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 11470583 # Type of FU issued -system.cpu1.iq.rate 0.653242 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 325114 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.028343 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 39732906 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15018676 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10950208 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 226102 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 108058 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 105069 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11670188 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 120758 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 118257 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 11455956 # Type of FU issued +system.cpu1.iq.rate 0.652736 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 327079 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028551 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 39706848 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 14995495 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10932885 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 225297 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 107483 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 104737 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 11657954 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 120325 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 118525 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 553253 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 5172 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 179987 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 552207 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1214 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 5210 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 179004 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 535 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 99855 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 539 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 99906 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 182237 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 561579 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 275117 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13190679 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 58497 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2543631 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1545283 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 532703 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6805 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 266988 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 5172 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 45989 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 148806 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 194795 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 11280251 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2456871 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 190331 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 183199 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 564470 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 284501 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13175740 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 58730 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2539964 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1543921 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 532175 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7107 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 276039 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 5210 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 46730 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 149015 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 195745 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 11262138 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2450359 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 193817 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 650640 # number of nop insts executed -system.cpu1.iew.exec_refs 3907176 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1689156 # Number of branches executed -system.cpu1.iew.exec_stores 1450305 # Number of stores executed -system.cpu1.iew.exec_rate 0.642403 # Inst execution rate -system.cpu1.iew.wb_sent 11110028 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11055277 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5286560 # num instructions producing a value -system.cpu1.iew.wb_consumers 7445661 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.629590 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710019 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 2598878 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 153697 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 169517 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 16202334 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.644600 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.619525 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 650192 # number of nop insts executed +system.cpu1.iew.exec_refs 3899095 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1684701 # Number of branches executed +system.cpu1.iew.exec_stores 1448736 # Number of stores executed +system.cpu1.iew.exec_rate 0.641693 # Inst execution rate +system.cpu1.iew.wb_sent 11092333 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11037622 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5277529 # num instructions producing a value +system.cpu1.iew.wb_consumers 7434192 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.628900 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709899 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 2589103 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 153639 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 170452 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 16200161 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.644352 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.619659 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 12420063 76.66% 76.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1746761 10.78% 87.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 624490 3.85% 91.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 388127 2.40% 93.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 294767 1.82% 95.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 125393 0.77% 96.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 112323 0.69% 96.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 119344 0.74% 97.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 371066 2.29% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12420478 76.67% 76.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1746852 10.78% 87.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 623239 3.85% 91.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 386399 2.39% 93.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 294857 1.82% 95.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 125210 0.77% 96.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 112311 0.69% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 119786 0.74% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 371029 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 16202334 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 10444029 # Number of instructions committed -system.cpu1.commit.committedOps 10444029 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 16200161 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10438605 # Number of instructions committed +system.cpu1.commit.committedOps 10438605 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3355674 # Number of memory references committed -system.cpu1.commit.loads 1990378 # Number of loads committed -system.cpu1.commit.membars 48933 # Number of memory barriers committed -system.cpu1.commit.branches 1499197 # Number of branches committed -system.cpu1.commit.fp_insts 102946 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9701123 # Number of committed integer instructions. -system.cpu1.commit.function_calls 163891 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 490447 4.70% 4.70% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 6215282 59.51% 64.21% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16829 0.16% 64.37% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 13998 0.13% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1994471 19.10% 83.62% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1324148 12.68% 96.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemRead 44840 0.43% 96.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemWrite 41733 0.40% 97.13% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 299906 2.87% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3352674 # Number of memory references committed +system.cpu1.commit.loads 1987757 # Number of loads committed +system.cpu1.commit.membars 48909 # Number of memory barriers committed +system.cpu1.commit.branches 1497531 # Number of branches committed +system.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9696003 # Number of committed integer instructions. +system.cpu1.commit.function_calls 163829 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 490211 4.70% 4.70% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 6213226 59.52% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16788 0.16% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1991924 19.08% 83.62% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1323832 12.68% 96.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 44742 0.43% 96.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 41669 0.40% 97.13% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 299845 2.87% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 10444029 # Class of committed instruction -system.cpu1.commit.bw_lim_events 371066 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 28763808 # The number of ROB reads -system.cpu1.rob.rob_writes 26546353 # The number of ROB writes -system.cpu1.timesIdled 134909 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 894640 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3801408429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9958332 # Number of Instructions Simulated -system.cpu1.committedOps 9958332 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.763295 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.763295 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.567120 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.567120 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 14511646 # number of integer regfile reads -system.cpu1.int_regfile_writes 7905629 # number of integer regfile writes -system.cpu1.fp_regfile_reads 58867 # number of floating regfile reads -system.cpu1.fp_regfile_writes 57930 # number of floating regfile writes -system.cpu1.misc_regfile_reads 573957 # number of misc regfile reads -system.cpu1.misc_regfile_writes 245081 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 131073 # number of replacements -system.cpu1.dcache.tags.tagsinuse 488.756113 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3063603 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 131585 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.282312 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 49534380500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.756113 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954602 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.954602 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 10438605 # Class of committed instruction +system.cpu1.commit.bw_lim_events 371029 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 28746473 # The number of ROB reads +system.cpu1.rob.rob_writes 26517839 # The number of ROB writes +system.cpu1.timesIdled 134718 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 886458 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3803363525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9953144 # Number of Instructions Simulated +system.cpu1.committedOps 9953144 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.763329 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.763329 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.567109 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.567109 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 14490611 # number of integer regfile reads +system.cpu1.int_regfile_writes 7893529 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58631 # number of floating regfile reads +system.cpu1.fp_regfile_writes 57835 # number of floating regfile writes +system.cpu1.misc_regfile_reads 573327 # number of misc regfile reads +system.cpu1.misc_regfile_writes 245000 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 130880 # number of replacements +system.cpu1.dcache.tags.tagsinuse 488.755319 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3056587 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 131392 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.263113 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 49534102500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.755319 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954600 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.954600 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14519091 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14519091 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 1948296 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1948296 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1026442 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1026442 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40668 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 40668 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37243 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 37243 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2974738 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2974738 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2974738 # number of overall hits -system.cpu1.dcache.overall_hits::total 2974738 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 241303 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 241303 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 292103 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 292103 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5304 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5304 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3101 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3101 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 533406 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 533406 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 533406 # number of overall misses -system.cpu1.dcache.overall_misses::total 533406 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3375705500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3375705500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12203212844 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 12203212844 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54365500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 54365500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17261500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 17261500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15578918344 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15578918344 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15578918344 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15578918344 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2189599 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2189599 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318545 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1318545 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45972 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 45972 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40344 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 40344 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3508144 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3508144 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3508144 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3508144 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110204 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.110204 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221534 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.221534 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115375 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115375 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076864 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076864 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152048 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.152048 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152048 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.152048 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.488320 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.488320 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41777.088370 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41777.088370 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10249.905732 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10249.905732 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5566.430184 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5566.430184 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 29206.492510 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 29206.492510 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 720965 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 386 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 24769 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.107554 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 20.315789 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 84598 # number of writebacks -system.cpu1.dcache.writebacks::total 84598 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148074 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 148074 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243671 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 243671 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 852 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 852 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 391745 # 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number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 141661 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 141661 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 141661 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 141661 # number of overall MSHR misses +system.cpu1.dcache.tags.tag_accesses 14487576 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14487576 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 1941589 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1941589 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1026269 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1026269 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40594 # 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number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3088 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3088 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 532595 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 532595 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 532595 # number of overall misses +system.cpu1.dcache.overall_misses::total 532595 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3354943500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3354943500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12208160588 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 12208160588 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 53604000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 53604000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17137500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 17137500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15563104088 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15563104088 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15563104088 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15563104088 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2182268 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2182268 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318185 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1318185 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45854 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 45854 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40327 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 40327 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3500453 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3500453 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3500453 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3500453 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110288 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.110288 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221453 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.221453 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.114712 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.114712 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152150 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.152150 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152150 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.152150 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13939.494098 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13939.494098 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41820.799778 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41820.799778 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10190.874525 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10190.874525 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5549.708549 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5549.708549 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29221.273365 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29221.273365 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29221.273365 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29221.273365 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 720106 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 464 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 24866 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.959463 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 33.142857 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 84401 # number of writebacks +system.cpu1.dcache.writebacks::total 84401 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147677 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 147677 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243516 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 243516 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 792 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 792 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 391193 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 391193 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 391193 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 391193 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93002 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 93002 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48400 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 48400 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4468 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4468 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3088 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3088 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 141402 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 141402 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 141402 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 141402 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3157 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3375 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262260500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262260500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962212693 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962212693 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40045500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40045500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14161500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14161500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3224473193 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3224473193 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3224473193 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3224473193 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41860500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41860500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41860500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41860500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036731 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036731 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096842 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096842 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076839 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076839 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040381 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040381 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13539.354707 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13539.354707 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40514.797923 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40514.797923 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8994.946092 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8994.946092 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4568.225806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4568.225806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192020.642202 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192020.642202 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12403.111111 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12403.111111 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 256867 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.812016 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1711658 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 257379 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.650341 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1882992885500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.812016 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919555 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919555 # Average percentage of cache occupancy +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3156 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3156 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3374 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3374 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1257789500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1257789500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1961692747 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1961692747 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39632000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39632000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14049500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14049500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3219482247 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3219482247 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3219482247 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3219482247 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41842500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41842500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41842500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41842500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042617 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042617 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097440 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097440 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076574 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076574 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040395 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040395 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13524.327434 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13524.327434 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40530.841880 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40530.841880 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8870.188004 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8870.188004 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.708549 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.708549 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191938.073394 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191938.073394 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12401.452282 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12401.452282 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 256309 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.814625 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1714023 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 256821 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.673999 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1883968823500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.814625 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919560 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.919560 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2238596 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2238596 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 1711658 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1711658 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1711658 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1711658 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1711658 # number of overall hits -system.cpu1.icache.overall_hits::total 1711658 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 269479 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 269479 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 269479 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 269479 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 269479 # number of overall misses -system.cpu1.icache.overall_misses::total 269479 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3760599998 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3760599998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3760599998 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3760599998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3760599998 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3760599998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1981137 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1981137 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1981137 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1981137 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1981137 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1981137 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136022 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.136022 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136022 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.136022 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136022 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.136022 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13955.076269 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13955.076269 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13955.076269 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13955.076269 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 535 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2239848 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2239848 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 1714023 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1714023 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1714023 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1714023 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1714023 # number of overall hits +system.cpu1.icache.overall_hits::total 1714023 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 268930 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 268930 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 268930 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 268930 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 268930 # number of overall misses +system.cpu1.icache.overall_misses::total 268930 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3748012499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3748012499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3748012499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3748012499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3748012499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3748012499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1982953 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1982953 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1982953 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1982953 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1982953 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1982953 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.135621 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.135621 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.135621 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.135621 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.135621 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.135621 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13936.758632 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13936.758632 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13936.758632 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13936.758632 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13936.758632 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13936.758632 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 558 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 46 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.382979 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.130435 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 256867 # number of writebacks -system.cpu1.icache.writebacks::total 256867 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12020 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 12020 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 12020 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 12020 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 12020 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 12020 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257459 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 257459 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 257459 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 257459 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 257459 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 257459 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3369785998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3369785998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3369785998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3369785998 # 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average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 256309 # number of writebacks +system.cpu1.icache.writebacks::total 256309 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12035 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 12035 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 12035 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 12035 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 12035 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 12035 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 256895 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 256895 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 256895 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 256895 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 256895 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 256895 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3358325499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3358325499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3358325499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3358325499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3358325499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3358325499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129552 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.129552 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.129552 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13072.755402 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13072.755402 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13072.755402 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1583,12 +1585,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7374 # Transaction distribution system.iobus.trans_dist::ReadResp 7374 # Transaction distribution -system.iobus.trans_dist::WriteReq 54619 # Transaction distribution -system.iobus.trans_dist::WriteResp 54619 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11924 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54617 # Transaction distribution +system.iobus.trans_dist::WriteResp 54617 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11920 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1597,11 +1599,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40524 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40520 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123986 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123982 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47680 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1610,50 +1612,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73922 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 73906 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735578 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12373500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2735562 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12368500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 820500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 176500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14090000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14153500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2829500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2825500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6041501 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6058000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 89000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216274759 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216256520 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27455000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.506657 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.514549 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714262526000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.506657 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031666 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031666 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714263350000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.514549 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.032159 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.032159 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375579 # Number of tag accesses system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1662,14 +1664,14 @@ system.iocache.demand_misses::tsunami.ide 41731 # n system.iocache.demand_misses::total 41731 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22653383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22653383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4913989376 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4913989376 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4936642759 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4936642759 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4936642759 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4936642759 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22652883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22652883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4915863637 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4915863637 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4938516520 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4938516520 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4938516520 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4938516520 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1686,19 +1688,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126555.212291 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126555.212291 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118261.199846 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118261.199846 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118296.775994 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118296.775994 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 945 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126552.418994 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126552.418994 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118306.306243 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118306.306243 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118341.676931 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118341.676931 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118341.676931 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118341.676931 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 135 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 173.750000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks @@ -1710,14 +1712,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41731 system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13703383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13703383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2833958851 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2833958851 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2847662234 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2847662234 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2847662234 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2847662234 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13702883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13702883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2835827584 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2835827584 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2849530467 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2849530467 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2849530467 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2849530467 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1726,454 +1728,455 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76555.212291 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76555.212291 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68202.706272 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68202.706272 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 345934 # number of replacements -system.l2c.tags.tagsinuse 65423.183339 # Cycle average of tags in use -system.l2c.tags.total_refs 4331268 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 411456 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.526686 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6416563000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 293.472249 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5322.167822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58815.337446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 207.084290 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 785.121532 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004478 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081210 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.897451 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003160 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011980 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998279 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76552.418994 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76552.418994 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68247.679630 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68247.679630 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68283.301790 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68283.301790 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68283.301790 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68283.301790 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 345895 # number of replacements +system.l2c.tags.tagsinuse 65423.250509 # Cycle average of tags in use +system.l2c.tags.total_refs 4330734 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 411417 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.526386 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6416604000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 292.398395 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5320.578215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58825.194930 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 208.100344 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 776.978626 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.004462 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081186 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.897601 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003175 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011856 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998280 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1689 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9122 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52734 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1663 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1868 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5665 # 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mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013295 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.274178 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022799 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254149 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.162692 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.162692 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 38750 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18750 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32083.333333 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002459 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.003318 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.002756 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002141 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001033 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.429093 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280466 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.407675 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013287 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273696 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022883 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253766 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305421 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.108781 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.162658 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305421 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.108781 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.162658 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 41642.857143 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18900 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32166.666667 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93283.663814 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116991.422972 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 95637.198290 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 91029.359838 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71548.632457 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106013.245033 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71794.968708 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210679.661746 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179520.642202 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209735.580264 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87043.998342 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11595.703704 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74476.729839 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 852121 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 399760 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 540 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93340.010218 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116972.351186 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 95682.869096 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90348.831118 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71395.052499 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 104363.497712 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71631.289445 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77689.265685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115204.469314 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79438.271672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77689.265685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115204.469314 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79438.271672 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210695.499498 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179438.073394 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209748.436414 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87055.697027 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11593.805572 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74488.647581 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 851998 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 399673 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 538 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 297263 # Transaction distribution -system.membus.trans_dist::WriteReq 13067 # Transaction distribution -system.membus.trans_dist::WriteResp 13067 # Transaction distribution -system.membus.trans_dist::WritebackDirty 123600 # Transaction distribution -system.membus.trans_dist::CleanEvict 263134 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6631 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5160 # Transaction distribution +system.membus.trans_dist::ReadResp 297108 # Transaction distribution +system.membus.trans_dist::WriteReq 13065 # Transaction distribution +system.membus.trans_dist::WriteResp 13065 # Transaction distribution +system.membus.trans_dist::WritebackDirty 123588 # Transaction distribution +system.membus.trans_dist::CleanEvict 263109 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6612 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5150 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 121851 # Transaction distribution -system.membus.trans_dist::ReadExResp 121443 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 290113 # Transaction distribution +system.membus.trans_dist::ReadExReq 121960 # Transaction distribution +system.membus.trans_dist::ReadExResp 121558 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289958 # Transaction distribution system.membus.trans_dist::BadAddressError 45 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 134 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40524 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40520 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179462 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1220226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1220072 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1303671 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73922 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31560064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31633986 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1303517 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73906 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31556864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31630770 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34292226 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 12662 # Total snoops (count) -system.membus.snoopTraffic 28800 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 485569 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001425 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037724 # Request fanout histogram +system.membus.pkt_size::total 34289010 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 12625 # Total snoops (count) +system.membus.snoopTraffic 28672 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 485492 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001421 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037673 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 484877 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 692 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 484802 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 690 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 485569 # Request fanout histogram -system.membus.reqLayer0.occupancy 36441999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 485492 # Request fanout histogram +system.membus.reqLayer0.occupancy 36514000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1353891077 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1353680299 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 56500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 56000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2179677750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2179395750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1104580 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1105081 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5103299 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2546186 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 356313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1076 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5103450 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2546310 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 356575 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2260964 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13067 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13067 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 904251 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1149139 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 825400 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10906 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6131 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 17037 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 299755 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 299755 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1150512 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1103306 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2260935 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13065 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13065 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 904465 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1148228 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 826225 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10843 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6117 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16960 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 299845 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 299845 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1149557 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1104232 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution system.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2678185 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3810494 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771737 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 418186 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7678602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114248448 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127253332 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32913792 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13701358 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 288116930 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 382331 # Total snoops (count) -system.toL2Bus.snoopTraffic 6809920 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2937042 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.126206 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.332589 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2677077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3814281 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 770058 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7678991 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114202560 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127366412 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32842432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13680230 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 288091634 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 382034 # Total snoops (count) +system.toL2Bus.snoopTraffic 6794496 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2936985 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.126280 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.332605 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2566846 87.40% 87.40% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 369740 12.59% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 436 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2566512 87.39% 87.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 370085 12.60% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 367 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 21 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2937042 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4539664918 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2936985 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4539093837 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 302885 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 303384 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1341208229 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1340375720 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1910262297 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1912124205 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 387640565 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 386934286 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 217884535 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 217615473 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2205,142 +2208,142 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6478 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 176731 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 62783 40.27% 40.27% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6479 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 176756 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 62790 40.27% 40.27% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.24% 41.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 182 0.12% 41.71% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 90863 58.29% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 155886 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 61769 49.18% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.53% 50.82% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 182 0.14% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 61587 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864292107000 97.65% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64306500 0.00% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 577089500 0.03% 97.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 88747000 0.00% 97.69% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 44160796000 2.31% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1909183046000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983849 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_count::22 1928 1.24% 41.59% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 90883 58.29% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 155913 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 61775 49.18% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1928 1.53% 50.82% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 61594 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 125609 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865241808000 97.65% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64326000 0.00% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 577244500 0.03% 97.68% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 87620000 0.00% 97.69% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 44188694000 2.31% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1910159692500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983835 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.677801 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.805691 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.677729 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.805635 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 294 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3351 2.05% 2.23% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 149332 91.35% 93.61% # number of callpals executed -system.cpu0.kern.callpal::rdps 5685 3.48% 97.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed +system.cpu0.kern.callpal::swpipl 149358 91.35% 93.61% # number of callpals executed +system.cpu0.kern.callpal::rdps 5686 3.48% 97.09% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rti 4313 2.64% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4314 2.64% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 163481 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6669 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1070 # number of protection mode switches +system.cpu0.kern.callpal::total 163506 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6667 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1071 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1070 -system.cpu0.kern.mode_good::user 1070 +system.cpu0.kern.mode_good::kernel 1071 +system.cpu0.kern.mode_good::user 1071 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.160444 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.160642 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.276522 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1907148784500 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1683022000 0.09% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.276816 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1908119380500 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1686628500 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3352 # number of times the context was actually changed +system.cpu0.kern.swap_context 3350 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2546 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 62928 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 19570 37.60% 37.60% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 3.70% 41.30% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 294 0.56% 41.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 30260 58.14% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 52049 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 19207 47.61% 47.61% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 4.77% 52.39% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 294 0.73% 53.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 18913 46.89% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 40339 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874881279000 98.19% 98.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 565111500 0.03% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 141720000 0.01% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33895004500 1.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1909483115000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981451 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2544 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 62917 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 19565 37.60% 37.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1926 3.70% 41.30% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 30256 58.14% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 52040 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 19203 47.61% 47.61% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1926 4.78% 52.39% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 18910 46.89% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 40332 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1875855078000 98.19% 98.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 566007000 0.03% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 141529500 0.01% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33893640500 1.77% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1910456255000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981498 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625017 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.775020 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.625000 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.775019 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 182 0.33% 0.34% # number of callpals executed +system.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1230 2.25% 2.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed system.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed -system.cpu1.kern.callpal::swpipl 46579 85.30% 87.91% # number of callpals executed -system.cpu1.kern.callpal::rdps 3079 5.64% 93.55% # number of callpals executed +system.cpu1.kern.callpal::swpipl 46571 85.30% 87.91% # number of callpals executed +system.cpu1.kern.callpal::rdps 3080 5.64% 93.55% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed system.cpu1.kern.callpal::wrusp 6 0.01% 93.56% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.56% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::rti 3250 5.95% 99.52% # number of callpals executed +system.cpu1.kern.callpal::rti 3249 5.95% 99.52% # number of callpals executed system.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 54607 # number of callpals executed +system.cpu1.kern.callpal::total 54596 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1700 # number of protection mode switches -system.cpu1.kern.mode_switch::user 670 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2433 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 890 -system.cpu1.kern.mode_good::user 670 -system.cpu1.kern.mode_good::idle 220 -system.cpu1.kern.mode_switch_good::kernel 0.523529 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch::user 669 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2431 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 888 +system.cpu1.kern.mode_good::user 669 +system.cpu1.kern.mode_good::idle 219 +system.cpu1.kern.mode_switch_good::kernel 0.522353 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.090423 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.370602 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5328500500 0.28% 0.28% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1057436000 0.06% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1903097170500 99.67% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1231 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.090086 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.370000 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 5325548500 0.28% 0.28% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1057057500 0.06% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1904073641000 99.67% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1229 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 5af666630..df3a97326 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.865010 # Number of seconds simulated -sim_ticks 1865009748000 # Number of ticks simulated -final_tick 1865009748000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.865014 # Number of seconds simulated +sim_ticks 1865014104500 # Number of ticks simulated +final_tick 1865014104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235871 # Simulator instruction rate (inst/s) -host_op_rate 235870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8303287371 # Simulator tick rate (ticks/s) -host_mem_usage 337912 # Number of bytes of host memory used -host_seconds 224.61 # Real time elapsed on the host -sim_insts 52979108 # Number of instructions simulated -sim_ops 52979108 # Number of ops (including micro ops) simulated +host_inst_rate 231832 # Simulator instruction rate (inst/s) +host_op_rate 231832 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8163594872 # Simulator tick rate (ticks/s) +host_mem_usage 339292 # Number of bytes of host memory used +host_seconds 228.46 # Real time elapsed on the host +sim_insts 52963270 # Number of instructions simulated +sim_ops 52963270 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 962240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24880192 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 962304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25843392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 962240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 962240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15035 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388753 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25843264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 962304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 962304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7514304 # Number of bytes written to this memory +system.physmem.bytes_written::total 7514304 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403803 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 515944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13340516 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403801 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117411 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117411 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 515977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13340382 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13856974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 515944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4030126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4030126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4030126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 515944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13340516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13856873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 515977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4029087 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4029087 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4029087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 515977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13340382 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17887100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403803 # Number of read requests accepted -system.physmem.writeReqs 117441 # Number of write requests accepted -system.physmem.readBursts 403803 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117441 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25835712 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 7515136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25843392 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7516224 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17885960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403801 # Number of read requests accepted +system.physmem.writeReqs 117411 # Number of write requests accepted +system.physmem.readBursts 403801 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117411 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25836480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 7512704 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25843264 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7514304 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25444 # Per bank write bursts -system.physmem.perBankRdBursts::1 25611 # Per bank write bursts -system.physmem.perBankRdBursts::2 25628 # Per bank write bursts -system.physmem.perBankRdBursts::3 25719 # Per bank write bursts -system.physmem.perBankRdBursts::4 25100 # Per bank write bursts -system.physmem.perBankRdBursts::5 25088 # Per bank write bursts -system.physmem.perBankRdBursts::6 24758 # Per bank write bursts -system.physmem.perBankRdBursts::7 24649 # Per bank write bursts -system.physmem.perBankRdBursts::8 24903 # Per bank write bursts -system.physmem.perBankRdBursts::9 25188 # Per bank write bursts -system.physmem.perBankRdBursts::10 25284 # Per bank write bursts -system.physmem.perBankRdBursts::11 25005 # Per bank write bursts -system.physmem.perBankRdBursts::12 24375 # Per bank write bursts -system.physmem.perBankRdBursts::13 25430 # Per bank write bursts +system.physmem.perBankRdBursts::0 25442 # Per bank write bursts +system.physmem.perBankRdBursts::1 25616 # Per bank write bursts +system.physmem.perBankRdBursts::2 25500 # Per bank write bursts +system.physmem.perBankRdBursts::3 25612 # Per bank write bursts +system.physmem.perBankRdBursts::4 25113 # Per bank write bursts +system.physmem.perBankRdBursts::5 25182 # Per bank write bursts +system.physmem.perBankRdBursts::6 24743 # Per bank write bursts +system.physmem.perBankRdBursts::7 24567 # Per bank write bursts +system.physmem.perBankRdBursts::8 25026 # Per bank write bursts +system.physmem.perBankRdBursts::9 25298 # Per bank write bursts +system.physmem.perBankRdBursts::10 25283 # Per bank write bursts +system.physmem.perBankRdBursts::11 25011 # Per bank write bursts +system.physmem.perBankRdBursts::12 24384 # Per bank write bursts +system.physmem.perBankRdBursts::13 25424 # Per bank write bursts system.physmem.perBankRdBursts::14 25804 # Per bank write bursts -system.physmem.perBankRdBursts::15 25697 # Per bank write bursts -system.physmem.perBankWrBursts::0 7804 # Per bank write bursts -system.physmem.perBankWrBursts::1 7583 # Per bank write bursts -system.physmem.perBankWrBursts::2 7900 # Per bank write bursts -system.physmem.perBankWrBursts::3 7698 # Per bank write bursts -system.physmem.perBankWrBursts::4 7224 # Per bank write bursts -system.physmem.perBankWrBursts::5 7092 # Per bank write bursts -system.physmem.perBankWrBursts::6 6759 # Per bank write bursts -system.physmem.perBankWrBursts::7 6515 # Per bank write bursts -system.physmem.perBankWrBursts::8 7053 # Per bank write bursts -system.physmem.perBankWrBursts::9 6824 # Per bank write bursts +system.physmem.perBankRdBursts::15 25690 # Per bank write bursts +system.physmem.perBankWrBursts::0 7803 # Per bank write bursts +system.physmem.perBankWrBursts::1 7588 # Per bank write bursts +system.physmem.perBankWrBursts::2 7778 # Per bank write bursts +system.physmem.perBankWrBursts::3 7603 # Per bank write bursts +system.physmem.perBankWrBursts::4 7231 # Per bank write bursts +system.physmem.perBankWrBursts::5 7190 # Per bank write bursts +system.physmem.perBankWrBursts::6 6745 # Per bank write bursts +system.physmem.perBankWrBursts::7 6418 # Per bank write bursts +system.physmem.perBankWrBursts::8 7146 # Per bank write bursts +system.physmem.perBankWrBursts::9 6920 # Per bank write bursts system.physmem.perBankWrBursts::10 7197 # Per bank write bursts system.physmem.perBankWrBursts::11 7005 # Per bank write bursts -system.physmem.perBankWrBursts::12 6955 # Per bank write bursts -system.physmem.perBankWrBursts::13 7882 # Per bank write bursts +system.physmem.perBankWrBursts::12 6963 # Per bank write bursts +system.physmem.perBankWrBursts::13 7878 # Per bank write bursts system.physmem.perBankWrBursts::14 8018 # Per bank write bursts -system.physmem.perBankWrBursts::15 7915 # Per bank write bursts +system.physmem.perBankWrBursts::15 7903 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 65 # Number of times write queue was full causing retry -system.physmem.totGap 1865004470500 # Total gap between requests +system.physmem.numWrRetry 61 # Number of times write queue was full causing retry +system.physmem.totGap 1865008869500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403803 # Read request sizes (log2) +system.physmem.readPktSize::6 403801 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117441 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117411 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -149,115 +149,116 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 543.503536 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 333.365701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.323842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13476 21.96% 21.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10707 17.45% 39.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4479 7.30% 46.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2678 4.36% 51.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2195 3.58% 54.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1843 3.00% 57.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1874 3.05% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1552 2.53% 63.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22558 36.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61362 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.231977 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2938.731055 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5157 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 139 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61269 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 544.301360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 334.095290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.294475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13441 21.94% 21.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10649 17.38% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4420 7.21% 46.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2704 4.41% 50.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2252 3.68% 54.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1833 2.99% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1848 3.02% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1534 2.50% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22588 36.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61269 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5165 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.156438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2937.375866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5162 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.756589 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.921420 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.589297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4641 89.94% 89.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 34 0.66% 90.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 173 3.35% 93.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 9 0.17% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 2 0.04% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 16 0.31% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.16% 94.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 3 0.06% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 29 0.56% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.08% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 150 2.91% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 19 0.37% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 6 0.12% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.10% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 7 0.14% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 7 0.14% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.10% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 10 0.19% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 13 0.25% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.08% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.08% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads -system.physmem.totQLat 7817102750 # Total ticks spent queuing -system.physmem.totMemAccLat 15386159000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018415000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19364.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5165 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5165 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.727202 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.973066 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.761118 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4630 89.64% 89.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 34 0.66% 90.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 183 3.54% 93.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 6 0.12% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.06% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 17 0.33% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 3 0.06% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 30 0.58% 95.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.08% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 158 3.06% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 16 0.31% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 13 0.25% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 4 0.08% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.12% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.12% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.12% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 9 0.17% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 8 0.15% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 5 0.10% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5165 # Writes before turning the bus around for reads +system.physmem.totQLat 7762770500 # Total ticks spent queuing +system.physmem.totMemAccLat 15332051750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19229.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38114.46 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37979.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s @@ -266,88 +267,88 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing -system.physmem.readRowHits 364427 # Number of row buffer hits during reads -system.physmem.writeRowHits 95317 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing +system.physmem.readRowHits 364450 # Number of row buffer hits during reads +system.physmem.writeRowHits 95361 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.16 # Row buffer hit rate for writes -system.physmem.avgGap 3577987.41 # Average gap between requests -system.physmem.pageHitRate 88.22 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 216106380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 114863265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1442258580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 305761500 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4158564390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 232346880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8004158310 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4220231520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 438996708360 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 461312299845 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.351146 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1855244620250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 361602000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1537874000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1826739481250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 10990187750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7827619250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 17552983750 # Time in different power states -system.physmem_1.actEnergy 222025440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 118005525 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1440038040 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 307191780 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4104344850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 228211680 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8096599200 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4247999520 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 438951182175 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 461336536560 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.364142 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1855407985250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 350582750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1537736000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1826594899250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11062498750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7708202750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 17755828500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 19556212 # Number of BP lookups -system.cpu.branchPred.condPredicted 16618547 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 593854 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12802975 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5420040 # Number of BTB hits +system.physmem.writeRowHitRate 81.22 # Row buffer hit rate for writes +system.physmem.avgGap 3578215.52 # Average gap between requests +system.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 215406660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 114491355 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1440673500 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 304618320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3636824880.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4141323030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240547200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8014976340 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4268063520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 438971983965 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 461349368400 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.370445 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1855266278000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 380549250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1544966000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1826613361750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 11114845500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7783583250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 17576798750 # Time in different power states +system.physmem_1.actEnergy 222061140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 118024500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1441708800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 308136600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3631907760.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4166934840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 235115520 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8062896810 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4253243040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 438933503490 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 461375149740 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.384267 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1855254817500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 370314000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1542730000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1826502260750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11076094000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7841044250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 17681661500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 19565204 # Number of BP lookups +system.cpu.branchPred.condPredicted 16626727 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 606351 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12911299 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5422453 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 42.334223 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1126473 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42524 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6261380 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 563797 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5697583 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 265016 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 41.997734 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1125914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 42947 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6343232 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 564019 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5779213 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 264491 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 11131129 # DTB read hits -system.cpu.dtb.read_misses 49734 # DTB read misses -system.cpu.dtb.read_acv 613 # DTB read access violations -system.cpu.dtb.read_accesses 995788 # DTB read accesses -system.cpu.dtb.write_hits 6783534 # DTB write hits -system.cpu.dtb.write_misses 12230 # DTB write misses -system.cpu.dtb.write_acv 435 # DTB write access violations -system.cpu.dtb.write_accesses 345368 # DTB write accesses -system.cpu.dtb.data_hits 17914663 # DTB hits -system.cpu.dtb.data_misses 61964 # DTB misses -system.cpu.dtb.data_acv 1048 # DTB access violations -system.cpu.dtb.data_accesses 1341156 # DTB accesses -system.cpu.itb.fetch_hits 1815343 # ITB hits -system.cpu.itb.fetch_misses 10369 # ITB misses -system.cpu.itb.fetch_acv 759 # ITB acv -system.cpu.itb.fetch_accesses 1825712 # ITB accesses +system.cpu.dtb.read_hits 11109232 # DTB read hits +system.cpu.dtb.read_misses 50748 # DTB read misses +system.cpu.dtb.read_acv 615 # DTB read access violations +system.cpu.dtb.read_accesses 993788 # DTB read accesses +system.cpu.dtb.write_hits 6757496 # DTB write hits +system.cpu.dtb.write_misses 12693 # DTB write misses +system.cpu.dtb.write_acv 420 # DTB write access violations +system.cpu.dtb.write_accesses 345501 # DTB write accesses +system.cpu.dtb.data_hits 17866728 # DTB hits +system.cpu.dtb.data_misses 63441 # DTB misses +system.cpu.dtb.data_acv 1035 # DTB access violations +system.cpu.dtb.data_accesses 1339289 # DTB accesses +system.cpu.itb.fetch_hits 1817930 # ITB hits +system.cpu.itb.fetch_misses 10423 # ITB misses +system.cpu.itb.fetch_acv 754 # ITB acv +system.cpu.itb.fetch_accesses 1828353 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -360,270 +361,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12878 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 279575452.943004 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 438968142.754116 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 71000 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12882 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6441 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 279499621.875485 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 438940062.434372 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6441 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 80500 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 64823406500 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1800186341500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 129653253 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6441 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 64757040000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1800257064500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 129520522 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30226306 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85761758 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19556212 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7110310 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 91828962 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1682802 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 214 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 31116 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 206972 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 428466 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9929941 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 408418 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 123563934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.694068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.023639 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30117726 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85842784 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19565204 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7112386 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 91831627 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1707334 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 94 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 30324 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 206515 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 432806 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9953050 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 416768 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 123473258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.695234 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.025215 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 107716203 87.17% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1033964 0.84% 88.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2108086 1.71% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 968916 0.78% 90.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2910075 2.36% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 665807 0.54% 93.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 808204 0.65% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1035117 0.84% 94.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6317562 5.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 107617936 87.16% 87.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1029887 0.83% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2106014 1.71% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 969195 0.78% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2907839 2.36% 92.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 668408 0.54% 93.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 818971 0.66% 94.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1034002 0.84% 94.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6321006 5.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123563934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150835 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661470 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24256271 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86199481 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 10262767 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2038754 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 806660 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 739137 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 35567 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 74091152 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 113387 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 806660 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25262123 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 56608165 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20046193 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11227977 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9612814 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 71075345 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 200089 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2115758 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 264182 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5312560 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 47887128 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 85631010 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 85450068 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168489 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38179018 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9708102 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1730208 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 277739 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13892500 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 11673351 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7232744 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1724750 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1099672 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 62753291 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2208700 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 60568136 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 94532 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11982878 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5316307 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1547451 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123563934 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.490176 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.236204 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 123473258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.151059 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.662774 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24152038 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86201336 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 10258063 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2042752 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 819068 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 5235547 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 36008 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 74118733 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 112337 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 819068 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25161583 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 56623083 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20020475 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11228852 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9620195 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 71027053 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 203339 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2122213 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 263594 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5326402 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 47839712 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 85552570 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 85371726 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168391 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38166163 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9673541 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1731851 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 279206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13863805 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 11669742 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7218714 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1729922 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1107908 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 62661067 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2212545 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 60426230 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 90696 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11910337 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5399466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1551308 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 123473258 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.489387 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.234720 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 99014105 80.13% 80.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10422330 8.43% 88.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4419921 3.58% 92.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3179961 2.57% 94.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3252538 2.63% 97.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1603803 1.30% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1099991 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 433312 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 137973 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 98959132 80.15% 80.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10414953 8.43% 88.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4418122 3.58% 92.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3174360 2.57% 94.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3248671 2.63% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1596633 1.29% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1092968 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 431056 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 137363 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123563934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 123473258 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206621 16.55% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 610635 48.92% 65.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372589 29.85% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 31948 2.56% 97.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 26502 2.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 204093 16.54% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 604376 48.98% 65.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 366984 29.74% 95.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 31970 2.59% 97.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 26536 2.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7279 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 40937281 67.59% 67.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62136 0.10% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38562 0.06% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 11522525 19.02% 86.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6750152 11.14% 97.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 156092 0.26% 98.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 141347 0.23% 98.43% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 40835249 67.58% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62139 0.10% 67.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38557 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 11506324 19.04% 86.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6726484 11.13% 97.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 156184 0.26% 98.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 141292 0.23% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949086 1.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 60568136 # Type of FU issued -system.cpu.iq.rate 0.467155 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1248295 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020610 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 245303428 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 76606948 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 58345447 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 739604 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 359470 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 336798 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 61411065 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 398087 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 692317 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 60426230 # Type of FU issued +system.cpu.iq.rate 0.466538 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1233959 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020421 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 244910582 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 76445733 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 58177679 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 739790 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 359586 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 336759 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 61254735 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 398175 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 690768 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2580830 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3930 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22198 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 854795 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2579745 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4605 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21941 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 842112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17998 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 456632 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18009 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 459546 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 806660 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 52694504 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1340713 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 68945664 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 202125 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 11673351 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7232744 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1959731 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45749 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1091638 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22198 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 229988 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 630611 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 860599 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 59710531 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 11213503 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 857604 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 819068 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 52732826 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1310921 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 68860028 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 210874 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 11669742 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7218714 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1962223 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 46667 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1061185 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21941 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 239076 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 633747 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 872823 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 59548676 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 11192398 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 877553 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3983673 # number of nop insts executed -system.cpu.iew.exec_refs 18029484 # number of memory reference insts executed -system.cpu.iew.exec_branches 9387402 # Number of branches executed -system.cpu.iew.exec_stores 6815981 # Number of stores executed -system.cpu.iew.exec_rate 0.460540 # Inst execution rate -system.cpu.iew.wb_sent 58927059 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 58682245 # cumulative count of insts written-back -system.cpu.iew.wb_producers 29779151 # num instructions producing a value -system.cpu.iew.wb_consumers 41279871 # num instructions consuming a value -system.cpu.iew.wb_rate 0.452609 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.721396 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12584544 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661249 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 770143 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 121389515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.462724 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.395132 # Number of insts commited each cycle +system.cpu.iew.exec_nop 3986416 # number of nop insts executed +system.cpu.iew.exec_refs 17982691 # number of memory reference insts executed +system.cpu.iew.exec_branches 9367788 # Number of branches executed +system.cpu.iew.exec_stores 6790293 # Number of stores executed +system.cpu.iew.exec_rate 0.459762 # Inst execution rate +system.cpu.iew.wb_sent 58762094 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 58514438 # cumulative count of insts written-back +system.cpu.iew.wb_producers 29700638 # num instructions producing a value +system.cpu.iew.wb_consumers 41179298 # num instructions consuming a value +system.cpu.iew.wb_rate 0.451777 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.721252 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12514858 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661237 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 782772 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121281996 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462997 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.395862 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 101523124 83.63% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7984339 6.58% 90.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4194668 3.46% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2261790 1.86% 95.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1754136 1.45% 96.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 633873 0.52% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 481376 0.40% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 513083 0.42% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2043126 1.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 101434078 83.63% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7974018 6.57% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4186796 3.45% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2256770 1.86% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1754187 1.45% 96.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 639315 0.53% 97.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 479528 0.40% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 513600 0.42% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2043704 1.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 121389515 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56169799 # Number of instructions committed -system.cpu.commit.committedOps 56169799 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 121281996 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56153243 # Number of instructions committed +system.cpu.commit.committedOps 56153243 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470470 # Number of memory references committed -system.cpu.commit.loads 9092521 # Number of loads committed -system.cpu.commit.membars 226360 # Number of memory barriers committed -system.cpu.commit.branches 8440690 # Number of branches committed +system.cpu.commit.refs 15466599 # Number of memory references committed +system.cpu.commit.loads 9089997 # Number of loads committed +system.cpu.commit.membars 226363 # Number of memory barriers committed +system.cpu.commit.branches 8438860 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52019202 # Number of committed integer instructions. -system.cpu.commit.function_calls 740566 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197964 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36217526 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60675 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52003390 # Number of committed integer instructions. +system.cpu.commit.function_calls 740372 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197246 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36205593 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60678 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -653,39 +653,39 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9174285 16.33% 86.69% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6245839 11.12% 97.81% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9171764 16.33% 86.69% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6244492 11.12% 97.81% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949086 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56169799 # Class of committed instruction -system.cpu.commit.bw_lim_events 2043126 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 187851195 # The number of ROB reads -system.cpu.rob.rob_writes 139687376 # The number of ROB writes -system.cpu.timesIdled 556781 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6089319 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3600366244 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979108 # Number of Instructions Simulated -system.cpu.committedOps 52979108 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.447252 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.447252 # CPI: Total CPI of All Threads -system.cpu.ipc 0.408622 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.408622 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 77910051 # number of integer regfile reads -system.cpu.int_regfile_writes 42617580 # number of integer regfile writes -system.cpu.fp_regfile_reads 166665 # number of floating regfile reads -system.cpu.fp_regfile_writes 175716 # number of floating regfile writes -system.cpu.misc_regfile_reads 2001313 # number of misc regfile reads -system.cpu.misc_regfile_writes 939513 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1405851 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994060 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 12629128 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1406363 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.979992 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 28232500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994060 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 56153243 # Class of committed instruction +system.cpu.commit.bw_lim_events 2043704 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 187656858 # The number of ROB reads +system.cpu.rob.rob_writes 139533948 # The number of ROB writes +system.cpu.timesIdled 550447 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6047264 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3600507688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52963270 # Number of Instructions Simulated +system.cpu.committedOps 52963270 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.445478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.445478 # CPI: Total CPI of All Threads +system.cpu.ipc 0.408918 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.408918 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 77682847 # number of integer regfile reads +system.cpu.int_regfile_writes 42491451 # number of integer regfile writes +system.cpu.fp_regfile_reads 166573 # number of floating regfile reads +system.cpu.fp_regfile_writes 175777 # number of floating regfile writes +system.cpu.misc_regfile_reads 2001872 # number of misc regfile reads +system.cpu.misc_regfile_writes 939479 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1405824 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994108 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 12609719 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1406336 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.966363 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 28054500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994108 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -693,507 +693,501 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 67152661 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 67152661 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 8020035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8020035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4180765 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4180765 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 212398 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 212398 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215680 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215680 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 12200800 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12200800 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 12200800 # number of overall hits -system.cpu.dcache.overall_hits::total 12200800 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1817327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1817327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1966706 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1966706 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23570 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23570 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 93 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 93 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3784033 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3784033 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3784033 # number of overall misses -system.cpu.dcache.overall_misses::total 3784033 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45159601500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45159601500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 92703832258 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 92703832258 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 420302500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 420302500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1299500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 1299500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137863433758 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137863433758 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137863433758 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137863433758 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9837362 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9837362 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147471 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147471 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235968 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235968 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215773 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215773 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15984833 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15984833 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15984833 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15984833 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184737 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184737 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319921 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.319921 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099886 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099886 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000431 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000431 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.236726 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.236726 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.236726 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.236726 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24849.463800 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24849.463800 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47136.599094 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47136.599094 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17832.095885 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17832.095885 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13973.118280 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13973.118280 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36432.936435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36432.936435 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4933871 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2725 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 132268 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.302076 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 97.321429 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 844182 # number of writebacks -system.cpu.dcache.writebacks::total 844182 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717105 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 717105 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1677249 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1677249 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6763 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6763 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2394354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2394354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2394354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2394354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100222 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1100222 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289457 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289457 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16807 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16807 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 93 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 93 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1389679 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1389679 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1389679 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1389679 # number of overall MSHR misses +system.cpu.dcache.tags.tag_accesses 67057386 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 67057386 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 8001397 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8001397 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4179263 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4179263 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 213150 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 213150 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215702 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215702 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 12180660 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 12180660 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 12180660 # number of overall hits +system.cpu.dcache.overall_hits::total 12180660 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1813374 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1813374 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1966870 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1966870 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22944 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22944 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 62 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 62 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3780244 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3780244 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3780244 # number of overall misses +system.cpu.dcache.overall_misses::total 3780244 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45111482000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45111482000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 92228872060 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 92228872060 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 421566000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 421566000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 865000 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14384695133 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14384695133 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 210983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 210983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1206500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1206500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47398255633 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47398255633 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47398255633 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47398255633 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535352000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535352000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535352000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535352000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111841 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111841 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047086 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047086 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071226 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071226 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000431 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000431 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.086937 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.086937 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30006.271916 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30006.271916 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49695.447452 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49695.447452 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12553.281371 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12553.281371 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12973.118280 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12973.118280 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221551.515152 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221551.515152 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92888.378002 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92888.378002 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1077480 # number of replacements -system.cpu.icache.tags.tagsinuse 509.004193 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8783075 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1077988 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.147656 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 30284131500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.004193 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994149 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994149 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33019179500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33019179500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14332081529 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14332081529 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 803000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 803000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47351261029 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47351261029 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47351261029 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47351261029 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535277500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535277500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535277500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535277500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.112147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.112147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.069328 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.069328 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000287 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000287 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087093 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087093 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087093 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087093 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29998.346053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29998.346053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49526.342353 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49526.342353 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12531.066716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12531.066716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12951.612903 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12951.612903 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34063.621402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34063.621402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34063.621402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34063.621402 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221540.764791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221540.764791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92883.870773 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92883.870773 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1070370 # number of replacements +system.cpu.icache.tags.tagsinuse 509.026702 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8813001 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1070878 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.229697 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 30284278500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.026702 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994193 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994193 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11008225 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11008225 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 8783075 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8783075 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8783075 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8783075 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8783075 # number of overall hits -system.cpu.icache.overall_hits::total 8783075 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209049.278499 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209049.278499 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87646.651340 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87646.651340 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4968207 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483449 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 5093 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 951 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 951 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 348000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 348000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10865472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10865472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1368867500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1368867500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19644703500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19644703500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1368867500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30510175500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31879043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1368867500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30510175500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31879043000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448637000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448637000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448637000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448637000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.142857 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.142857 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382640 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382640 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014041 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248050 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248050 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.163176 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276738 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.163176 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 34800 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34800 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94726.182173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94726.182173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91033.284565 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91033.284565 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71566.447234 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71566.447234 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91033.284565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78392.023381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78862.259021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91033.284565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78392.023381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78862.259021 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209038.528139 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209038.528139 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87642.144110 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87642.144110 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4953861 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2476312 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4344 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 953 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 953 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2191810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2184804 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 920111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1077480 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 824354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 75 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 93 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 168 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 299937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 299937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 919237 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1070370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 825198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 70 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 62 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 299770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 299770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1071150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106776 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3233688 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252227 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7485915 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137945088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144089148 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 282034236 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 339553 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4894016 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2840416 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.046099 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3212444 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252074 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7464518 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137042816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144033404 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 281076220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 339392 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4881984 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2833204 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001872 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043223 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2834367 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6049 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2827901 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5303 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2840416 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4418829500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2833204 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4403702500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1618554275 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1607637172 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2121571625 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2121526099 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1207,7 +1201,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51151 # Transaction distribution @@ -1238,46 +1232,46 @@ system.iobus.pkt_size_system.bridge.master::total 44156 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5364500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 813500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 815500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14114000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14072500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2179500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2178500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6040500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6063000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 93500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216207792 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216225034 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.265392 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.265440 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714257470000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.265392 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.079087 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.079087 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714255689000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.265440 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.079090 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.079090 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1286,14 +1280,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21940383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21940383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4930799409 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4930799409 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4952739792 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4952739792 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4952739792 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4952739792 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21944883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21944883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931807151 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4931807151 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4953752034 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4953752034 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4953752034 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4953752034 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1310,19 +1304,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126823.023121 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126823.023121 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118665.753971 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118665.753971 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118699.575602 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118699.575602 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1416 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126849.034682 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126849.034682 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118690.006522 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118690.006522 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118723.835446 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118723.835446 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118723.835446 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118723.835446 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1219 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 108.923077 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 101.583333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1334,14 +1328,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13290383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13290383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2850780302 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2850780302 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2864070685 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2864070685 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2864070685 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2864070685 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13294883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13294883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851781783 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2851781783 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2865076666 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2865076666 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2865076666 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2865076666 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1350,76 +1344,76 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76823.023121 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76823.023121 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68607.535185 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68607.535185 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 825546 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 380389 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76849.034682 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76849.034682 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68631.637057 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68631.637057 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68665.707993 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68665.707993 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68665.707993 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68665.707993 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 825536 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 380380 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 527 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 296601 # Transaction distribution +system.membus.trans_dist::ReadResp 296589 # Transaction distribution system.membus.trans_dist::WriteReq 9599 # Transaction distribution system.membus.trans_dist::WriteResp 9599 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117441 # Transaction distribution -system.membus.trans_dist::CleanEvict 262065 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117411 # Transaction distribution +system.membus.trans_dist::CleanEvict 262092 # Transaction distribution system.membus.trans_dist::UpgradeReq 137 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 114568 # Transaction distribution -system.membus.trans_dist::ReadExResp 114568 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289718 # Transaction distribution +system.membus.trans_dist::ReadExReq 114577 # Transaction distribution +system.membus.trans_dist::ReadExResp 114577 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289706 # Transaction distribution system.membus.trans_dist::BadAddressError 47 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 124 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178956 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1262389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1262381 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30743996 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33403772 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 563 # Total snoops (count) -system.membus.snoopTraffic 27904 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 462504 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001466 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038259 # Request fanout histogram +system.membus.pkt_size::total 33401724 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 562 # Total snoops (count) +system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 462501 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001464 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038231 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 461826 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 461824 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 462504 # Request fanout histogram -system.membus.reqLayer0.occupancy 28800500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 462501 # Request fanout histogram +system.membus.reqLayer0.occupancy 28785000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313542061 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313532070 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 57500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2137882250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2137876500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1056521 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1057021 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1451,52 +1445,52 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211030 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105578 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182260 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182250 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1819124828000 97.54% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 67368000 0.00% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 565513500 0.03% 97.57% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 45251211500 2.43% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865008921000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148608 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1819143935000 97.54% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 67422000 0.00% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 565966500 0.03% 97.57% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 45235960500 2.43% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865013284000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694302 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815418 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694287 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815407 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed @@ -1504,7 +1498,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175141 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175131 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1513,7 +1507,7 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191988 # number of callpals executed +system.cpu.kern.callpal::total 191978 # number of callpals executed system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches @@ -1524,9 +1518,9 @@ system.cpu.kern.mode_switch_good::kernel 0.326098 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29666586000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2759246500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832583080500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29665976500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2757716000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832589583500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 37e31e615..b789abbb5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,163 +1,163 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848913 # Number of seconds simulated -sim_ticks 2848912955000 # Number of ticks simulated -final_tick 2848912955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848599 # Number of seconds simulated +sim_ticks 2848598682500 # Number of ticks simulated +final_tick 2848598682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 258856 # Simulator instruction rate (inst/s) -host_op_rate 313468 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5762698171 # Simulator tick rate (ticks/s) -host_mem_usage 627144 # Number of bytes of host memory used -host_seconds 494.37 # Real time elapsed on the host -sim_insts 127970828 # Number of instructions simulated -sim_ops 154969713 # Number of ops (including micro ops) simulated +host_inst_rate 262669 # Simulator instruction rate (inst/s) +host_op_rate 318064 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5881753499 # Simulator tick rate (ticks/s) +host_mem_usage 626168 # Number of bytes of host memory used +host_seconds 484.31 # Real time elapsed on the host +sim_insts 127213455 # Number of instructions simulated +sim_ops 154041729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 9408 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 9280 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1675840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1349948 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8501504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 229824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 661012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 405952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1663936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1359352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8597824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 234560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 659412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 325376 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12835728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1675840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 229824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1905664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9061888 # Number of bytes written to this memory +system.physmem.bytes_read::total 12852044 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1663936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 234560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1898496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8978368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9079452 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 147 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8995932 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 145 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21618 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 132836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3591 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10349 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21764 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10324 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5084 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 201104 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141592 # Number of write requests responded to by this memory +system.physmem.num_reads::total 201358 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 140287 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145983 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3302 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 144678 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3258 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 588238 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 473847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2984122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 80671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 232023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 142494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 584124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 477200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3018264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 82342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 231486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 114223 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4505483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 588238 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 80671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 668909 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3180823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4511707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 584124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 82342 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 666467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3151854 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6152 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3186988 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3180823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3158020 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3151854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3258 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 588238 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 479998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2984122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 80671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 232037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 142494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 584124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 483352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3018264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 82342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 231500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 114223 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7692471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 201104 # Number of read requests accepted -system.physmem.writeReqs 145983 # Number of write requests accepted -system.physmem.readBursts 201104 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 145983 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12861056 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 9091968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12835728 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9079452 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 7669728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 201358 # Number of read requests accepted +system.physmem.writeReqs 144678 # Number of write requests accepted +system.physmem.readBursts 201358 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 144678 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12877760 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue +system.physmem.bytesWritten 9008896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12852044 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8995932 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12429 # Per bank write bursts -system.physmem.perBankRdBursts::1 12794 # Per bank write bursts -system.physmem.perBankRdBursts::2 13696 # Per bank write bursts -system.physmem.perBankRdBursts::3 13190 # Per bank write bursts -system.physmem.perBankRdBursts::4 15337 # Per bank write bursts -system.physmem.perBankRdBursts::5 12894 # Per bank write bursts -system.physmem.perBankRdBursts::6 12741 # Per bank write bursts -system.physmem.perBankRdBursts::7 13088 # Per bank write bursts -system.physmem.perBankRdBursts::8 12333 # Per bank write bursts -system.physmem.perBankRdBursts::9 12486 # Per bank write bursts -system.physmem.perBankRdBursts::10 11357 # Per bank write bursts -system.physmem.perBankRdBursts::11 10671 # Per bank write bursts -system.physmem.perBankRdBursts::12 11888 # Per bank write bursts -system.physmem.perBankRdBursts::13 12773 # Per bank write bursts -system.physmem.perBankRdBursts::14 11762 # Per bank write bursts -system.physmem.perBankRdBursts::15 11515 # Per bank write bursts -system.physmem.perBankWrBursts::0 8987 # Per bank write bursts -system.physmem.perBankWrBursts::1 9459 # Per bank write bursts -system.physmem.perBankWrBursts::2 10102 # Per bank write bursts -system.physmem.perBankWrBursts::3 9553 # Per bank write bursts -system.physmem.perBankWrBursts::4 8641 # Per bank write bursts -system.physmem.perBankWrBursts::5 9022 # Per bank write bursts -system.physmem.perBankWrBursts::6 9160 # Per bank write bursts -system.physmem.perBankWrBursts::7 9289 # Per bank write bursts -system.physmem.perBankWrBursts::8 8726 # Per bank write bursts -system.physmem.perBankWrBursts::9 8906 # Per bank write bursts -system.physmem.perBankWrBursts::10 8219 # Per bank write bursts -system.physmem.perBankWrBursts::11 7897 # Per bank write bursts -system.physmem.perBankWrBursts::12 8731 # Per bank write bursts -system.physmem.perBankWrBursts::13 8920 # Per bank write bursts -system.physmem.perBankWrBursts::14 8491 # Per bank write bursts -system.physmem.perBankWrBursts::15 7959 # Per bank write bursts +system.physmem.perBankRdBursts::0 12337 # Per bank write bursts +system.physmem.perBankRdBursts::1 12726 # Per bank write bursts +system.physmem.perBankRdBursts::2 13547 # Per bank write bursts +system.physmem.perBankRdBursts::3 13037 # Per bank write bursts +system.physmem.perBankRdBursts::4 15119 # Per bank write bursts +system.physmem.perBankRdBursts::5 12845 # Per bank write bursts +system.physmem.perBankRdBursts::6 12657 # Per bank write bursts +system.physmem.perBankRdBursts::7 13022 # Per bank write bursts +system.physmem.perBankRdBursts::8 12280 # Per bank write bursts +system.physmem.perBankRdBursts::9 12341 # Per bank write bursts +system.physmem.perBankRdBursts::10 11583 # Per bank write bursts +system.physmem.perBankRdBursts::11 10739 # Per bank write bursts +system.physmem.perBankRdBursts::12 12026 # Per bank write bursts +system.physmem.perBankRdBursts::13 12946 # Per bank write bursts +system.physmem.perBankRdBursts::14 12179 # Per bank write bursts +system.physmem.perBankRdBursts::15 11831 # Per bank write bursts +system.physmem.perBankWrBursts::0 8873 # Per bank write bursts +system.physmem.perBankWrBursts::1 9291 # Per bank write bursts +system.physmem.perBankWrBursts::2 9856 # Per bank write bursts +system.physmem.perBankWrBursts::3 9274 # Per bank write bursts +system.physmem.perBankWrBursts::4 8405 # Per bank write bursts +system.physmem.perBankWrBursts::5 8988 # Per bank write bursts +system.physmem.perBankWrBursts::6 8961 # Per bank write bursts +system.physmem.perBankWrBursts::7 9107 # Per bank write bursts +system.physmem.perBankWrBursts::8 8695 # Per bank write bursts +system.physmem.perBankWrBursts::9 8769 # Per bank write bursts +system.physmem.perBankWrBursts::10 8272 # Per bank write bursts +system.physmem.perBankWrBursts::11 7845 # Per bank write bursts +system.physmem.perBankWrBursts::12 8751 # Per bank write bursts +system.physmem.perBankWrBursts::13 8985 # Per bank write bursts +system.physmem.perBankWrBursts::14 8630 # Per bank write bursts +system.physmem.perBankWrBursts::15 8062 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 98 # Number of times write queue was full causing retry -system.physmem.totGap 2848912399000 # Total gap between requests +system.physmem.numWrRetry 74 # Number of times write queue was full causing retry +system.physmem.totGap 2848598144000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 556 # Read request sizes (log2) +system.physmem.readPktSize::2 555 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 200520 # Read request sizes (log2) +system.physmem.readPktSize::6 200775 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 141592 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 84624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6722 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 140287 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4878 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -185,178 +185,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 296 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 244.770315 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.172635 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 301.083170 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45750 51.01% 51.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18787 20.95% 71.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6651 7.42% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3758 4.19% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2958 3.30% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1568 1.75% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1004 1.12% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1009 1.13% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8203 9.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89688 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7073 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.410010 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 554.388606 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7071 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 216 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 88566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 247.121830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 141.476955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 302.598654 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 44693 50.46% 50.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18724 21.14% 71.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6637 7.49% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3795 4.28% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2919 3.30% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1572 1.77% 88.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 960 1.08% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1024 1.16% 90.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8242 9.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88566 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.806586 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 558.021687 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6983 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7073 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.085112 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.515707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.383837 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5944 84.04% 84.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 432 6.11% 90.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 82 1.16% 91.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 52 0.74% 92.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 255 3.61% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.35% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 15 0.21% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.10% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.18% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.13% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.10% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 148 2.09% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 11 0.16% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.08% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.04% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 9 0.13% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.08% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.08% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.06% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.06% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7073 # Writes before turning the bus around for reads -system.physmem.totQLat 9366475580 # Total ticks spent queuing -system.physmem.totMemAccLat 13134363080 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1004770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 46610.05 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6985 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.152326 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.495944 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.110349 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5869 84.02% 84.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 441 6.31% 90.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 79 1.13% 91.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 0.63% 92.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 241 3.45% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.36% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 15 0.21% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.14% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.24% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.11% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.04% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.10% 96.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 146 2.09% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.09% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.10% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 11 0.16% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.14% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6985 # Writes before turning the bus around for reads +system.physmem.totQLat 9483410947 # Total ticks spent queuing +system.physmem.totMemAccLat 13256192197 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1006075000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47130.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 65360.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.51 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 65880.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.20 # Average write queue length when enqueuing -system.physmem.readRowHits 166422 # Number of row buffer hits during reads -system.physmem.writeRowHits 86905 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.16 # Row buffer hit rate for writes -system.physmem.avgGap 8208064.26 # Average gap between requests -system.physmem.pageHitRate 73.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341813220 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 181678035 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 758046660 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 387391860 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5805889440.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5444775090 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 308095680 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 11642068740 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8562690720 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 670190772435 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 703626055650 # Total energy per rank (pJ) -system.physmem_0.averagePower 246.980538 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2836051939093 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 546109733 # Time in different power states -system.physmem_0.memoryStateTime::REF 2466940000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2788334468750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 22298648785 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9735828674 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 25530959058 # Time in different power states -system.physmem_1.actEnergy 298566240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 158687925 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 676764900 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 354171780 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5707547040.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5348415450 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 325299360 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10595992200 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8817735360 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 670663868775 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 702949735620 # Total energy per rank (pJ) -system.physmem_1.averagePower 246.743143 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2836330915238 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 596946927 # Time in different power states -system.physmem_1.memoryStateTime::REF 2425844000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2790131179750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 22962884806 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9559167335 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 23236932182 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.98 # Average write queue length when enqueuing +system.physmem.readRowHits 166670 # Number of row buffer hits during reads +system.physmem.writeRowHits 86742 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.61 # Row buffer hit rate for writes +system.physmem.avgGap 8232086.10 # Average gap between requests +system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 334044900 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 177549075 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 751770600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 379781100 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5711234880.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5249821980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 307614240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 11585671230 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8434613280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 670304268120 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 703238620035 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.871777 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2836104738853 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 545953693 # Time in different power states +system.physmem_0.memoryStateTime::REF 2426690000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2788907518000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21965166332 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9346009704 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 25407344771 # Time in different power states +system.physmem_1.actEnergy 298323480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 158558895 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 684904500 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 355006980 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5713078800.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5198973990 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 317598720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10947475860 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8696180160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 670560217290 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 702932935245 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.764467 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2836364452001 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 573854684 # Time in different power states +system.physmem_1.memoryStateTime::REF 2428124000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2789710596750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 22646269258 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9232187315 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24007650493 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -375,30 +375,30 @@ system.realview.nvmem.bw_inst_read::total 472 # I system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20830846 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13649526 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1014386 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13197369 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8753451 # Number of BTB hits +system.cpu0.branchPred.lookups 21387746 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14055793 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1067110 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13655999 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8982856 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.327243 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3414506 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 211257 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 762629 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 580306 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 182323 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 100148 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 65.779560 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3510572 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 218030 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 788067 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 592988 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 195079 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 105213 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -428,61 +428,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 66699 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 66699 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45954 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20745 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 66699 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 66699 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 66699 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6786 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12503.831418 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11414.396725 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6634.903581 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6272 92.43% 92.43% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 416 6.13% 98.56% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 85 1.25% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 5 0.07% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 5 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6786 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 69629 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 69629 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46094 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23535 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 69629 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 69629 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 69629 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7649 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12135.050333 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10988.955041 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 11832.363963 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 7639 99.87% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7649 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5256 77.45% 77.45% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1530 22.55% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6786 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66699 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5959 77.91% 77.91% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1690 22.09% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7649 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69629 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66699 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6786 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69629 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7649 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6786 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 73485 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7649 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 77278 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17337178 # DTB read hits -system.cpu0.dtb.read_misses 60105 # DTB read misses -system.cpu0.dtb.write_hits 14536732 # DTB write hits -system.cpu0.dtb.write_misses 6594 # DTB write misses +system.cpu0.dtb.read_hits 17966885 # DTB read hits +system.cpu0.dtb.read_misses 63028 # DTB read misses +system.cpu0.dtb.write_hits 15039551 # DTB write hits +system.cpu0.dtb.write_misses 6601 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3451 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1375 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1930 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3754 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2059 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 524 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17397283 # DTB read accesses -system.cpu0.dtb.write_accesses 14543326 # DTB write accesses +system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 18029913 # DTB read accesses +system.cpu0.dtb.write_accesses 15046152 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31873910 # DTB hits -system.cpu0.dtb.misses 66699 # DTB misses -system.cpu0.dtb.accesses 31940609 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 33006436 # DTB hits +system.cpu0.dtb.misses 69629 # DTB misses +system.cpu0.dtb.accesses 33076065 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -512,40 +509,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 4013 # Table walker walks requested -system.cpu0.itb.walker.walksShort 4013 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 305 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3708 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 4013 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 4013 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 4013 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2436 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12745.689655 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11895.862443 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5321.422543 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 433 17.78% 17.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1791 73.52% 91.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 138 5.67% 96.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.52% 98.48% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.48% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 4318 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4318 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3993 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4318 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4318 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4318 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2683 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12304.137160 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11560.884208 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4695.711947 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 502 18.71% 18.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1984 73.95% 92.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 147 5.48% 98.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 31 1.16% 99.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 18 0.67% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2436 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2683 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2136 87.68% 87.68% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 300 12.32% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2436 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2363 88.07% 88.07% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 320 11.93% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2683 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4013 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4013 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4318 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4318 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2436 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2436 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6449 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38740955 # ITB inst hits -system.cpu0.itb.inst_misses 4013 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2683 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2683 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 7001 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 39752533 # ITB inst hits +system.cpu0.itb.inst_misses 4318 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -554,798 +551,796 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2172 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2396 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7050 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7865 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38744968 # ITB inst accesses -system.cpu0.itb.hits 38740955 # DTB hits -system.cpu0.itb.misses 4013 # DTB misses -system.cpu0.itb.accesses 38744968 # DTB accesses -system.cpu0.numPwrStateTransitions 3702 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1851 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1492467740.212318 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23926618307.518574 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1069 57.75% 57.75% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.87% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 39756851 # ITB inst accesses +system.cpu0.itb.hits 39752533 # DTB hits +system.cpu0.itb.misses 4318 # DTB misses +system.cpu0.itb.accesses 39756851 # DTB accesses +system.cpu0.numPwrStateTransitions 3708 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1854 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1488611861.955232 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23946276211.601498 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1085 58.52% 58.52% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 762 41.10% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963002708 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1851 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 86355167867 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762557787133 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 172712897 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963838164 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1854 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 88712290435 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759886392065 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 177427128 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79713377 # Number of instructions committed -system.cpu0.committedOps 95922535 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5281292 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1851 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5525141996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.166674 # CPI: cycles per instruction -system.cpu0.ipc 0.461537 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 63731011 66.44% 66.44% # Class of committed instruction -system.cpu0.op_class_0::IntMult 92142 0.10% 66.54% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatMisc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 8073 0.01% 66.55% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.55% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.55% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.55% # Class of committed instruction -system.cpu0.op_class_0::MemRead 16805807 17.52% 84.07% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 15273589 15.92% 99.99% # Class of committed instruction -system.cpu0.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction -system.cpu0.op_class_0::FloatMemWrite 7384 0.01% 100.00% # Class of committed instruction +system.cpu0.committedInsts 82154396 # Number of instructions committed +system.cpu0.committedOps 98918766 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5358225 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1854 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5519798084 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.159679 # CPI: cycles per instruction +system.cpu0.ipc 0.463032 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 2315 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 65610842 66.33% 66.33% # Class of committed instruction +system.cpu0.op_class_0::IntMult 94061 0.10% 66.43% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatMisc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8175 0.01% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::MemRead 17407324 17.60% 84.03% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15784753 15.96% 99.99% # Class of committed instruction +system.cpu0.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction +system.cpu0.op_class_0::FloatMemWrite 8588 0.01% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 95922535 # Class of committed instruction +system.cpu0.op_class_0::total 98918766 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1851 # number of quiesce instructions executed -system.cpu0.tickCycles 120871852 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 51841045 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 716918 # number of replacements -system.cpu0.dcache.tags.tagsinuse 495.671066 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30432435 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 717430 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.418682 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed +system.cpu0.tickCycles 124478065 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 52949063 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 756000 # number of replacements +system.cpu0.dcache.tags.tagsinuse 495.989536 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 31503611 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 756512 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 41.643240 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.671066 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968108 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.968108 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.989536 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968730 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.968730 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63807329 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63807329 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15850504 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15850504 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13422208 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13422208 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320804 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 320804 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365505 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365505 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361161 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361161 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29272712 # 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number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1020292 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1020292 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1156048 # number of overall misses -system.cpu0.dcache.overall_misses::total 1156048 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6443435000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6443435000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11283390500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11283390500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 333090000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 333090000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 482408000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 482408000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 637500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 637500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 17726825500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 17726825500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 17726825500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 17726825500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16289639 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16289639 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 14003365 # 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miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033681 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033681 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037596 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.037596 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14673.016271 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14673.016271 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19415.391194 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19415.391194 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15919.801176 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15919.801176 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23652.088645 # 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number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370195 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 370195 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 30318579 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 30318579 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 30646903 # number of overall hits +system.cpu0.dcache.overall_hits::total 30646903 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 460755 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 460755 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 603639 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 603639 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141924 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141924 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21489 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21489 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20512 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20512 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1064394 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1064394 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1206318 # number of overall misses +system.cpu0.dcache.overall_misses::total 1206318 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6676359500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6676359500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11544866500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11544866500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336675500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 336675500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485473000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 485473000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 539500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 539500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 18221226000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 18221226000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 18221226000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 18221226000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16888891 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16888891 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 14494082 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 14494082 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470248 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 470248 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 395608 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 395608 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390707 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 390707 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 31382973 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 31382973 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 31853221 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 31853221 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027282 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027282 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041647 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041647 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301807 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301807 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054319 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054319 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052500 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052500 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033916 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033916 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037871 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037871 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.042430 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.042430 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19125.448323 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19125.448323 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15667.341430 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15667.341430 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23667.755460 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23667.755460 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17374.266877 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17374.266877 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15333.987430 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15333.987430 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17118.873274 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17118.873274 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15104.828080 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15104.828080 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 716918 # number of writebacks -system.cpu0.dcache.writebacks::total 716918 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44597 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 44597 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255598 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 255598 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14548 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14548 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 300195 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 300195 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 300195 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 300195 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 394538 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 394538 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325559 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325559 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102257 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 102257 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6375 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6375 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20396 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20396 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 720097 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 720097 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 822354 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 822354 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20581 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39851 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5273598500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5273598500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6168960000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6168960000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1704833000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1704833000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102845500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102845500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 462030000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 462030000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 619500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 619500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11442558500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11442558500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13147391500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13147391500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4607502500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4607502500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4607502500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4607502500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024220 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024220 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223973 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223973 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016497 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016497 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053455 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053455 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023771 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023771 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026744 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026744 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13366.516026 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13366.516026 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18948.823408 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18948.823408 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16672.042012 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16672.042012 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16132.627451 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16132.627451 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22652.971171 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22652.971171 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 756000 # number of writebacks +system.cpu0.dcache.writebacks::total 756000 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 45822 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 45822 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266133 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 266133 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14947 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14947 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 311955 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 311955 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 311955 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 311955 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 414933 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 414933 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337506 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 337506 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108299 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 108299 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6542 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6542 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20512 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20512 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 752439 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 752439 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 860738 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 860738 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20603 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20603 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19302 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19302 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39905 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39905 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5470255000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5470255000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6299771000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6299771000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1751643500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1751643500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104376500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104376500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 464977000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 464977000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 523500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 523500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11770026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11770026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13521669500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13521669500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4611679000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4611679000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4611679000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4611679000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024568 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024568 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023286 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023286 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230302 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230302 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016537 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016537 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052500 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052500 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023976 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023976 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027022 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027022 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13183.465764 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13183.465764 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18665.656314 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18665.656314 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16174.142882 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.142882 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15954.830327 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15954.830327 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22668.535491 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22668.535491 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15890.301584 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15890.301584 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15987.508421 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15987.508421 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223871.653467 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223871.653467 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115618.240446 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115618.240446 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1966568 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.773009 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36766553 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1967080 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.690929 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6697446000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.773009 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999557 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999557 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15642.498595 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15642.498595 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15709.390662 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15709.390662 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223835.315245 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223835.315245 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115566.445308 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115566.445308 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 2036864 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.774783 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 37707013 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 2037376 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.507636 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6575306000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774783 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79434387 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79434387 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 36766553 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36766553 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36766553 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36766553 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36766553 # number of overall hits -system.cpu0.icache.overall_hits::total 36766553 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1967094 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1967094 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1967094 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1967094 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1967094 # number of overall misses -system.cpu0.icache.overall_misses::total 1967094 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19796906000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 19796906000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 19796906000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 19796906000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 19796906000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 19796906000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38733647 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38733647 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38733647 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38733647 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38733647 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38733647 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050785 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050785 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050785 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050785 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050785 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050785 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10064.036594 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10064.036594 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10064.036594 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10064.036594 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10064.036594 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10064.036594 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 81526207 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 81526207 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 37707013 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 37707013 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 37707013 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 37707013 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 37707013 # number of overall hits +system.cpu0.icache.overall_hits::total 37707013 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 2037394 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2037394 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 2037394 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2037394 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 2037394 # number of overall misses +system.cpu0.icache.overall_misses::total 2037394 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20429568000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 20429568000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 20429568000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 20429568000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 20429568000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 20429568000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 39744407 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 39744407 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 39744407 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 39744407 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 39744407 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 39744407 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051262 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.051262 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051262 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.051262 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051262 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.051262 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10027.303506 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10027.303506 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10027.303506 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10027.303506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10027.303506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10027.303506 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # 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Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004030 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063834 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.953750 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 230 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15349 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 83 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14568.839087 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.655947 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.055478 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1008.263889 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.889211 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003763 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000003 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.061540 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954517 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 252 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15345 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 32 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 142 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1192 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7258 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5558 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1085 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.014038 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936829 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 91498325 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 91498325 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # 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number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4442744500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4740410500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014430 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4446739000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4744405000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009832 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159236 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159236 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046643 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.226095 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.226095 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.202801 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088376 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.202801 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.151135 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.151135 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046819 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216613 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216613 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193928 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.086286 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193928 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.182218 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34078.086672 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63097.730550 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17308.922663 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17308.922663 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15108.575211 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.575211 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177388 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 41446.590909 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63628.910343 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17351.312476 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17351.312476 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15124.902496 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15124.902496 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50274.240208 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50274.240208 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43245.133621 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26883.323189 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26883.323189 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36948.799964 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50415.402160 # average overall mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51416.629338 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51416.629338 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42309.640626 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26915.711725 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26915.711725 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33530.887785 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36862.117594 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33530.887785 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50608.790647 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215866.308731 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198692.702657 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215829.684997 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198676.926298 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111483.889990 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109914.916064 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5521359 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2782090 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 221607 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217384 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4223 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 119065 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2638335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19270 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19270 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 714834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2201699 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 105895 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 314040 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88690 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43009 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113952 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288266 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284716 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1967094 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3100 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111433.128681 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109869.968969 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5741859 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2893899 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44137 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 221175 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4173 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 125397 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2741625 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19302 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19302 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 743607 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2286693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 110010 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 316910 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 86864 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42906 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 299874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 296474 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2037394 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 616815 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3112 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5907309 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2596679 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13203 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166718 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8683909 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251964032 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99557768 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21928 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 317096 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 351860824 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 942421 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 19099824 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3784720 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.076642 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.270185 # Request fanout histogram +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6118205 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2712873 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14034 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 176949 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 9022061 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 260962176 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104517534 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22892 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 335140 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 365837742 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 939630 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 19388808 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3896038 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.075284 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.267877 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3498873 92.45% 92.45% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 281624 7.44% 99.89% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4223 0.11% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3606903 92.58% 92.58% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 284962 7.31% 99.89% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4173 0.11% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3784720 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5512121494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3896038 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5733869996 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115701354 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115563972 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2955829450 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 3061282943 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1228012492 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1285797933 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7726489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 8314992 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 87463960 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 93182962 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 19376501 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6203106 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 800498 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9925818 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3621861 # Number of BTB hits +system.cpu1.branchPred.lookups 18647514 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5782822 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 870887 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9511803 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3428026 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.489295 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8664248 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 596452 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3651980 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 3587973 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 64007 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 23614 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 36.039708 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8548256 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 712976 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3551521 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 3498978 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 52543 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 17984 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1375,63 +1370,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 26236 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26236 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19848 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6388 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26236 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26236 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26236 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2697 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12386.911383 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11389.033391 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6251.379906 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 628 23.29% 23.29% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1805 66.93% 90.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 172 6.38% 96.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.08% 98.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 26 0.96% 99.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 2 0.07% 99.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 3 0.11% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 3 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2697 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1855739032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1855739032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1855739032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2013 74.64% 74.64% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 684 25.36% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2697 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26236 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 22971 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 22971 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19558 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3413 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 22971 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 22971 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 22971 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1848 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12803.300866 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11525.814953 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15800.491207 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 1844 99.78% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3 0.16% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1848 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1978443032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1978443032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1978443032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1308 70.78% 70.78% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 540 29.22% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1848 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22971 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26236 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2697 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22971 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1848 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2697 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 28933 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1848 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24819 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11335471 # DTB read hits -system.cpu1.dtb.read_misses 23997 # DTB read misses -system.cpu1.dtb.write_hits 7067505 # DTB write hits -system.cpu1.dtb.write_misses 2239 # DTB write misses +system.cpu1.dtb.read_hits 10530339 # DTB read hits +system.cpu1.dtb.read_misses 20830 # DTB read misses +system.cpu1.dtb.write_hits 6472980 # DTB write hits +system.cpu1.dtb.write_misses 2141 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1990 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 147 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 359 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1623 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 116 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 265 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11359468 # DTB read accesses -system.cpu1.dtb.write_accesses 7069744 # DTB write accesses +system.cpu1.dtb.perms_faults 184 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10551169 # DTB read accesses +system.cpu1.dtb.write_accesses 6475121 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18402976 # DTB hits -system.cpu1.dtb.misses 26236 # DTB misses -system.cpu1.dtb.accesses 18429212 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 17003319 # DTB hits +system.cpu1.dtb.misses 22971 # DTB misses +system.cpu1.dtb.accesses 17026290 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1461,45 +1450,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 2445 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2445 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2265 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2445 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2445 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2445 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12500.891266 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11818.240424 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4741.770571 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 15.60% 15.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 626 55.79% 71.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 208 18.54% 89.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.37% 94.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 21 1.87% 96.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 29 2.58% 98.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 9 0.80% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1856356532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1856356532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1856356532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 957 85.29% 85.29% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 165 14.71% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 2051 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2051 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 145 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1906 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2051 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2051 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2051 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 830 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12046.987952 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11480.071390 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4509.628818 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 126 15.18% 15.18% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 555 66.87% 82.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 85 10.24% 92.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 14 1.69% 93.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 22 2.65% 96.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 18 2.17% 98.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 6 0.72% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.36% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 830 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1979056532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1979056532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1979056532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 695 83.73% 83.73% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 135 16.27% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 830 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2445 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2445 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2051 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2051 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3567 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39707544 # ITB inst hits -system.cpu1.itb.inst_misses 2445 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 830 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 830 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2881 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 38623354 # ITB inst hits +system.cpu1.itb.inst_misses 2051 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1508,790 +1495,785 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1094 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1860 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1040 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39709989 # ITB inst accesses -system.cpu1.itb.hits 39707544 # DTB hits -system.cpu1.itb.misses 2445 # DTB misses -system.cpu1.itb.accesses 39709989 # DTB accesses -system.cpu1.numPwrStateTransitions 5531 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2766 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1008751457.310195 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25700289930.408852 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1968 71.15% 71.15% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.71% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 38625405 # ITB inst accesses +system.cpu1.itb.hits 38623354 # DTB hits +system.cpu1.itb.misses 2051 # DTB misses +system.cpu1.itb.accesses 38625405 # DTB accesses +system.cpu1.numPwrStateTransitions 5477 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2739 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1019571073.706097 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25827442882.959442 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1941 70.87% 70.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.99% 99.85% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 949980202104 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2766 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 58706424080 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790206530920 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 117416330 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 949980394548 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2739 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 55993511619 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2792605170881 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 111990488 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48257451 # Number of instructions committed -system.cpu1.committedOps 59047178 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5145755 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2766 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5579767080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.433123 # CPI: cycles per instruction -system.cpu1.ipc 0.410994 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 40655660 68.85% 68.85% # Class of committed instruction -system.cpu1.op_class_0::IntMult 45723 0.08% 68.93% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatMultAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatMisc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 3341 0.01% 68.94% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.94% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.94% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.94% # Class of committed instruction -system.cpu1.op_class_0::MemRead 11158922 18.90% 87.83% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 7181682 12.16% 100.00% # Class of committed instruction -system.cpu1.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction +system.cpu1.committedInsts 45059059 # Number of instructions committed +system.cpu1.committedOps 55122963 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 4849343 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2739 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5584538446 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.485416 # CPI: cycles per instruction +system.cpu1.ipc 0.402347 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 38107074 69.13% 69.13% # Class of committed instruction +system.cpu1.op_class_0::IntMult 43629 0.08% 69.21% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatMisc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3226 0.01% 69.22% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.22% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.22% # Class of committed instruction +system.cpu1.op_class_0::MemRead 10387367 18.84% 88.06% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 6581643 11.94% 100.00% # Class of committed instruction +system.cpu1.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu1.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 59047178 # Class of committed instruction +system.cpu1.op_class_0::total 55122963 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed -system.cpu1.tickCycles 94212752 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 23203578 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 197406 # number of replacements -system.cpu1.dcache.tags.tagsinuse 475.838335 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17978253 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 197762 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 90.908531 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91321339500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.838335 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929372 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.929372 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 356 # Occupied blocks per task id +system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed +system.cpu1.tickCycles 90184958 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 21805530 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 157661 # number of replacements +system.cpu1.dcache.tags.tagsinuse 475.726390 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 16648746 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 158020 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 105.358474 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91198641000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.726390 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929153 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.929153 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 284 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.695312 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36857417 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36857417 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 10958654 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10958654 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6778912 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6778912 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50538 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50538 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80236 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80236 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71701 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71701 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17737566 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17737566 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17788104 # number of overall hits -system.cpu1.dcache.overall_hits::total 17788104 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 149954 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 149954 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 146295 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 146295 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30728 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30728 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16950 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16950 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 296249 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 296249 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 326977 # number of overall misses -system.cpu1.dcache.overall_misses::total 326977 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2480923500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2480923500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4141245000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4141245000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326364000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 326364000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557050500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 557050500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 662000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 662000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6622168500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6622168500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6622168500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6622168500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11108608 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11108608 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6925207 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6925207 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81266 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 81266 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97186 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97186 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95370 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95370 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 18033815 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 18033815 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 18115081 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 18115081 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013499 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.013499 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021125 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021125 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378116 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378116 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174408 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174408 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248181 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248181 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016427 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.016427 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018050 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.018050 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16544.563666 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16544.563666 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28307.495130 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28307.495130 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19254.513274 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19254.513274 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23535.024716 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23535.024716 # average StoreCondReq miss latency +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 34039754 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 34039754 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 10204486 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10204486 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6223411 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6223411 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 43300 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 43300 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71256 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 71256 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 62645 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 62645 # 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number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23356 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 249653 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 249653 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 273818 # number of overall misses +system.cpu1.dcache.overall_misses::total 273818 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2191208500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2191208500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3801376500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3801376500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322530000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 322530000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548226000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 548226000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 650000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 650000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5992585000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5992585000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5992585000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5992585000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10331876 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10331876 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6345674 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6345674 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67465 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 67465 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87781 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 87781 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 86001 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 86001 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16677550 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16677550 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16745015 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16745015 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012330 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.012330 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.019267 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.019267 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358186 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358186 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188253 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188253 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.271578 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.271578 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014969 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.014969 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.016352 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.016352 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17200.788916 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 17200.788916 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31091.798009 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31091.798009 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19517.700454 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19517.700454 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23472.598048 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23472.598048 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22353.386847 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22353.386847 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20252.704319 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20252.704319 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24003.657076 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24003.657076 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21885.285116 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21885.285116 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 197406 # number of writebacks -system.cpu1.dcache.writebacks::total 197406 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5638 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 5638 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53221 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 53221 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12059 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12059 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 58859 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 58859 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 58859 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 58859 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 144316 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 144316 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93074 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 93074 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29900 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29900 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4891 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4891 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 237390 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 237390 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 267290 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 267290 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11757 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26181 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26181 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2239010000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2239010000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2480218000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2480218000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 521766000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 521766000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86789500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86789500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533397500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533397500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 646000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 646000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4719228000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4719228000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5240994000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5240994000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2492996500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2492996500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2492996500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2492996500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.367928 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.367928 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050326 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050326 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248181 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248181 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013164 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013164 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014755 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15514.634552 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15514.634552 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26647.807121 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26647.807121 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17450.367893 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17450.367893 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17744.735228 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17744.735228 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22535.700706 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22535.700706 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 157661 # number of writebacks +system.cpu1.dcache.writebacks::total 157661 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 4447 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 4447 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42267 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 42267 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11747 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11747 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 46714 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 46714 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 46714 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 46714 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 122943 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 122943 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79996 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 79996 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23657 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23657 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4778 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4778 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23356 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23356 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 202939 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 202939 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 226596 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 226596 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14406 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14406 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11728 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11728 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26134 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26134 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1987288500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1987288500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2305734500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2305734500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 418963500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 418963500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86008500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86008500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524885000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524885000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 635000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 635000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4293023000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4293023000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4711986500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4711986500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2490253500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2490253500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2490253500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2490253500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.011899 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.011899 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012606 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012606 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.350656 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.350656 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054431 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054431 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.271578 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.271578 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.012168 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.012168 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.013532 # 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average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22473.240281 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19879.641097 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19879.641097 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19607.894048 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19607.894048 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172836.695785 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172836.695785 # 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Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974976 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21154.253249 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21154.253249 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20794.658776 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20794.658776 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172862.244898 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172862.244898 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95287.881687 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95287.881687 # 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Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80363305 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80363305 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 38753540 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38753540 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38753540 # 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number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8812564500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8812564500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8812564500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39705615 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39705615 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39705615 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39705615 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39705615 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39705615 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023978 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023978 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023978 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023978 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023978 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023978 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9256.166268 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9256.166268 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9256.166268 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9256.166268 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 78117905 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 78117905 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 37748872 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 37748872 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 37748872 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 37748872 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 37748872 # number of overall hits +system.cpu1.icache.overall_hits::total 37748872 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 873387 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 873387 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 873387 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 873387 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 873387 # 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average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9173.100241 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9173.100241 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9173.100241 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 951563 # number of writebacks -system.cpu1.icache.writebacks::total 951563 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 952075 # 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mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023978 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8756.166268 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98183.035714 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98183.035714 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 202046 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 202062 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7574973000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7574973000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7574973000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7574973000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7574973000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7574973000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11042500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 11042500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 11042500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 11042500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022614 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022614 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8673.100241 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8673.100241 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8673.100241 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98593.750000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98593.750000 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 118852 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 118852 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58314 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 53261 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14759.472479 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1060224 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 67460 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 15.716336 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 49172 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 37377 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14753.834184 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 946442 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 52088 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 18.170058 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14399.124814 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.202581 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.100138 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 322.044945 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.878853 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002332 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019656 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.900847 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 251 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13906 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 172 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1287 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7824 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4795 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.015320 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.848755 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 39696628 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 39696628 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28743 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3180 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 31923 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 117832 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 117832 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 1010940 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 1010940 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28052 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 28052 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 916446 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 916446 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 103629 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 103629 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28743 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3180 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 916446 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 131681 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1080050 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28743 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3180 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 916446 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 131681 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1080050 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 682 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 266 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 948 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 30054 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 30054 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23668 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23668 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34968 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34968 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 35629 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 35629 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75478 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 75478 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 682 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 266 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 35629 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 110446 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 147023 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 682 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 266 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 35629 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 110446 # number of overall misses -system.cpu1.l2cache.overall_misses::total 147023 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15962500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5289000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 21251500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13859000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 13859000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17603500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17603500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 622000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 622000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1509066000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1509066000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1359934000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1359934000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1890312995 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1890312995 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15962500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5289000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1359934000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3399378995 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4780564495 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15962500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5289000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1359934000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3399378995 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4780564495 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29425 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3446 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 32871 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 117832 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 117832 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 1010940 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 1010940 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30054 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 30054 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23668 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23668 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63020 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 63020 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 952075 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 952075 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 179107 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 179107 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29425 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3446 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 952075 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 242127 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1227073 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29425 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3446 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 952075 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 242127 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1227073 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.077191 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.028840 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 14422.597482 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 42.225036 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.137350 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 287.874316 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.880285 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002577 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000069 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.017570 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.900503 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 261 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14372 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 24 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 234 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 53 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1285 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2929 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10158 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.015930 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.877197 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 35693220 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 35693220 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23446 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2580 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 26026 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 95283 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 95283 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 916386 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 916386 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18220 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 18220 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 844850 # 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mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16420.802534 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36722.378742 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15370.915685 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15370.915685 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14987.683792 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14987.683792 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 526000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 526000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36731.335557 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36731.335557 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32174.482604 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19032.901739 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19032.901739 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26400.089251 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27968.467730 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164835.239878 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164260.044029 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90813.318819 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90810.634009 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2407036 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1212847 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 118681 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110741 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7940 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 51870 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1220498 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11757 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11757 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 156434 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1031137 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 35507 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 31472 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 73789 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42123 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86153 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 70267 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67627 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952075 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295896 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 106 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2855937 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915985 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8156 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62049 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3842127 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121840000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30925576 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13784 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117700 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 152897060 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 370911 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 5180924 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1603484 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.097889 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.313386 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.137257 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18290.843806 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37324.744513 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15238.915498 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15238.915498 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14925.415311 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14925.415311 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37833.451748 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37833.451748 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34186.842843 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18662.386039 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18662.386039 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24742.762058 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26733.993569 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24742.762058 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28108.097146 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164860.717756 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164287.780686 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90877.152369 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90875.943001 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2165902 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1090398 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 115909 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 108045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7864 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 44859 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1106447 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11728 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11728 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 126621 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 935252 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 26571 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 23763 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71775 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41777 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84685 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 58060 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55427 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 873387 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263309 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 71 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2619873 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 793002 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6834 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50653 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3470362 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 111767936 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25786238 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11508 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 97076 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 137662758 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 338759 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4674348 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1446654 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.103615 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.322104 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1454460 90.71% 90.71% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 141084 8.80% 99.50% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 7940 0.50% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1304623 90.18% 90.18% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 134167 9.27% 99.46% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 7864 0.54% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1603484 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2385111494 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1446654 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2144021494 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79363429 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 78336814 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1428355849 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 412276680 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1310300396 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 351676729 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4711996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3959994 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 32634978 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 26397473 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 31009 # Transaction distribution +system.iobus.trans_dist::ReadResp 31009 # Transaction distribution +system.iobus.trans_dist::WriteReq 59424 # Transaction distribution +system.iobus.trans_dist::WriteResp 59424 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2310,11 +2292,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2333,94 +2315,94 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48355001 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483988 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48425501 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 110500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 611500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 621000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6349500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6370500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38550000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 39055001 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187836280 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187730317 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36461 # number of replacements -system.iocache.tags.tagsinuse 14.472129 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36449 # number of replacements +system.iocache.tags.tagsinuse 14.472713 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272035829000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.472129 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904508 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904508 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 271902155000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.472713 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904545 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904545 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328311 # Number of tag accesses -system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses -system.iocache.ReadReq_misses::total 255 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses -system.iocache.demand_misses::total 36479 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36479 # number of overall misses -system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 33894626 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 33894626 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4361652654 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4361652654 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4395547280 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4395547280 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4395547280 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4395547280 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses +system.iocache.demand_misses::total 36467 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36467 # number of overall misses +system.iocache.overall_misses::total 36467 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32482877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32482877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4347292440 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4347292440 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4379775317 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4379775317 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4379775317 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4379775317 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2429,38 +2411,38 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 132920.101961 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 132920.101961 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.813991 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120407.813991 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120495.278928 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120495.278928 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 133674.390947 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 133674.390947 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120011.385822 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120011.385822 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120102.430060 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120102.430060 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120102.430060 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120102.430060 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.600000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 21144626 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 21144626 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2548533560 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2548533560 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2569678186 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2569678186 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2569678186 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2569678186 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20332877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20332877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2534226880 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2534226880 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2554559757 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2554559757 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2554559757 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2554559757 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2469,587 +2451,591 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82920.101961 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82920.101961 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70354.835468 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70354.835468 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 144965 # number of replacements -system.l2c.tags.tagsinuse 65152.937424 # Cycle average of tags in use -system.l2c.tags.total_refs 609190 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 210433 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.894936 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 94596333000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6623.641464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.873340 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030778 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8717.297780 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6753.906827 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34978.887881 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.032858 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2236.963584 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3439.697056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2304.605856 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.101069 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001280 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 83674.390947 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 83674.390947 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69959.885159 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69959.885159 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70051.272575 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70051.272575 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70051.272575 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70051.272575 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 143599 # number of replacements +system.l2c.tags.tagsinuse 65154.346859 # Cycle average of tags in use +system.l2c.tags.total_refs 605481 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 209069 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.896082 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 94462980000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6720.710891 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 87.363500 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.029896 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8711.779777 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6725.180439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34970.113845 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.660518 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2224.966255 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3446.409233 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2253.132505 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.102550 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001333 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.133015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.103056 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533735 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.034133 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.052486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.035165 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994155 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31624 # 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average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 139796.117076 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108322.950558 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121397.498831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94470.334561 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 108545.308295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121397.498831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94470.334561 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 108545.308295 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197863.927895 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146864.503155 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167402.972051 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197827.840606 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146890.057627 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167421.474150 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102186.582520 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80905.072962 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92580.706733 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 519148 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 291431 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 639 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102138.754542 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80963.510773 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92591.249550 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 513996 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 285885 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 629 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38391 # Transaction distribution -system.membus.trans_dist::ReadResp 216211 # Transaction distribution -system.membus.trans_dist::WriteReq 31027 # Transaction distribution -system.membus.trans_dist::WriteResp 31027 # Transaction distribution -system.membus.trans_dist::WritebackDirty 141592 # Transaction distribution -system.membus.trans_dist::CleanEvict 19995 # Transaction distribution -system.membus.trans_dist::UpgradeReq 63966 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38983 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38395 # Transaction distribution +system.membus.trans_dist::ReadResp 216403 # Transaction distribution +system.membus.trans_dist::WriteReq 31030 # Transaction distribution +system.membus.trans_dist::WriteResp 31030 # Transaction distribution +system.membus.trans_dist::WritebackDirty 140287 # Transaction distribution +system.membus.trans_dist::CleanEvict 19048 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61128 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38691 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40431 # Transaction distribution -system.membus.trans_dist::ReadExResp 19912 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 177820 # Transaction distribution +system.membus.trans_dist::ReadExReq 40497 # Transaction distribution +system.membus.trans_dist::ReadExResp 19965 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 178008 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 4302 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::InvalidateResp 4238 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 782044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 854999 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 655043 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 777209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 850140 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19597036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19789560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19529832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19722372 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22107704 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 127509 # Total snoops (count) -system.membus.snoopTraffic 37120 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 426843 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011580 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.106987 # Request fanout histogram +system.membus.pkt_size::total 22040516 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 124379 # Total snoops (count) +system.membus.snoopTraffic 36224 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 423974 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011487 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.106558 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 421900 98.84% 98.84% # Request fanout histogram -system.membus.snoop_fanout::1 4943 1.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 419104 98.85% 98.85% # Request fanout histogram +system.membus.snoop_fanout::1 4870 1.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 426843 # Request fanout histogram -system.membus.reqLayer0.occupancy 94581999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 423974 # Request fanout histogram +system.membus.reqLayer0.occupancy 95170998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12496000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12519499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1014639485 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1006886251 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1151195264 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1152568025 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 6864902 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 6725047 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3081,78 +3067,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1123711 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 579018 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 224775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 30515 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 29083 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1432 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38394 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 569470 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31027 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31027 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 374544 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 155002 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 112494 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44031 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 156525 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51717 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51717 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 531080 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4357 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 3099 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1346867 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408809 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1755676 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38391932 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144124 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45536056 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 402215 # Total snoops (count) -system.toL2Bus.snoopTraffic 16179148 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 958128 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.409221 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.494721 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1101165 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 567136 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 209084 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 30878 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 29463 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1415 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38398 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 558656 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31030 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31030 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 370367 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 149733 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109212 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43837 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153049 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51538 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51538 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 520262 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4298 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 3081 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1372035 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 353597 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1725632 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 39251474 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5647218 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 44898692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 393768 # Total snoops (count) +system.toL2Bus.snoopTraffic 15844428 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 942231 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.393753 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.491645 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 567474 59.23% 59.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 389222 40.62% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1432 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 572640 60.77% 60.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 368176 39.07% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1415 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 958128 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 954442443 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 942231 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 939495440 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1977326 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1962409 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 723838248 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 733983819 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 286417681 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 257943151 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index a1ac44f79..9ef8eea73 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.854886 # Number of seconds simulated -sim_ticks 2854886132500 # Number of ticks simulated -final_tick 2854886132500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.854944 # Number of seconds simulated +sim_ticks 2854944380500 # Number of ticks simulated +final_tick 2854944380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 259825 # Simulator instruction rate (inst/s) -host_op_rate 314145 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6635713455 # Simulator tick rate (ticks/s) -host_mem_usage 588360 # Number of bytes of host memory used -host_seconds 430.23 # Real time elapsed on the host -sim_insts 111784531 # Number of instructions simulated -sim_ops 135154718 # Number of ops (including micro ops) simulated +host_inst_rate 264512 # Simulator instruction rate (inst/s) +host_op_rate 319813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6754449586 # Simulator tick rate (ticks/s) +host_mem_usage 588784 # Number of bytes of host memory used +host_seconds 422.68 # Real time elapsed on the host +sim_insts 111803105 # Number of instructions simulated +sim_ops 135177203 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 7232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1667840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9176172 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 6784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1665024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9168492 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10852268 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1667840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1667840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7959296 # Number of bytes written to this memory +system.physmem.bytes_read::total 10841388 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1665024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1665024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7956736 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7976820 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 113 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26060 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143899 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7974260 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 106 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26016 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143779 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170088 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124364 # Number of write requests responded to by this memory +system.physmem.num_reads::total 169918 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124324 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128745 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 584205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3214199 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128705 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 583207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3211443 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3801296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 584205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 584205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2787956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3797408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 583207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 583207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2787002 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6138 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2794094 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2787956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 584205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3220337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2793140 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2787002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 583207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3217581 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6595390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170088 # Number of read requests accepted -system.physmem.writeReqs 128745 # Number of write requests accepted -system.physmem.readBursts 170088 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 128745 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10876160 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 7989120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10852268 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7976820 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6590548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 169918 # Number of read requests accepted +system.physmem.writeReqs 128705 # Number of write requests accepted +system.physmem.readBursts 169918 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 128705 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10866560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue +system.physmem.bytesWritten 7986688 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10841388 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7974260 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10602 # Per bank write bursts -system.physmem.perBankRdBursts::1 10348 # Per bank write bursts -system.physmem.perBankRdBursts::2 10682 # Per bank write bursts -system.physmem.perBankRdBursts::3 10189 # Per bank write bursts -system.physmem.perBankRdBursts::4 13369 # Per bank write bursts -system.physmem.perBankRdBursts::5 10294 # Per bank write bursts -system.physmem.perBankRdBursts::6 10368 # Per bank write bursts -system.physmem.perBankRdBursts::7 10838 # Per bank write bursts -system.physmem.perBankRdBursts::8 10130 # Per bank write bursts -system.physmem.perBankRdBursts::9 10489 # Per bank write bursts -system.physmem.perBankRdBursts::10 10055 # Per bank write bursts -system.physmem.perBankRdBursts::11 9592 # Per bank write bursts -system.physmem.perBankRdBursts::12 10755 # Per bank write bursts -system.physmem.perBankRdBursts::13 11804 # Per bank write bursts -system.physmem.perBankRdBursts::14 10513 # Per bank write bursts -system.physmem.perBankRdBursts::15 9912 # Per bank write bursts -system.physmem.perBankWrBursts::0 7846 # Per bank write bursts -system.physmem.perBankWrBursts::1 7741 # Per bank write bursts -system.physmem.perBankWrBursts::2 8334 # Per bank write bursts -system.physmem.perBankWrBursts::3 7790 # Per bank write bursts -system.physmem.perBankWrBursts::4 7606 # Per bank write bursts -system.physmem.perBankWrBursts::5 7522 # Per bank write bursts -system.physmem.perBankWrBursts::6 7517 # Per bank write bursts -system.physmem.perBankWrBursts::7 7997 # Per bank write bursts -system.physmem.perBankWrBursts::8 7756 # Per bank write bursts -system.physmem.perBankWrBursts::9 7896 # Per bank write bursts -system.physmem.perBankWrBursts::10 7435 # Per bank write bursts -system.physmem.perBankWrBursts::11 7391 # Per bank write bursts -system.physmem.perBankWrBursts::12 8149 # Per bank write bursts -system.physmem.perBankWrBursts::13 8812 # Per bank write bursts -system.physmem.perBankWrBursts::14 7798 # Per bank write bursts -system.physmem.perBankWrBursts::15 7240 # Per bank write bursts +system.physmem.perBankRdBursts::0 10675 # Per bank write bursts +system.physmem.perBankRdBursts::1 10444 # Per bank write bursts +system.physmem.perBankRdBursts::2 10743 # Per bank write bursts +system.physmem.perBankRdBursts::3 10387 # Per bank write bursts +system.physmem.perBankRdBursts::4 13022 # Per bank write bursts +system.physmem.perBankRdBursts::5 10182 # Per bank write bursts +system.physmem.perBankRdBursts::6 10267 # Per bank write bursts +system.physmem.perBankRdBursts::7 10712 # Per bank write bursts +system.physmem.perBankRdBursts::8 10430 # Per bank write bursts +system.physmem.perBankRdBursts::9 10642 # Per bank write bursts +system.physmem.perBankRdBursts::10 10231 # Per bank write bursts +system.physmem.perBankRdBursts::11 9545 # Per bank write bursts +system.physmem.perBankRdBursts::12 10746 # Per bank write bursts +system.physmem.perBankRdBursts::13 11530 # Per bank write bursts +system.physmem.perBankRdBursts::14 10184 # Per bank write bursts +system.physmem.perBankRdBursts::15 10050 # Per bank write bursts +system.physmem.perBankWrBursts::0 7937 # Per bank write bursts +system.physmem.perBankWrBursts::1 7870 # Per bank write bursts +system.physmem.perBankWrBursts::2 8420 # Per bank write bursts +system.physmem.perBankWrBursts::3 7905 # Per bank write bursts +system.physmem.perBankWrBursts::4 7296 # Per bank write bursts +system.physmem.perBankWrBursts::5 7361 # Per bank write bursts +system.physmem.perBankWrBursts::6 7425 # Per bank write bursts +system.physmem.perBankWrBursts::7 7903 # Per bank write bursts +system.physmem.perBankWrBursts::8 7956 # Per bank write bursts +system.physmem.perBankWrBursts::9 8136 # Per bank write bursts +system.physmem.perBankWrBursts::10 7613 # Per bank write bursts +system.physmem.perBankWrBursts::11 7341 # Per bank write bursts +system.physmem.perBankWrBursts::12 8127 # Per bank write bursts +system.physmem.perBankWrBursts::13 8673 # Per bank write bursts +system.physmem.perBankWrBursts::14 7491 # Per bank write bursts +system.physmem.perBankWrBursts::15 7338 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 69 # Number of times write queue was full causing retry -system.physmem.totGap 2854885682000 # Total gap between requests +system.physmem.numWrRetry 64 # Number of times write queue was full causing retry +system.physmem.totGap 2854943930000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169531 # Read request sizes (log2) +system.physmem.readPktSize::6 169361 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124364 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 160094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124324 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 159846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -160,121 +160,123 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60347 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.612325 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.506399 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.136235 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21716 35.99% 35.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14599 24.19% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6802 11.27% 71.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3528 5.85% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2551 4.23% 81.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1581 2.62% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1111 1.84% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1010 1.67% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7449 12.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60347 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6172 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.532242 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 583.546907 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6171 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 166 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.418122 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.510807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.995418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21664 35.90% 35.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14701 24.36% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6745 11.18% 71.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3562 5.90% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2510 4.16% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1679 2.78% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1014 1.68% 85.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1006 1.67% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7465 12.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60346 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6177 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.486158 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 583.334644 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6176 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6172 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6172 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.225211 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.326492 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 15.268498 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5463 88.51% 88.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 63 1.02% 89.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.53% 90.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 41 0.66% 90.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 274 4.44% 95.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 26 0.42% 95.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.23% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.13% 95.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.16% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.06% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.26% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6177 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6177 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.202687 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.306581 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.265718 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5466 88.49% 88.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 67 1.08% 89.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 30 0.49% 90.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 47 0.76% 90.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 264 4.27% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 28 0.45% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 18 0.29% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.10% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.15% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.11% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.26% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 7 0.11% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 140 2.27% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.08% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.10% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.05% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.05% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 11 0.18% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.05% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.23% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 6 0.10% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.06% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.10% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 143 2.32% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 7 0.11% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.08% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 11 0.18% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.05% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.23% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.06% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 5 0.08% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6172 # Writes before turning the bus around for reads -system.physmem.totQLat 4562123250 # Total ticks spent queuing -system.physmem.totMemAccLat 7748498250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849700000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26845.49 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6177 # Writes before turning the bus around for reads +system.physmem.totQLat 4574555750 # Total ticks spent queuing +system.physmem.totMemAccLat 7758118250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 848950000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26942.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45595.49 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 45692.43 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s @@ -284,52 +286,52 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.21 # Average write queue length when enqueuing -system.physmem.readRowHits 140395 # Number of row buffer hits during reads -system.physmem.writeRowHits 94027 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.31 # Row buffer hit rate for writes -system.physmem.avgGap 9553448.52 # Average gap between requests -system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 217784280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 115755090 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 618966600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 325482660 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6028389120.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4546972650 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 380659200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12537712590 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8446773120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 671876398965 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 705097688865 # Total energy per rank (pJ) -system.physmem_0.averagePower 246.979269 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2843583812750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 720868250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2563490000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2794425375000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21996678750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7684667500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 27495053000 # Time in different power states -system.physmem_1.actEnergy 213100440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 113261775 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 594405000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 326129940 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6103375200.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4480349340 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 365416320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 12364122510 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8637319200 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 671971041390 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 705171178185 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.005010 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2844103138750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 682770250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2596086000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2794495958000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 22493040000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7504072000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 27114206250 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 25.37 # Average write queue length when enqueuing +system.physmem.readRowHits 140247 # Number of row buffer hits during reads +system.physmem.writeRowHits 93988 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.30 # Row buffer hit rate for writes +system.physmem.avgGap 9560361.83 # Average gap between requests +system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 217834260 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 115781655 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 617124480 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 324250740 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6010564560.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4580096490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 375795840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12507827490 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8401113600 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 671912403285 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 705065679060 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.963017 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2843582682250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 706056250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2555890000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2794607920750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21877952250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7767045000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 27429516250 # Time in different power states +system.physmem_1.actEnergy 213043320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 113231415 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595176120 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 327163500 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6093540960.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4507043580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 367350240 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 12209497470 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8677272480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 672029778480 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 705136507095 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.987826 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2844096160000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 691055750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2591938000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2794723975250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 22596980000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7565161250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 26775270250 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory @@ -342,30 +344,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 179 system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31050902 # Number of BP lookups -system.cpu.branchPred.condPredicted 16823011 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2467385 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18598277 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10398347 # Number of BTB hits +system.cpu.branchPred.lookups 31068063 # Number of BP lookups +system.cpu.branchPred.condPredicted 16834819 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2474290 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18684214 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10413110 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 55.910271 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7909634 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1502216 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3035557 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2846976 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 188581 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 109207 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 55.732128 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7904720 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1504932 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3038151 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2849063 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 189088 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 109706 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -395,57 +397,59 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 67916 # Table walker walks requested -system.cpu.dtb.walker.walksShort 67916 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44853 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23063 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 67916 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 67916 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 67916 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7871 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10132.638801 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8470.700593 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 9365.136659 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 7864 99.91% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7871 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 67808 # Table walker walks requested +system.cpu.dtb.walker.walksShort 67808 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44545 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23263 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 67808 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 67808 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 67808 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7897 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10074.838546 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8443.809763 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7240.808120 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 7014 88.82% 88.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 876 11.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 5 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::245760-262143 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7897 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 276581000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 276581000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 276581000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6482 82.35% 82.35% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1389 17.65% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7871 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67916 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6507 82.40% 82.40% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1390 17.60% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7897 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67808 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67916 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7871 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67808 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7897 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7871 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 75787 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7897 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 75705 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24685993 # DTB read hits -system.cpu.dtb.read_misses 61030 # DTB read misses -system.cpu.dtb.write_hits 19409907 # DTB write hits -system.cpu.dtb.write_misses 6886 # DTB write misses +system.cpu.dtb.read_hits 24693754 # DTB read hits +system.cpu.dtb.read_misses 60831 # DTB read misses +system.cpu.dtb.write_hits 19411318 # DTB write hits +system.cpu.dtb.write_misses 6977 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4276 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1444 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1826 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4277 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24747023 # DTB read accesses -system.cpu.dtb.write_accesses 19416793 # DTB write accesses +system.cpu.dtb.perms_faults 779 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24754585 # DTB read accesses +system.cpu.dtb.write_accesses 19418295 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44095900 # DTB hits -system.cpu.dtb.misses 67916 # DTB misses -system.cpu.dtb.accesses 44163816 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 44105072 # DTB hits +system.cpu.dtb.misses 67808 # DTB misses +system.cpu.dtb.accesses 44172880 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -475,39 +479,39 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 5836 # Table walker walks requested -system.cpu.itb.walker.walksShort 5836 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 323 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5513 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5836 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5836 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5836 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3199 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10502.500781 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8663.235820 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 6980.719897 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1845 57.67% 57.67% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 784 24.51% 82.18% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 564 17.63% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 5 0.16% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 5860 # Table walker walks requested +system.cpu.itb.walker.walksShort 5860 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5541 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5860 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5860 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5860 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3216 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10484.452736 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8664.992606 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 6927.635793 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1845 57.37% 57.37% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 815 25.34% 82.71% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 549 17.07% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 6 0.19% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3199 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3216 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 276141500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 276141500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 276141500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2889 90.31% 90.31% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.69% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3199 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 2906 90.36% 90.36% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.64% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3216 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5836 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5836 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5860 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5860 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3199 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3199 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 9035 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57468050 # ITB inst hits -system.cpu.itb.inst_misses 5836 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3216 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3216 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 9076 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57505769 # ITB inst hits +system.cpu.itb.inst_misses 5860 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -516,45 +520,45 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2922 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2934 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8328 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57473886 # ITB inst accesses -system.cpu.itb.hits 57468050 # DTB hits -system.cpu.itb.misses 5836 # DTB misses -system.cpu.itb.accesses 57473886 # DTB accesses +system.cpu.itb.inst_accesses 57511629 # ITB inst accesses +system.cpu.itb.hits 57505769 # DTB hits +system.cpu.itb.misses 5860 # DTB misses +system.cpu.itb.accesses 57511629 # DTB accesses system.cpu.numPwrStateTransitions 6066 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887944293.276624 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17437791477.805088 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887942089.664688 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17437807884.014717 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499966835544 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499966671100 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 161751090992 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2693135041508 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 323505132 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 161816022547 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2693128357953 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 323634999 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 111784531 # Number of instructions committed -system.cpu.committedOps 135154718 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7776689 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 111803105 # Number of instructions committed +system.cpu.committedOps 135177203 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7783284 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5386331427 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.894006 # CPI: cycles per instruction -system.cpu.ipc 0.345542 # IPC: instructions per cycle +system.cpu.quiesceCycles 5386318328 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.894687 # CPI: cycles per instruction +system.cpu.ipc 0.345460 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 90595549 67.03% 67.03% # Class of committed instruction -system.cpu.op_class_0::IntMult 113150 0.08% 67.12% # Class of committed instruction +system.cpu.op_class_0::IntAlu 90612203 67.03% 67.03% # Class of committed instruction +system.cpu.op_class_0::IntMult 113141 0.08% 67.12% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction @@ -580,519 +584,519 @@ system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Cl system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 8471 0.01% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 8473 0.01% 67.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::MemRead 24195627 17.90% 85.02% # Class of committed instruction -system.cpu.op_class_0::MemWrite 20228352 14.97% 99.99% # Class of committed instruction +system.cpu.op_class_0::MemRead 24199534 17.90% 85.03% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20230283 14.97% 99.99% # Class of committed instruction system.cpu.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction system.cpu.op_class_0::FloatMemWrite 8524 0.01% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 135154718 # Class of committed instruction +system.cpu.op_class_0::total 135177203 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.tickCycles 217865051 # Number of cycles that the object actually ticked -system.cpu.idleCycles 105640081 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 843791 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.945118 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42554576 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 844303 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.402019 # Average number of references to valid blocks. +system.cpu.tickCycles 217984467 # Number of cycles that the object actually ticked +system.cpu.idleCycles 105650532 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 844606 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.945154 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42562338 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 845118 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.362598 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 330588500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.945118 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.945154 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999893 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 364 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 175868835 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 175868835 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23043762 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23043762 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18247268 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18247268 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 357174 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 357174 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443432 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443432 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460038 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460038 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41291030 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41291030 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41648204 # number of overall hits -system.cpu.dcache.overall_hits::total 41648204 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 465012 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 465012 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 548381 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 548381 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 168658 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 168658 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22398 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22398 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 175904316 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 175904316 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23049763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23049763 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18249075 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18249075 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 357182 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 357182 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443419 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443419 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460030 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460030 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41298838 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41298838 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41656020 # number of overall hits +system.cpu.dcache.overall_hits::total 41656020 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 464983 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 464983 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 548530 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 548530 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169407 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169407 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22402 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22402 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1013393 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1013393 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1182051 # number of overall misses -system.cpu.dcache.overall_misses::total 1182051 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7327923000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7327923000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26756956980 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26756956980 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306920500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 306920500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 171000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 171000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34084879980 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34084879980 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34084879980 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34084879980 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23508774 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23508774 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18795649 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18795649 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 525832 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 525832 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465830 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465830 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460040 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460040 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42304423 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42304423 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42830255 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42830255 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019780 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.019780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029176 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029176 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.320745 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.320745 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048082 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048082 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 1013513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1013513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1182920 # number of overall misses +system.cpu.dcache.overall_misses::total 1182920 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7335235000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7335235000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26749219979 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26749219979 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303724500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 303724500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 169000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 169000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34084454979 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34084454979 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34084454979 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34084454979 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23514746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23514746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18797605 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18797605 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526589 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526589 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465821 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465821 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460032 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460032 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42312351 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42312351 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42838940 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42838940 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019774 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.019774 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029181 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029181 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321706 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.321706 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048091 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048091 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023955 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023955 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.027599 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.027599 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15758.567521 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15758.567521 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48792.640482 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48792.640482 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13703.031521 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13703.031521 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 85500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 85500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33634.414270 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33634.414270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28835.371723 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28835.371723 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.023953 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027613 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027613 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15775.275655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15775.275655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48765.281715 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48765.281715 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13557.918936 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13557.918936 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 84500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 84500 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33630.012618 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33630.012618 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28813.829320 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28813.829320 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 813 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.571429 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.954545 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 701301 # number of writebacks -system.cpu.dcache.writebacks::total 701301 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45802 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45802 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 249489 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14157 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14157 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 295291 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 295291 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 295291 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 295291 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419210 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 419210 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298892 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298892 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 120813 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 120813 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8241 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8241 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 701993 # number of writebacks +system.cpu.dcache.writebacks::total 701993 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45638 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45638 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249404 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 249404 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14200 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14200 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 295042 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 295042 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 295042 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 295042 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419345 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 419345 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299126 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299126 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121262 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 121262 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8202 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8202 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 718102 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 718102 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 838915 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 838915 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 718471 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 718471 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 839733 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 839733 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438741500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438741500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14235579000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14235579000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1652909500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1652909500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 122323000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 122323000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20674320500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20674320500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22327230000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22327230000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305432000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305432000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305432000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305432000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015902 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.229756 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.229756 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017691 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017691 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6449852500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6449852500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14240256000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14240256000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1658671000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1658671000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118600500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118600500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 167000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 167000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20690108500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20690108500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22348779500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22348779500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305317500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305317500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305317500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305317500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017833 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017833 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015913 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015913 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230278 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230278 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017608 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017608 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016975 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016975 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019587 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019587 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15359.226879 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15359.226879 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47627.835472 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47627.835472 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13681.553310 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13681.553310 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14843.222910 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14843.222910 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 84500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 84500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28790.228268 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28790.228268 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26614.412664 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26614.412664 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202551.622229 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202551.622229 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107392.308478 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107392.308478 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2889413 # number of replacements -system.cpu.icache.tags.tagsinuse 511.370681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54569461 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2889925 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.882656 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 16116553500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.370681 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998771 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998771 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016980 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016980 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019602 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019602 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15380.778357 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15380.778357 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47606.212767 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47606.212767 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13678.407085 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13678.407085 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14459.948793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14459.948793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 83500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 83500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28797.416319 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28797.416319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26614.149378 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26614.149378 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202547.944105 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202547.944105 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107390.358347 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107390.358347 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2890432 # number of replacements +system.cpu.icache.tags.tagsinuse 511.371135 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54606166 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2890944 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.888697 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 16096310500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.371135 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998772 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998772 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60349332 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60349332 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12771.709996 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12771.709996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12771.709996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12771.709996 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050280 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050280 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050280 # 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average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 96873 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65145.709178 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7314750 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162275 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 45.076259 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 99924187000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 73.512854 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023684 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 12110.922280 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 52961.250360 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184798 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.808125 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994045 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65344 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4564 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60694 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000885 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 60034528 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 60034528 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67803 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3361 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 71164 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 701301 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 701301 # 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number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 2866935 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 700447 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3638546 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 67803 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3361 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 2866935 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 700447 # number of overall hits -system.cpu.l2cache.overall_hits::total 3638546 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 113 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 96713 # 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average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112219.003599 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94710.112409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85537.594613 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86966.695642 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94710.112409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85537.594613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86966.695642 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436355 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436355 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007924 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001553 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000592 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.043764 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001553 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000592 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.043764 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 86750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 320837.962963 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82802.310744 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82802.310744 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94399.009080 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94399.009080 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 111619.350332 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 111619.350332 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 86750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94399.009080 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85674.504261 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87026.272204 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 86750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94399.009080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85674.504261 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87026.272204 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190049.261163 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179072.469269 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190045.518792 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179069.067710 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100763.591307 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99187.375673 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 7501348 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3767098 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100761.607112 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99185.491566 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 7504755 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768676 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58052 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 184 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 184 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 136577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3574918 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 136721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3576628 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 789475 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2889413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 151189 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2821 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 790127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2890432 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 151192 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2791 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2889936 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 548482 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 4413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8675486 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2655698 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14711 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158895 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11504790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370075584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99113193 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 271664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 469473889 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 132758 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5779048 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 4002764 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.022319 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.147720 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2793 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2890956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 549028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 4410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8678540 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2658068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159341 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11510728 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370205760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99209257 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 273080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 469701609 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 132371 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5775904 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 4004544 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.022245 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.147479 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3913425 97.77% 97.77% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 89339 2.23% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3915463 97.78% 97.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 89081 2.22% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4002764 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7421735500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4004544 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7425335000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 289875 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 287877 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4340119421 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4341709800 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1313068534 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1314266535 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 11352493 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 11403994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 91007942 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 91100441 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1291,29 +1295,29 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46393500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46325500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 613000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 623000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) @@ -1323,34 +1327,34 @@ system.iobus.reqLayer19.occupancy 2500 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6090000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6084500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 39095500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 39097500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187683346 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187729822 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.033754 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.033985 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272028370000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.033754 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064610 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064610 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 272037045000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.033985 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064624 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064624 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1359,14 +1363,14 @@ system.iocache.demand_misses::realview.ide 36458 # system.iocache.demand_misses::total 36458 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36458 # number of overall misses system.iocache.overall_misses::total 36458 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29456377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29456377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4371874969 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4371874969 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4401331346 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4401331346 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4401331346 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4401331346 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 37405377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 37405377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4361655445 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4361655445 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4399060822 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4399060822 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4399060822 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4399060822 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1383,14 +1387,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125881.952991 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125881.952991 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120690.011291 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120690.011291 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120723.334961 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120723.334961 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120723.334961 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120723.334961 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 159852.038462 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 159852.038462 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.891039 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120407.891039 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120661.057162 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120661.057162 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120661.057162 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120661.057162 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1407,14 +1411,14 @@ system.iocache.demand_mshr_misses::realview.ide 36458 system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17756377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17756377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2558822831 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2558822831 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2576579208 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2576579208 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2576579208 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2576579208 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 25705377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 25705377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2548589823 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2548589823 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2574295200 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2574295200 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2574295200 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2574295200 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1423,91 +1427,91 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75881.952991 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75881.952991 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70638.881156 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70638.881156 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70672.532997 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70672.532997 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70672.532997 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70672.532997 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 336642 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 137901 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 539 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109852.038462 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 109852.038462 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70356.388665 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70356.388665 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70609.885348 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70609.885348 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70609.885348 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70609.885348 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 336307 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 137733 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 538 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34249 # Transaction distribution -system.membus.trans_dist::ReadResp 71720 # Transaction distribution +system.membus.trans_dist::ReadResp 71814 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124364 # Transaction distribution -system.membus.trans_dist::CleanEvict 8933 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124324 # Transaction distribution +system.membus.trans_dist::CleanEvict 8813 # Transaction distribution system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 129451 # Transaction distribution -system.membus.trans_dist::ReadExResp 129451 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37471 # Transaction distribution +system.membus.trans_dist::ReadExReq 129187 # Transaction distribution +system.membus.trans_dist::ReadExResp 129187 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37565 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 4363 # Transaction distribution +system.membus.trans_dist::InvalidateResp 4361 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446194 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445694 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553262 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 626659 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 626159 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16511968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16675753 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16498528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16662313 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18992873 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 4867 # Total snoops (count) +system.membus.pkt_size::total 18979433 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 4865 # Total snoops (count) system.membus.snoopTraffic 32128 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 265109 # Request fanout histogram -system.membus.snoop_fanout::mean 0.018562 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.134973 # Request fanout histogram +system.membus.snoop_fanout::samples 264939 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018563 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.134975 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 260188 98.14% 98.14% # Request fanout histogram -system.membus.snoop_fanout::1 4921 1.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 260021 98.14% 98.14% # Request fanout histogram +system.membus.snoop_fanout::1 4918 1.86% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 265109 # Request fanout histogram -system.membus.reqLayer0.occupancy 92913500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 264939 # Request fanout histogram +system.membus.reqLayer0.occupancy 92843000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1694500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 904283412 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 903707925 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 988660500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 987836250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 5813415 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 5807414 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1539,28 +1543,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 2fb8c4409..27961363f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.826654 # Number of seconds simulated -sim_ticks 2826653666000 # Number of ticks simulated -final_tick 2826653666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826673 # Number of seconds simulated +sim_ticks 2826672558500 # Number of ticks simulated +final_tick 2826672558500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170078 # Simulator instruction rate (inst/s) -host_op_rate 206349 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4004321035 # Simulator tick rate (ticks/s) -host_mem_usage 626896 # Number of bytes of host memory used -host_seconds 705.90 # Real time elapsed on the host -sim_insts 120058397 # Number of instructions simulated -sim_ops 145661611 # Number of ops (including micro ops) simulated +host_inst_rate 170041 # Simulator instruction rate (inst/s) +host_op_rate 206302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4002646805 # Simulator tick rate (ticks/s) +host_mem_usage 627056 # Number of bytes of host memory used +host_seconds 706.20 # Real time elapsed on the host +sim_insts 120082757 # Number of instructions simulated +sim_ops 145690782 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 1664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1325840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1300840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8393920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1308688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1308456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8387648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 176672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 586900 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 432960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 193312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 594324 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 432320 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12220460 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1325840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 176672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1502512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8774720 # Number of bytes written to this memory +system.physmem.bytes_read::total 12228268 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1308688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 193312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1502000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8790464 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8792284 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 26 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20846 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 131155 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8808028 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131057 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2828 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9191 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3088 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9307 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6755 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193804 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 137105 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193926 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 137351 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141496 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 91 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 469049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 460205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2969561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 141742 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 462978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 462896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2967322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 158 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 62502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 207631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 153171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 68389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 210256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 152943 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4323296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 469049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 62502 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 531552 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3104278 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4326029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 462978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 68389 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 531367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3109827 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6200 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3110492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3104278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 91 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 469049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 466405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2969561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3116041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3109827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 462978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 469096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2967322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 158 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 62502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 207645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 153171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 68389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 210270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 152943 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7433788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 193805 # Number of read requests accepted -system.physmem.writeReqs 141496 # Number of write requests accepted -system.physmem.readBursts 193805 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 141496 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12392576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10880 # Total number of bytes read from write queue -system.physmem.bytesWritten 8805056 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12220524 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8792284 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 170 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7442070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 193927 # Number of read requests accepted +system.physmem.writeReqs 141742 # Number of write requests accepted +system.physmem.readBursts 193927 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141742 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12400768 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10496 # Total number of bytes read from write queue +system.physmem.bytesWritten 8820224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12228332 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8808028 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11925 # Per bank write bursts -system.physmem.perBankRdBursts::1 11855 # Per bank write bursts -system.physmem.perBankRdBursts::2 12297 # Per bank write bursts -system.physmem.perBankRdBursts::3 12187 # Per bank write bursts -system.physmem.perBankRdBursts::4 14909 # Per bank write bursts -system.physmem.perBankRdBursts::5 12660 # Per bank write bursts -system.physmem.perBankRdBursts::6 12587 # Per bank write bursts -system.physmem.perBankRdBursts::7 12794 # Per bank write bursts -system.physmem.perBankRdBursts::8 12033 # Per bank write bursts -system.physmem.perBankRdBursts::9 12070 # Per bank write bursts -system.physmem.perBankRdBursts::10 11247 # Per bank write bursts -system.physmem.perBankRdBursts::11 10141 # Per bank write bursts -system.physmem.perBankRdBursts::12 11323 # Per bank write bursts -system.physmem.perBankRdBursts::13 11835 # Per bank write bursts -system.physmem.perBankRdBursts::14 11954 # Per bank write bursts -system.physmem.perBankRdBursts::15 11817 # Per bank write bursts -system.physmem.perBankWrBursts::0 8684 # Per bank write bursts -system.physmem.perBankWrBursts::1 8734 # Per bank write bursts -system.physmem.perBankWrBursts::2 9001 # Per bank write bursts -system.physmem.perBankWrBursts::3 8790 # Per bank write bursts -system.physmem.perBankWrBursts::4 8747 # Per bank write bursts -system.physmem.perBankWrBursts::5 9254 # Per bank write bursts -system.physmem.perBankWrBursts::6 9144 # Per bank write bursts -system.physmem.perBankWrBursts::7 9206 # Per bank write bursts -system.physmem.perBankWrBursts::8 8582 # Per bank write bursts -system.physmem.perBankWrBursts::9 8592 # Per bank write bursts -system.physmem.perBankWrBursts::10 8144 # Per bank write bursts -system.physmem.perBankWrBursts::11 7450 # Per bank write bursts -system.physmem.perBankWrBursts::12 8375 # Per bank write bursts -system.physmem.perBankWrBursts::13 8211 # Per bank write bursts -system.physmem.perBankWrBursts::14 8456 # Per bank write bursts -system.physmem.perBankWrBursts::15 8209 # Per bank write bursts +system.physmem.perBankRdBursts::0 11912 # Per bank write bursts +system.physmem.perBankRdBursts::1 11892 # Per bank write bursts +system.physmem.perBankRdBursts::2 12330 # Per bank write bursts +system.physmem.perBankRdBursts::3 12174 # Per bank write bursts +system.physmem.perBankRdBursts::4 14942 # Per bank write bursts +system.physmem.perBankRdBursts::5 12676 # Per bank write bursts +system.physmem.perBankRdBursts::6 12556 # Per bank write bursts +system.physmem.perBankRdBursts::7 12785 # Per bank write bursts +system.physmem.perBankRdBursts::8 12022 # Per bank write bursts +system.physmem.perBankRdBursts::9 12081 # Per bank write bursts +system.physmem.perBankRdBursts::10 11226 # Per bank write bursts +system.physmem.perBankRdBursts::11 10162 # Per bank write bursts +system.physmem.perBankRdBursts::12 11365 # Per bank write bursts +system.physmem.perBankRdBursts::13 11848 # Per bank write bursts +system.physmem.perBankRdBursts::14 11951 # Per bank write bursts +system.physmem.perBankRdBursts::15 11840 # Per bank write bursts +system.physmem.perBankWrBursts::0 8683 # Per bank write bursts +system.physmem.perBankWrBursts::1 8758 # Per bank write bursts +system.physmem.perBankWrBursts::2 9038 # Per bank write bursts +system.physmem.perBankWrBursts::3 8776 # Per bank write bursts +system.physmem.perBankWrBursts::4 8736 # Per bank write bursts +system.physmem.perBankWrBursts::5 9287 # Per bank write bursts +system.physmem.perBankWrBursts::6 9143 # Per bank write bursts +system.physmem.perBankWrBursts::7 9209 # Per bank write bursts +system.physmem.perBankWrBursts::8 8594 # Per bank write bursts +system.physmem.perBankWrBursts::9 8600 # Per bank write bursts +system.physmem.perBankWrBursts::10 8159 # Per bank write bursts +system.physmem.perBankWrBursts::11 7478 # Per bank write bursts +system.physmem.perBankWrBursts::12 8406 # Per bank write bursts +system.physmem.perBankWrBursts::13 8230 # Per bank write bursts +system.physmem.perBankWrBursts::14 8500 # Per bank write bursts +system.physmem.perBankWrBursts::15 8219 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 72 # Number of times write queue was full causing retry -system.physmem.totGap 2826653384500 # Total gap between requests +system.physmem.numWrRetry 60 # Number of times write queue was full causing retry +system.physmem.totGap 2826672288500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3091 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190135 # Read request sizes (log2) +system.physmem.readPktSize::6 190257 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 137105 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 58100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 269 # What read queue length does an incoming req see +system.physmem.writePktSize::6 137351 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 58372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12836 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8377 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 747 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 270 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -189,165 +189,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9465 # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1498 1.77% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 998 1.18% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 977 1.15% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8299 9.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 84669 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6797 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.488009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.388330 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6795 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3319 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 187 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 84506 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.118169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.721377 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.168687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42580 50.39% 50.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17667 20.91% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6229 7.37% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3460 4.09% 82.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2829 3.35% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1565 1.85% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 960 1.14% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 994 1.18% 90.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8222 9.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84506 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6824 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.393318 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.270042 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6822 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6797 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6797 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.241136 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.514528 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.610339 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 6111 89.91% 89.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 128 1.88% 91.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 273 4.02% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 31 0.46% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 13 0.19% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.21% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 146 2.15% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 13 0.19% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 11 0.16% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 7 0.10% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.12% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 5 0.07% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 4 0.06% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 8 0.12% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 6 0.09% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.03% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.04% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.07% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-327 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6797 # Writes before turning the bus around for reads -system.physmem.totQLat 9919718835 # Total ticks spent queuing -system.physmem.totMemAccLat 13550356335 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 968170000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51228.96 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6824 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.195780 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.530637 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.731147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5748 84.23% 84.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 362 5.30% 89.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 98 1.44% 90.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 53 0.78% 91.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 250 3.66% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 24 0.35% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.25% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 13 0.19% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 6 0.09% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.12% 96.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.15% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 144 2.11% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 13 0.19% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.10% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.09% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.10% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 7 0.10% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.07% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 5 0.07% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.13% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.07% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6824 # Writes before turning the bus around for reads +system.physmem.totQLat 10004432906 # Total ticks spent queuing +system.physmem.totMemAccLat 13637470406 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 968810000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51632.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 69978.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 70382.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing -system.physmem.readRowHits 161407 # Number of row buffer hits during reads -system.physmem.writeRowHits 85137 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.87 # Row buffer hit rate for writes -system.physmem.avgGap 8430196.70 # Average gap between requests -system.physmem.pageHitRate 74.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 316180620 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 168053985 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 722667960 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 373543200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4556326320.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4729873110 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240133440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 9128983770 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6579538080 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 667569876735 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 694387365510 # Total energy per rank (pJ) -system.physmem_0.averagePower 245.657037 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2815586462334 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 417040689 # Time in different power states -system.physmem_0.memoryStateTime::REF 1935564000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2778497008500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 17134268560 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8650044977 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 20019739274 # Time in different power states -system.physmem_1.actEnergy 288356040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 153264870 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 659878800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 344619180 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4568619120.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4738351860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 236664480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8828064240 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6766632480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 667633644195 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 694220207745 # Total energy per rank (pJ) -system.physmem_1.averagePower 245.597901 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2815641624954 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 407791169 # Time in different power states -system.physmem_1.memoryStateTime::REF 1940956000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2778660280000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17621547350 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8663293877 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 19359797604 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.32 # Average write queue length when enqueuing +system.physmem.readRowHits 161584 # Number of row buffer hits during reads +system.physmem.writeRowHits 85488 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.02 # Row buffer hit rate for writes +system.physmem.avgGap 8421010.84 # Average gap between requests +system.physmem.pageHitRate 74.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 316830360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 168399330 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 723046380 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 373908600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4521291840.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4723358580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 248942400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 9096613470 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6505168320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 667621594905 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 694301661855 # Total energy per rank (pJ) +system.physmem_0.averagePower 245.625060 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2815660418258 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 439528927 # Time in different power states +system.physmem_0.memoryStateTime::REF 1920369500 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2778771385500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16940567035 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8652241815 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 19948465723 # Time in different power states +system.physmem_1.actEnergy 286542480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 152300940 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 660414300 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 345490920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4558170240.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4719582900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 238189440 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8751236790 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6789483360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 667674392880 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 694177600920 # Total energy per rank (pJ) +system.physmem_1.averagePower 245.581186 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2815698296531 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 410333187 # Time in different power states +system.physmem_1.memoryStateTime::REF 1936500000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2778826050750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17681028809 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8627428782 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 19191216972 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory @@ -366,30 +379,30 @@ system.realview.nvmem.bw_inst_read::total 102 # I system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 53099847 # Number of BP lookups -system.cpu0.branchPred.condPredicted 24413538 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 933900 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 32114969 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 13973138 # Number of BTB hits +system.cpu0.branchPred.lookups 23882865 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15636955 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 931558 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 14470894 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9520533 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 43.509735 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15469071 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33231 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 10119740 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 9963994 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 155746 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 49057 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 65.790911 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3844072 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 34146 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 1359371 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 1203202 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 156169 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 49075 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,84 +432,83 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 65583 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65583 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25222 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18949 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 21412 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44171 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 487.310679 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3087.040611 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 42986 97.32% 97.32% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 897 2.03% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 125 0.28% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 93 0.21% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 33 0.07% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 20 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 15 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 66298 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 66298 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25087 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19168 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 22043 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44255 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 493.831206 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3088.958464 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 43053 97.28% 97.28% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 899 2.03% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 141 0.32% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 95 0.21% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 32 0.07% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44171 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 16005 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11349.047173 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9735.111358 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7638.174811 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 14581 91.10% 91.10% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1176 7.35% 98.45% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 210 1.31% 99.76% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 16 0.10% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 7 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 12 0.07% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 16005 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 82168586356 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.591771 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.502145 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 82111702356 99.93% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 39388000 0.05% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 7963500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4902500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2427000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 777000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 938000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 463500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 24500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 82168586356 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5127 78.72% 78.72% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1386 21.28% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6513 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65583 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 44255 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 16149 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11407.424608 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9685.730755 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 9901.207568 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 14668 90.83% 90.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1230 7.62% 98.45% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 211 1.31% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 16 0.10% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 4 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-245759 17 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 16149 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 86482404152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.594104 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.503301 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 86424292152 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 40499500 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 7958000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4655000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1502500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 969000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1099000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1428000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 86482404152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5106 78.70% 78.70% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1382 21.30% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6488 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66298 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65583 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6513 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66298 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6488 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6513 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 72096 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6488 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 72786 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23662283 # DTB read hits -system.cpu0.dtb.read_misses 55655 # DTB read misses -system.cpu0.dtb.write_hits 17589226 # DTB write hits -system.cpu0.dtb.write_misses 9928 # DTB write misses +system.cpu0.dtb.read_hits 17693188 # DTB read hits +system.cpu0.dtb.read_misses 55688 # DTB read misses +system.cpu0.dtb.write_hits 14580631 # DTB write hits +system.cpu0.dtb.write_misses 10610 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3427 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2234 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 159 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2213 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 915 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23717938 # DTB read accesses -system.cpu0.dtb.write_accesses 17599154 # DTB write accesses +system.cpu0.dtb.perms_faults 845 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17748876 # DTB read accesses +system.cpu0.dtb.write_accesses 14591241 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41251509 # DTB hits -system.cpu0.dtb.misses 65583 # DTB misses -system.cpu0.dtb.accesses 41317092 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 32273819 # DTB hits +system.cpu0.dtb.misses 66298 # DTB misses +system.cpu0.dtb.accesses 32340117 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -526,61 +538,64 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 10907 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10907 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3899 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5942 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 1066 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9841 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 431.460217 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2241.549622 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9464 96.17% 96.17% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 172 1.75% 97.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 123 1.25% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 49 0.50% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 6 0.06% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 19 0.19% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9841 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3645 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12380.384088 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11386.423562 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5549.123195 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 601 16.49% 16.49% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 2727 74.81% 91.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 175 4.80% 96.10% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 87 2.39% 98.49% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 49 1.34% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-73727 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 11677 # Table walker walks requested +system.cpu0.itb.walker.walksShort 11677 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3850 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6772 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 1055 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 10622 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1021.559028 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 3971.298769 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9829 92.53% 92.53% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 232 2.18% 94.72% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 234 2.20% 96.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 118 1.11% 98.03% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 84 0.79% 98.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 68 0.64% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 21 0.20% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 17 0.16% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 11 0.10% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-53247 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 10622 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3671 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12324.162354 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11375.149198 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5369.602272 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 593 16.15% 16.15% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 2793 76.08% 92.24% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 150 4.09% 96.32% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 91 2.48% 98.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 38 1.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3645 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 22038229712 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.837207 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.369334 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 3588883500 16.28% 16.28% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 18448211212 83.71% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 1065000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 22038229712 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2246 87.09% 87.09% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 333 12.91% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2579 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3671 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 22057105212 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.847252 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.360404 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3373925500 15.30% 15.30% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 18678889712 84.68% 99.98% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 3873000 0.02% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 379500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 37500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22057105212 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2281 87.19% 87.19% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 335 12.81% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2616 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10907 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10907 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11677 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11677 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2579 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2579 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13486 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 72758108 # ITB inst hits -system.cpu0.itb.inst_misses 10907 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2616 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2616 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 14293 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 37442886 # ITB inst hits +system.cpu0.itb.inst_misses 11677 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -589,1058 +604,1066 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2282 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2325 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1937 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2439 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 72769015 # ITB inst accesses -system.cpu0.itb.hits 72758108 # DTB hits -system.cpu0.itb.misses 10907 # DTB misses -system.cpu0.itb.accesses 72769015 # DTB accesses +system.cpu0.itb.inst_accesses 37454563 # ITB inst accesses +system.cpu0.itb.hits 37442886 # DTB hits +system.cpu0.itb.misses 11677 # DTB misses +system.cpu0.itb.accesses 37454563 # DTB accesses system.cpu0.numPwrStateTransitions 3670 # Number of power state transitions system.cpu0.pwrStateClkGateDist::samples 1835 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1484523232.318801 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23903491534.812244 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1057 57.60% 57.60% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 773 42.13% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1504014886.326976 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 24031487578.448807 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1058 57.66% 57.66% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 770 41.96% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 499970835992 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::total 1835 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 102553534695 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724100131305 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 205108250 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::ON 66805242090 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759867316410 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 133611951 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20843459 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 195936196 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 53099847 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 39406203 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 175823444 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5691288 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 148299 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 58157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 416860 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 413792 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 98564 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 72757810 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 257476 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5315 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 200648219 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.193498 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.306871 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 19303849 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 111829084 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 23882865 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 14567807 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 107369786 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2747392 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 153767 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 58387 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 435607 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 423633 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 97811 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 37442098 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 257331 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 6030 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 129216536 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.043099 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.255701 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 95712766 47.70% 47.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 30373277 15.14% 62.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14586568 7.27% 70.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 59975608 29.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67189169 52.00% 52.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 21288743 16.48% 68.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8719000 6.75% 75.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 32019624 24.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 200648219 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.258887 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.955282 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 25818393 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 108480918 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 58863420 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4969304 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2516184 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3061987 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 333558 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 154376244 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3806825 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2516184 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 34429607 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12873889 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 83899455 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 55085453 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11843631 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 137696782 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1037438 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1493634 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 164344 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 57817 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7635337 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 141807029 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 635200062 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 152788581 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9462 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 130609661 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11197357 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2697375 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2554361 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 22576827 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 24592847 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 19077592 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1691886 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2320615 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 134759616 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1714081 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 132897861 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 450666 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10595447 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21697472 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 119702 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 200648219 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.662343 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.961216 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 129216536 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.178748 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.836969 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19892285 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 62318410 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 41002144 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4961574 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1042123 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 8668351 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 335752 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 109935605 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3778741 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1042123 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 25542587 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12841185 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 37729185 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 40176897 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11884559 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 104971930 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1005936 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1490559 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 163297 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 57296 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7681326 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 109147487 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 479167735 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 120008007 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9453 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 98091135 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11056341 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1226764 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1083940 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12369905 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18622381 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 16045587 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1690063 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2196173 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 102089116 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1690972 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 100270845 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 450536 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9007472 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21276029 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 120459 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 129216536 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.775991 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.026149 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 123885975 61.74% 61.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 33618455 16.75% 78.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 31280513 15.59% 94.09% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 10734778 5.35% 99.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1128444 0.56% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 54 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 73187499 56.64% 56.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 23243158 17.99% 74.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 22432715 17.36% 91.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 9250445 7.16% 99.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1102673 0.85% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 46 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 200648219 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 129216536 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 10806493 43.96% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 67 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5620315 22.86% 66.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8146085 33.14% 99.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 2848 0.01% 99.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 7137 0.03% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 9305182 40.57% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 67 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5565388 24.27% 64.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8055351 35.12% 99.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 2851 0.01% 99.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 6938 0.03% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 89788621 67.56% 67.56% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 110178 0.08% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8088 0.01% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 24348007 18.32% 85.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 18629393 14.02% 99.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 3106 0.00% 99.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 8193 0.01% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 66163298 65.98% 65.99% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 92264 0.09% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8058 0.01% 66.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18375460 18.33% 84.41% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 15618206 15.58% 99.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 3108 0.00% 99.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 8177 0.01% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 132897861 # Type of FU issued -system.cpu0.iq.rate 0.647940 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 24582945 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.184976 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 491444928 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 147076893 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 129373990 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32623 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11320 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 157457242 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21291 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 367347 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 100270845 # Type of FU issued +system.cpu0.iq.rate 0.750463 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 22935777 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228738 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 353112143 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 112794988 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 98251090 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32395 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11310 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9716 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 123183269 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21080 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 364715 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1915298 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2464 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19139 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 903377 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1893331 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2466 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 881018 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 121005 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 360360 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 109546 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 360879 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2516184 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1671558 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 251575 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 136626375 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1042123 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1649895 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 244572 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 103932598 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 24592847 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 19077592 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 875905 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27780 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 199746 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19139 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 262593 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 398520 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 661113 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 131868425 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 23910267 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 963966 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 18622381 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 16045587 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 874828 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27967 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 192686 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18814 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 252890 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 404204 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 657094 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 99256545 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 17939836 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 948116 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 152678 # number of nop insts executed -system.cpu0.iew.exec_refs 42387378 # number of memory reference insts executed -system.cpu0.iew.exec_branches 25593933 # Number of branches executed -system.cpu0.iew.exec_stores 18477111 # Number of stores executed -system.cpu0.iew.exec_rate 0.642921 # Inst execution rate -system.cpu0.iew.wb_sent 131315181 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 129383707 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 66018205 # num instructions producing a value -system.cpu0.iew.wb_consumers 106739719 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.630807 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.618497 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9567606 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1594379 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 604440 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 197485844 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.638022 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.337140 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 152510 # number of nop insts executed +system.cpu0.iew.exec_refs 33405569 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16813883 # Number of branches executed +system.cpu0.iew.exec_stores 15465733 # Number of stores executed +system.cpu0.iew.exec_rate 0.742872 # Inst execution rate +system.cpu0.iew.wb_sent 98711091 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 98260806 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 51187228 # num instructions producing a value +system.cpu0.iew.wb_consumers 84552650 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.735419 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.605389 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 8010093 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1570513 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 599985 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 127532122 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.744084 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.464109 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 137054336 69.40% 69.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 33455560 16.94% 86.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12646051 6.40% 92.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3243439 1.64% 94.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4914257 2.49% 96.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2777569 1.41% 98.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1312207 0.66% 98.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 555201 0.28% 99.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1527224 0.77% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 83238506 65.27% 65.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 24683933 19.36% 84.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 8242078 6.46% 91.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3223359 2.53% 93.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3451127 2.71% 96.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1466865 1.15% 97.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1171264 0.92% 98.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 549844 0.43% 98.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1505146 1.18% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 197485844 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 104056922 # Number of instructions committed -system.cpu0.commit.committedOps 126000293 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 127532122 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 78880347 # Number of instructions committed +system.cpu0.commit.committedOps 94894659 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 40851763 # Number of memory references committed -system.cpu0.commit.loads 22677548 # Number of loads committed -system.cpu0.commit.membars 647714 # Number of memory barriers committed -system.cpu0.commit.branches 24989662 # Number of branches committed +system.cpu0.commit.refs 31893618 # Number of memory references committed +system.cpu0.commit.loads 16729049 # Number of loads committed +system.cpu0.commit.membars 646523 # Number of memory barriers committed +system.cpu0.commit.branches 16211772 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 109983283 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4835482 # Number of function calls committed. +system.cpu0.commit.int_insts 81832780 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1927003 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 85032586 67.49% 67.49% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 107857 0.09% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8087 0.01% 67.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 22675292 18.00% 85.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 18166767 14.42% 99.99% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 62903043 66.29% 66.29% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 89941 0.09% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8057 0.01% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 16726793 17.63% 84.02% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 15157121 15.97% 99.99% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemWrite 7448 0.01% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 126000293 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1527224 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 308240127 # The number of ROB reads -system.cpu0.rob.rob_writes 274288918 # The number of ROB writes -system.cpu0.timesIdled 136024 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 4460031 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5448199500 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 103934870 # Number of Instructions Simulated -system.cpu0.committedOps 125878241 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.973431 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.973431 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.506732 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.506732 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 142861191 # number of integer regfile reads -system.cpu0.int_regfile_writes 81742978 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8188 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2265 # number of floating regfile writes -system.cpu0.cc_regfile_reads 465378109 # number of cc regfile reads -system.cpu0.cc_regfile_writes 49818068 # number of cc regfile writes -system.cpu0.misc_regfile_reads 399016543 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1225433 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 712812 # number of replacements -system.cpu0.dcache.tags.tagsinuse 499.246418 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 37680999 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 713324 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.824522 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 94894659 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1505146 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 224742704 # The number of ROB reads +system.cpu0.rob.rob_writes 207484818 # The number of ROB writes +system.cpu0.timesIdled 136289 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 4395415 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5519733867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 78758295 # Number of Instructions Simulated +system.cpu0.committedOps 94772607 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.696481 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.696481 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.589455 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.589455 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 110218064 # number of integer regfile reads +system.cpu0.int_regfile_writes 59484746 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8170 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes +system.cpu0.cc_regfile_reads 349694687 # number of cc regfile reads +system.cpu0.cc_regfile_writes 40999571 # number of cc regfile writes +system.cpu0.misc_regfile_reads 254801117 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1223326 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 712506 # number of replacements +system.cpu0.dcache.tags.tagsinuse 498.213160 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28740042 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 713018 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.307597 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 296154500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.246418 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975091 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.975091 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.213160 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973073 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.973073 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81225267 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81225267 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 21467047 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21467047 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14989931 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14989931 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307917 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 307917 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363108 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363108 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361279 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361279 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 36456978 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 36456978 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 36764895 # number of overall hits -system.cpu0.dcache.overall_hits::total 36764895 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 649306 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 649306 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1896144 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1896144 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148546 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 148546 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25295 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25295 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20257 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20257 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2545450 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2545450 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2693996 # number of overall misses -system.cpu0.dcache.overall_misses::total 2693996 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9384044500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 9384044500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32956196365 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32956196365 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 411578000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 411578000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 478843500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 478843500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 432000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 432000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 42340240865 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 42340240865 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 42340240865 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 42340240865 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22116353 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22116353 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16886075 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16886075 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456463 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456463 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388403 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388403 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381536 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381536 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39002428 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39002428 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39458891 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39458891 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029359 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029359 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.112290 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.112290 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325428 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325428 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065126 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065126 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053093 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053093 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065264 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.065264 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068273 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.068273 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14452.422279 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14452.422279 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17380.640060 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17380.640060 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16271.120775 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.120775 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23638.421286 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23638.421286 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63341698 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63341698 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 15523802 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15523802 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 11993925 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 11993925 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307586 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 307586 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 362517 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 362517 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360768 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 360768 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27517727 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27517727 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 27825313 # number of overall hits +system.cpu0.dcache.overall_hits::total 27825313 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 649486 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 649486 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1895154 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1895154 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148364 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 148364 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25286 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25286 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20247 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20247 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2544640 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2544640 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2693004 # number of overall misses +system.cpu0.dcache.overall_misses::total 2693004 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9367064500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 9367064500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33076385872 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 33076385872 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 412133000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 412133000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 479472000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 479472000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 42443450372 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 42443450372 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 42443450372 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 42443450372 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16173288 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16173288 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13889079 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13889079 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 455950 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 455950 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387803 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387803 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381015 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381015 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30062367 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30062367 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30518317 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30518317 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040158 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.040158 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136449 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.136449 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325395 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325395 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065203 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065203 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084645 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.084645 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088242 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088242 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14422.273151 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14422.273151 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17453.138833 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17453.138833 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16298.861030 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16298.861030 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23681.137946 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23681.137946 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16633.695757 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16633.695757 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15716.519574 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15716.519574 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 757 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4969613 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 42 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 201973 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.023810 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 24.605333 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 712815 # number of writebacks -system.cpu0.dcache.writebacks::total 712815 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260774 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 260774 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1570443 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1570443 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18576 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18576 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1831217 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1831217 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1831217 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1831217 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388532 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 388532 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325701 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325701 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102377 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 102377 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6719 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6719 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20257 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20257 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 714233 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 714233 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 816610 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 816610 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32008 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28682 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60690 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5031436500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5031436500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6631878895 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6631878895 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1714108500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1714108500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107735000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107735000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 458598500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 458598500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 420000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 420000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11663315395 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11663315395 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13377423895 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13377423895 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6681974000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6681974000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6681974000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6681974000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017568 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017568 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019288 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019288 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224283 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224283 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017299 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017299 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053093 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053093 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018313 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018313 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020695 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020695 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12949.863846 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12949.863846 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20361.862245 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20361.862245 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16743.101478 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16743.101478 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16034.380116 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16034.380116 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22639.013674 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22639.013674 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16679.550102 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16679.550102 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15760.633988 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15760.633988 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 689 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4988118 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 201830 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.531250 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 24.714453 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 712509 # number of writebacks +system.cpu0.dcache.writebacks::total 712509 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 261058 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 261058 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1569543 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1569543 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18570 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18570 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830601 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1830601 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830601 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1830601 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388428 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 388428 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325611 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325611 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102372 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102372 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6716 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6716 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20247 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20247 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 714039 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 714039 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 816411 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 816411 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20577 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19269 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19269 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39846 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5013254500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5013254500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6647950897 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6647950897 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1709667500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1709667500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108314000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108314000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459237000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459237000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 442500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 442500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11661205397 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11661205397 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13370872897 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13370872897 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4595503500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4595503500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4595503500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4595503500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024017 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024017 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023444 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023444 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224525 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224525 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017318 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017318 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023752 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023752 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026752 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026752 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12906.521929 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12906.521929 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20416.849852 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20416.849852 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16700.538233 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16700.538233 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16127.754616 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16127.754616 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22681.730627 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22681.730627 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16329.846696 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16329.846696 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16381.655741 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16381.655741 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208759.497626 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208759.497626 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110100.082386 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110100.082386 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1249331 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.757700 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 71450204 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1249842 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 57.167389 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6584638000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757700 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16331.328397 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16331.328397 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16377.624624 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16377.624624 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223332.045488 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223332.045488 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115331.614215 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115331.614215 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1246758 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.757641 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36137139 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1247269 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.973011 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6586723000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757641 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 125 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 146758301 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 146758301 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 71450207 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 71450207 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 71450207 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 71450207 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 71450207 # number of overall hits -system.cpu0.icache.overall_hits::total 71450207 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1303999 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1303999 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1303999 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1303999 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1303999 # number of overall misses -system.cpu0.icache.overall_misses::total 1303999 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14174791933 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14174791933 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14174791933 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14174791933 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14174791933 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14174791933 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 72754206 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 72754206 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 72754206 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 72754206 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 72754206 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 72754206 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017923 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.017923 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017923 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.017923 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017923 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.017923 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10870.247549 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10870.247549 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10870.247549 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10870.247549 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10870.247549 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10870.247549 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1760744 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1640 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 114723 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 76124237 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 76124237 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 36137142 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36137142 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36137142 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36137142 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36137142 # number of overall hits +system.cpu0.icache.overall_hits::total 36137142 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1301318 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1301318 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1301318 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1301318 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1301318 # number of overall misses +system.cpu0.icache.overall_misses::total 1301318 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14070925518 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14070925518 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14070925518 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14070925518 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14070925518 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14070925518 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37438460 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37438460 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37438460 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37438460 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37438460 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37438460 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034759 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.034759 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034759 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.034759 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034759 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.034759 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10812.826318 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10812.826318 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10812.826318 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10812.826318 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10812.826318 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10812.826318 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1742114 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1649 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 114160 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.347786 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 126.153846 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1249331 # number of writebacks -system.cpu0.icache.writebacks::total 1249331 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54109 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54109 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54109 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54109 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54109 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54109 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1249890 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1249890 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1249890 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1249890 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1249890 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1249890 # number of overall MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.260284 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 126.846154 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 1246758 # number of writebacks +system.cpu0.icache.writebacks::total 1246758 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54000 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54000 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54000 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54000 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54000 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54000 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1247318 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1247318 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1247318 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1247318 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1247318 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1247318 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3008 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3008 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12814231927 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12814231927 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12814231927 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12814231927 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12814231927 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12814231927 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12734729518 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12734729518 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12734729518 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12734729518 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12734729518 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12734729518 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 287646998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 287646998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 287646998 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 287646998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017180 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.017180 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.017180 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10252.287743 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10252.287743 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10252.287743 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033316 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033316 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10209.689524 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10209.689524 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10209.689524 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846767 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1849379 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2365 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1845705 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1848223 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2284 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 236461 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 270933 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15649.129225 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1883932 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 286558 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.574348 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 235089 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 270085 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15641.965642 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1885208 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 285711 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.598304 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14546.798617 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.022626 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.137647 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1090.170335 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.887866 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000734 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.066539 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.955147 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 298 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15316 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 145 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 80 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1433 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7528 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4690 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1338 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018188 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.934814 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 67601036 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 67601036 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54858 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13069 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 67927 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 483646 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 483646 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1447155 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1447155 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221212 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 221212 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1179291 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1179291 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 390010 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 390010 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54858 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13069 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1179291 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 611222 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1858440 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54858 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13069 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1179291 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 611222 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1858440 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 514 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 209 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 723 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55801 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55801 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20257 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20257 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48873 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 48873 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70560 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 70560 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107498 # 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number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 963844000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 963844000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 306251499 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 306251499 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 352500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 352500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2242873000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2242873000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3286309500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3286309500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2812269499 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2812269499 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 14785500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3455500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3286309500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5055142499 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 8359692999 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 14785500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3455500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3286309500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5055142499 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17281059402 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 25640752401 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265086000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6425579500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6690665500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4430574500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4695660500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 265086000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6425579500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6690665500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010473 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4430574500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4695660500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010253 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159346 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159346 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056423 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.214489 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.214489 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195086 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105933 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195086 # mshr miss rate for overall accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159784 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159784 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.055981 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.214650 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.214650 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195345 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105720 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195345 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231821 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22965.229485 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65364.722441 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65364.722441 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17300.908568 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300.908568 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15082.588735 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15082.588735 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52203.371494 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52203.371494 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47450.375780 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26557.534411 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26557.534411 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33928.098700 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38207.594581 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33928.098700 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65364.722441 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52954.993207 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231489 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25194.751381 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65891.093435 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65891.093435 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17281.242156 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17281.242156 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15126.518769 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15126.518769 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 352500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 352500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51984.540503 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51984.540503 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47065.614975 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26340.496965 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26340.496965 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33720.957762 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37919.490694 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33720.957762 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65891.093435 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53116.576279 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200749.172082 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 191074.523075 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215316.834330 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 199095.208819 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105875.424287 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 105037.293165 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 4075722 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2058160 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32446 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 214641 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212781 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1860 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 113949 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1910077 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28682 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28682 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 713807 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1478497 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 89121 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 330731 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42853 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113662 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111192.453446 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109573.447053 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 4070347 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2055545 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32650 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 214495 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1888 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 104418 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1897981 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19269 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19269 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 712665 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1476401 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 88407 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 330099 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42827 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113743 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288564 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284982 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1249890 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 587175 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3237 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288516 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284937 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1247318 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 587795 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3260 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3755087 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2622795 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29061 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 118492 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6525435 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159995712 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99013924 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53112 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 221488 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 259284236 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 927446 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18848064 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3052004 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.088140 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.285640 # Request fanout histogram +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3747367 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2580614 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32197 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119234 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6479412 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159666240 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98907572 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59212 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223244 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 258856268 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 926807 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18833272 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3029449 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.088921 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.286812 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2784861 91.25% 91.25% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 265283 8.69% 99.94% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1860 0.06% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2761954 91.17% 91.17% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 265607 8.77% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1888 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3052004 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4075635489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3029449 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4055747992 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114371967 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114619003 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1878285609 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1874463037 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1237556949 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1221112489 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15793479 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 17401984 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63149938 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63454935 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4617850 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2715513 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 269466 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2413279 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1525969 # Number of BTB hits +system.cpu1.branchPred.lookups 33856624 # Number of BP lookups +system.cpu1.branchPred.condPredicted 11500186 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 284574 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 18698220 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5965214 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 63.232183 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 876806 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7196 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 247807 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 212871 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 34936 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 10588 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 31.902577 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12503434 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7767 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 9010077 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 8973983 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 36094 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 10763 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1670,95 +1693,95 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 21585 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 21585 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8697 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5905 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6983 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 14602 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 620.599918 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3321.361869 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 13932 95.41% 95.41% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 194 1.33% 96.74% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 228 1.56% 98.30% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 109 0.75% 99.05% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 24 0.16% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 26 0.18% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 9 0.06% 99.45% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.44% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 7 0.05% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 6 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 14602 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5436 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11628.403238 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9929.194928 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8303.343609 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1858 34.18% 34.18% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2915 53.62% 87.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 446 8.20% 96.01% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 133 2.45% 98.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 34 0.63% 99.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.46% 99.54% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 6 0.11% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 11 0.20% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 7 0.13% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5436 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 81885681356 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.177146 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.385706 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 67426452132 82.34% 82.34% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 14437765724 17.63% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 12512000 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 4018500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 1336000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 984500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 1256500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 435000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 231000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 183500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 98500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 31000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 125000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 29500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 188500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 81885681356 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1913 75.20% 75.20% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 631 24.80% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2544 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21585 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 21842 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21842 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8830 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5887 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7125 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14717 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 626.588299 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3443.893339 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 14047 95.45% 95.45% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 191 1.30% 96.75% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 228 1.55% 98.29% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 115 0.78% 99.08% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 21 0.14% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.16% 99.37% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 7 0.05% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 61 0.41% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 9 0.06% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 3 0.02% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-45055 7 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::57344-61439 4 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14717 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5501 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11163.061262 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9675.830911 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6263.258432 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1953 35.50% 35.50% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2904 52.79% 88.29% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 452 8.22% 96.51% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 149 2.71% 99.22% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 15 0.27% 99.49% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 22 0.40% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 4 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5501 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 77610116560 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.192083 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.397646 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 62747643816 80.85% 80.85% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 14840857744 19.12% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 12907000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 3989500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1311000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 947500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 1279000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 355000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 209000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 144500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 123000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 26500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 158000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 24500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 7000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 133500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 77610116560 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1910 75.26% 75.26% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 628 24.74% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2538 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21842 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21585 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2544 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21842 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2538 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2544 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24129 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2538 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24380 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4154069 # DTB read hits -system.cpu1.dtb.read_misses 18709 # DTB read misses -system.cpu1.dtb.write_hits 3480708 # DTB write hits -system.cpu1.dtb.write_misses 2876 # DTB write misses +system.cpu1.dtb.read_hits 10130559 # DTB read hits +system.cpu1.dtb.read_misses 18924 # DTB read misses +system.cpu1.dtb.write_hits 6492882 # DTB write hits +system.cpu1.dtb.write_misses 2918 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1944 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 52 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1948 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 62 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 418 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 381 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4172778 # DTB read accesses -system.cpu1.dtb.write_accesses 3483584 # DTB write accesses +system.cpu1.dtb.perms_faults 414 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10149483 # DTB read accesses +system.cpu1.dtb.write_accesses 6495800 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7634777 # DTB hits -system.cpu1.dtb.misses 21585 # DTB misses -system.cpu1.dtb.accesses 7656362 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 16623441 # DTB hits +system.cpu1.dtb.misses 21842 # DTB misses +system.cpu1.dtb.accesses 16645283 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1788,64 +1811,59 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 5903 # Table walker walks requested -system.cpu1.itb.walker.walksShort 5903 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2681 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2633 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 589 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 5314 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 359.427926 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 2179.481540 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-2047 5115 96.26% 96.26% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::2048-4095 44 0.83% 97.08% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-6143 38 0.72% 97.80% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.40% 98.19% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-10239 22 0.41% 98.61% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::10240-12287 26 0.49% 99.10% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-14335 16 0.30% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.09% 99.49% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-18431 7 0.13% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::18432-20479 3 0.06% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-22527 3 0.06% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::22528-24575 4 0.08% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-26623 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::26624-28671 4 0.08% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-30719 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 5314 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1751 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12219.588806 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11149.776616 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5813.276337 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 298 17.02% 17.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1260 71.96% 88.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 107 6.11% 95.09% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 68 3.88% 98.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 8 0.46% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 5 0.29% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 3 0.17% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 6562 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6562 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2897 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 3033 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 632 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 5930 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 575.716695 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 2785.933852 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 5654 95.35% 95.35% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 104 1.75% 97.10% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 84 1.42% 98.52% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 46 0.78% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 13 0.22% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 9 0.15% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 14 0.24% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.05% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 5930 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1787 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12039.171796 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10885.386949 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5807.969289 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 326 18.24% 18.24% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1260 70.51% 88.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 112 6.27% 95.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 73 4.09% 99.10% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.28% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 6 0.34% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1751 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 17441612916 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.860137 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.346964 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2440154764 13.99% 13.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 15000736652 86.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 721500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 17441612916 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 992 85.37% 85.37% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 170 14.63% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1162 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 1787 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 17460932916 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.922072 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.268326 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1361890264 7.80% 7.80% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 16097906652 92.19% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 1078000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 58000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 17460932916 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 986 85.37% 85.37% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 169 14.63% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1155 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5903 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5903 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6562 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6562 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1162 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1162 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7065 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 8146400 # ITB inst hits -system.cpu1.itb.inst_misses 5903 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1155 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1155 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7717 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 43481037 # ITB inst hits +system.cpu1.itb.inst_misses 6562 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1854,928 +1872,936 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1127 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1123 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 570 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 565 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8152303 # ITB inst accesses -system.cpu1.itb.hits 8146400 # DTB hits -system.cpu1.itb.misses 5903 # DTB misses -system.cpu1.itb.accesses 8152303 # DTB accesses -system.cpu1.numPwrStateTransitions 5563 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2782 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1009807188.625809 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25701428342.991928 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1977 71.06% 71.06% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.72% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.11% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 43487599 # ITB inst accesses +system.cpu1.itb.hits 43481037 # DTB hits +system.cpu1.itb.misses 6562 # DTB misses +system.cpu1.itb.accesses 43487599 # DTB accesses +system.cpu1.numPwrStateTransitions 5583 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2792 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 993380119.566619 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25601801103.735863 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1979 70.88% 70.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 809 28.98% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 959983958132 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2782 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 17370067243 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2809283598757 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 34740953 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 959983178648 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2792 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 53155264670 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773517293830 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 106311330 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8935699 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 24503906 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4617850 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2615646 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 23842655 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 779742 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 80208 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 31335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 166914 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 295220 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 22708 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8145254 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 111581 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2082 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 33764610 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.884848 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.220160 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 10498191 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108665043 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 33856624 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 27442631 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 92291638 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3748932 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 86712 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 30975 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 185919 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 298023 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23349 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 43479865 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 112855 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2560 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 105289273 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.278878 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.339497 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20042304 59.36% 59.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4827845 14.30% 73.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1634677 4.84% 78.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 7259784 21.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 48625526 46.18% 46.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 13920511 13.22% 59.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7498101 7.12% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 35245135 33.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 33764610 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.132922 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.705332 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 7349000 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16390631 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8692861 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1069281 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 262837 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 706015 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 129761 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 23185557 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1033744 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 262837 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8748161 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2379135 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11360118 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8342372 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2671987 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 22035257 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 184232 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 261771 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 36717 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15492 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1677749 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 21981180 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 102687971 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 25443797 # Number of integer rename lookups +system.cpu1.fetch.rateDist::total 105289273 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.318467 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.022140 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 13318727 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 62566078 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 26583147 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1076022 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1745299 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 4334852 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 132018 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 67655162 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1099039 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1745299 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17698509 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2385948 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 57515508 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 23258780 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2685229 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 54782270 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 214949 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 261715 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 37045 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 16294 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1684754 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 54670319 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 258827504 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 58243055 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 19631101 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2350079 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 398085 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 327427 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2832658 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 4406260 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 3798525 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 616794 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 601017 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 21230855 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 553061 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 21048993 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91520 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2000545 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 4635811 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 42283 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 33764610 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.623404 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.949604 # Number of insts issued each cycle +system.cpu1.rename.CommittedMaps 52176795 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2493524 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1869295 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1798183 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13052424 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10386014 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6834101 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 620797 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 744232 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 53921335 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 577687 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 53701083 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93984 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3580846 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 5052182 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 42977 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 105289273 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.510034 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.848273 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 21364495 63.27% 63.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6105280 18.08% 81.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4197946 12.43% 93.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1839743 5.45% 99.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 257138 0.76% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72135914 68.51% 68.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16498960 15.67% 84.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 13045494 12.39% 96.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3324500 3.16% 99.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 284390 0.27% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 15 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 33764610 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 105289273 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1397917 29.28% 29.28% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 677 0.01% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1598296 33.48% 62.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1774858 37.18% 99.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 659 0.01% 99.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 1349 0.03% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2891632 45.26% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 674 0.01% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1660257 25.99% 71.25% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1834987 28.72% 99.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 656 0.01% 99.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 1067 0.02% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 12978869 61.66% 61.66% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 28429 0.14% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3301 0.02% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 4359753 20.71% 82.52% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 3676453 17.47% 99.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 718 0.00% 99.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 1404 0.01% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36615420 68.18% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46378 0.09% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3321 0.01% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 10339913 19.25% 87.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6693876 12.47% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 720 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 1389 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 21048993 # Type of FU issued -system.cpu1.iq.rate 0.605884 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4773756 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226793 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 80721609 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 23791762 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 20591914 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6263 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2082 # Number of floating instruction queue writes +system.cpu1.iq.FU_type_0::total 53701083 # Type of FU issued +system.cpu1.iq.rate 0.505130 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6389273 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.118978 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 219168744 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58087331 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 51738316 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5952 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2080 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 1787 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 25818553 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4130 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 87577 # Number of loads that had data forwarded from stores +system.cpu1.iq.int_alu_accesses 60086458 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3832 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 90387 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 404936 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 702 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 9416 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 250549 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 431562 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 735 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 9576 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 270603 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 40531 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 75671 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 51945 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 76138 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 262837 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 524383 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 105080 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 21825012 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1745299 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 526771 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 105542 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 54540026 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 4406260 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 3798525 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 290384 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 7837 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 90528 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 9416 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 33554 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 119405 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 152959 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 20820702 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 4265911 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 206727 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 10386014 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6834101 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 292206 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7827 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 90888 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 9576 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 43509 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 122774 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 166283 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 53458422 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10243364 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 220834 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 41096 # number of nop insts executed -system.cpu1.iew.exec_refs 7893380 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3012609 # Number of branches executed -system.cpu1.iew.exec_stores 3627469 # Number of stores executed -system.cpu1.iew.exec_rate 0.599313 # Inst execution rate -system.cpu1.iew.wb_sent 20691409 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 20593701 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 10296891 # num instructions producing a value -system.cpu1.iew.wb_consumers 16154886 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.592779 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.637386 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1790740 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 510778 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 142432 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 33360276 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.594007 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.352197 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 41004 # number of nop insts executed +system.cpu1.iew.exec_refs 16887479 # number of memory reference insts executed +system.cpu1.iew.exec_branches 11797622 # Number of branches executed +system.cpu1.iew.exec_stores 6644115 # Number of stores executed +system.cpu1.iew.exec_rate 0.502848 # Inst execution rate +system.cpu1.iew.wb_sent 53318700 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 51740103 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25143993 # num instructions producing a value +system.cpu1.iew.wb_consumers 38375917 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.486685 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.655202 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 3338971 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 534710 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 155407 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103400366 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.492755 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.151487 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 23884731 71.60% 71.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 5569703 16.70% 88.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1678289 5.03% 93.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 665043 1.99% 95.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 510124 1.53% 96.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 336609 1.01% 97.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 218533 0.66% 98.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 117875 0.35% 98.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 379369 1.14% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 77772385 75.21% 75.21% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 14344116 13.87% 89.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6076791 5.88% 94.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 698306 0.68% 95.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1980317 1.92% 97.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1651720 1.60% 99.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 355943 0.34% 99.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 123415 0.12% 99.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 397373 0.38% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 33360276 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 16156383 # Number of instructions committed -system.cpu1.commit.committedOps 19816226 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103400366 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41357318 # Number of instructions committed +system.cpu1.commit.committedOps 50951031 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 7549300 # Number of memory references committed -system.cpu1.commit.loads 4001324 # Number of loads committed -system.cpu1.commit.membars 208499 # Number of memory barriers committed -system.cpu1.commit.branches 2862007 # Number of branches committed +system.cpu1.commit.refs 16517950 # Number of memory references committed +system.cpu1.commit.loads 9954452 # Number of loads committed +system.cpu1.commit.membars 209769 # Number of memory barriers committed +system.cpu1.commit.branches 11645067 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 17632180 # Number of committed integer instructions. -system.cpu1.commit.function_calls 461985 # Number of function calls committed. +system.cpu1.commit.int_insts 45808028 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3371132 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 12236255 61.75% 61.75% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 27370 0.14% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3301 0.02% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 4000808 20.19% 82.09% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 3546708 17.90% 99.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemRead 516 0.00% 99.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemWrite 1268 0.01% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 34384478 67.49% 67.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 45282 0.09% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3321 0.01% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9953936 19.54% 87.12% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6562230 12.88% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 19816226 # Class of committed instruction -system.cpu1.commit.bw_lim_events 379369 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 53607539 # The number of ROB reads -system.cpu1.rob.rob_writes 43609460 # The number of ROB writes -system.cpu1.timesIdled 58654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 976343 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5617999605 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 16123527 # Number of Instructions Simulated -system.cpu1.committedOps 19783370 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.154675 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.154675 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.464107 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.464107 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 23404305 # number of integer regfile reads -system.cpu1.int_regfile_writes 13364979 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1400 # number of floating regfile reads +system.cpu1.commit.op_class_0::total 50951031 # Class of committed instruction +system.cpu1.commit.bw_lim_events 397373 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 137214928 # The number of ROB reads +system.cpu1.rob.rob_writes 110460111 # The number of ROB writes +system.cpu1.timesIdled 59286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1022057 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5546467999 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41324462 # Number of Instructions Simulated +system.cpu1.committedOps 50918175 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.572600 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.572600 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.388712 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.388712 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 56077052 # number of integer regfile reads +system.cpu1.int_regfile_writes 35632532 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1385 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 74742517 # number of cc regfile reads -system.cpu1.cc_regfile_writes 6682824 # number of cc regfile writes -system.cpu1.misc_regfile_reads 68400417 # number of misc regfile reads -system.cpu1.misc_regfile_writes 381677 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 186538 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.297864 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6754124 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 186882 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.141116 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 89307598000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.297864 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920504 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920504 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.671875 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14996504 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14996504 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3592307 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3592307 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2912324 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2912324 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49253 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49253 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78431 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78431 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70573 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70573 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6504631 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6504631 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6553884 # number of overall hits -system.cpu1.dcache.overall_hits::total 6553884 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 213962 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 213962 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 393973 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 393973 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30075 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30075 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18449 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18449 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23608 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23608 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 607935 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 607935 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 638010 # number of overall misses -system.cpu1.dcache.overall_misses::total 638010 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3561244000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3561244000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10027675956 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10027675956 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 364257500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 364257500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554259000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 554259000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 434000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 434000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13588919956 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13588919956 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13588919956 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13588919956 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3806269 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3806269 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3306297 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3306297 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79328 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79328 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96880 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96880 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94181 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94181 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7112566 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7112566 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7191894 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7191894 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056213 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.056213 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.119158 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.119158 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379122 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379122 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190431 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190431 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250666 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250666 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085473 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.085473 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088712 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.088712 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16644.282630 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16644.282630 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25452.698423 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25452.698423 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19744.024066 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19744.024066 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23477.592342 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23477.592342 # average StoreCondReq miss latency +system.cpu1.cc_regfile_reads 190521590 # number of cc regfile reads +system.cpu1.cc_regfile_writes 15513949 # number of cc regfile writes +system.cpu1.misc_regfile_reads 212156067 # number of misc regfile reads +system.cpu1.misc_regfile_writes 383841 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 187625 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.246001 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 15706444 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187980 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 83.553804 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 89314291000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.246001 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920402 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920402 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.693359 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 32901851 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 32901851 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 9540637 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9540637 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5911714 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5911714 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49749 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49749 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78973 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78973 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71099 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71099 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15452351 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15452351 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15502100 # number of overall hits +system.cpu1.dcache.overall_hits::total 15502100 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 214896 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 214896 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 395681 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 395681 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30189 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30189 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18483 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18483 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23644 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23644 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 610577 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 610577 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 640766 # number of overall misses +system.cpu1.dcache.overall_misses::total 640766 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3583570500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3583570500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10071608465 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 10071608465 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363005500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 363005500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554928000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 554928000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 408500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 408500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13655178965 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13655178965 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13655178965 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13655178965 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9755533 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9755533 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6307395 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6307395 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79938 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79938 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97456 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97456 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94743 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94743 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16062928 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16062928 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16142866 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16142866 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022028 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.022028 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062733 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.062733 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377655 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377655 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.189655 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.189655 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249559 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249559 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038012 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038012 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039693 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039693 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16675.836218 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16675.836218 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25453.859207 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25453.859207 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19639.966456 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19639.966456 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23470.140416 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23470.140416 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22352.586964 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22352.586964 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21298.913741 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21298.913741 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 300 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1464130 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 31 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 39463 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.677419 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 37.101335 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 186538 # number of writebacks -system.cpu1.dcache.writebacks::total 186538 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 78472 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 78472 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 304164 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 304164 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13133 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13133 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 382636 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 382636 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 382636 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 382636 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 135490 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 135490 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89809 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 89809 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28779 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28779 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5316 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5316 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23608 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23608 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254078 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254078 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2880 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2880 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2230 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5110 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5110 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1973019500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1973019500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2438757966 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2438757966 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 489881500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 489881500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95317000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95317000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 530661000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 530661000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 424000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 424000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4411777466 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4411777466 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4901658966 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4901658966 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 386538000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 386538000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 386538000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 386538000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027163 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027163 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.362785 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.362785 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054872 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054872 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250666 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250666 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031676 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031676 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035328 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035328 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14562.104214 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14562.104214 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27154.939549 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27154.939549 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17022.186316 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17022.186316 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17930.210685 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17930.210685 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22478.015927 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22478.015927 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22364.384779 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22364.384779 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21310.710876 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21310.710876 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 381 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1471779 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39630 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.137931 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37.138002 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 187625 # number of writebacks +system.cpu1.dcache.writebacks::total 187625 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 78547 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 78547 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 305511 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 305511 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13157 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13157 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 384058 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 384058 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 384058 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 384058 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136349 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 136349 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90170 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 90170 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28879 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28879 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5326 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5326 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23644 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23644 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 226519 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 226519 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 255398 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 255398 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14314 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14314 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11648 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11648 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25962 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 25962 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988454500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1988454500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2445262471 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2445262471 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 492196500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 492196500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93636000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93636000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 531294000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 531294000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 398500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 398500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4433716971 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4433716971 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4925913471 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4925913471 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2472670000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2472670000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2472670000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2472670000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013977 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013977 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014296 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014296 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361267 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361267 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054650 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054650 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249559 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249559 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014102 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014102 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015821 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015821 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14583.564969 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14583.564969 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27118.359443 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27118.359443 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17043.405243 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17043.405243 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17580.923770 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17580.923770 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22470.563356 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22470.563356 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19581.877709 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19581.877709 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19291.945647 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19291.945647 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134214.583333 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 134214.583333 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 75643.444227 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 75643.444227 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 594968 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.436901 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7527273 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 595480 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 12.640681 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79132209500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.436901 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975463 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975463 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19573.267457 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19573.267457 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19287.204563 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19287.204563 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172744.865167 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172744.865167 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95241.891996 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95241.891996 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 599092 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.435973 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 42856272 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 599604 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 71.474293 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79139515500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.435973 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975461 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975461 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 16885432 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 16885432 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 7527273 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7527273 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7527273 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7527273 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7527273 # number of overall hits -system.cpu1.icache.overall_hits::total 7527273 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 617701 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 617701 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 617701 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 617701 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 617701 # number of overall misses -system.cpu1.icache.overall_misses::total 617701 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5784933521 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5784933521 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5784933521 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5784933521 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5784933521 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5784933521 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8144974 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8144974 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8144974 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8144974 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8144974 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8144974 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.075838 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.075838 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.075838 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.075838 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.075838 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.075838 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9365.264944 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9365.264944 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9365.264944 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9365.264944 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9365.264944 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9365.264944 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 523604 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 40 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 42411 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 87558770 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 87558770 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 42856272 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 42856272 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 42856272 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 42856272 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 42856272 # number of overall hits +system.cpu1.icache.overall_hits::total 42856272 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 623309 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 623309 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 623309 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 623309 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 623309 # number of overall misses +system.cpu1.icache.overall_misses::total 623309 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5905173986 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5905173986 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5905173986 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5905173986 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5905173986 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5905173986 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43479581 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43479581 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43479581 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43479581 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43479581 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43479581 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014336 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014336 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014336 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014336 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014336 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014336 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9473.910991 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9473.910991 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9473.910991 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9473.910991 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9473.910991 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9473.910991 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 533657 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 290 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42078 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.345948 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 40 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 594968 # number of writebacks -system.cpu1.icache.writebacks::total 594968 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22217 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 22217 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 22217 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 22217 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 22217 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 22217 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 595484 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 595484 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 595484 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 595484 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 595484 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 595484 # number of overall MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.682566 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 290 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 599092 # number of writebacks +system.cpu1.icache.writebacks::total 599092 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 23701 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 23701 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 23701 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 23701 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 23701 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 23701 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 599608 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 599608 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 599608 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 599608 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 599608 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 599608 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5318077800 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5318077800 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5318077800 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5318077800 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5318077800 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5318077800 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9663500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9663500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9663500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9663500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.073111 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.073111 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.073111 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8930.681261 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8930.681261 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8930.681261 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95678.217822 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95678.217822 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95678.217822 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95678.217822 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 194116 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 194726 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 546 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5403181271 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5403181271 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5403181271 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5403181271 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5403181271 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5403181271 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9499999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9499999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9499999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9499999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013791 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013791 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013791 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9011.189429 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9011.189429 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9011.189429 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94059.396040 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94059.396040 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 194821 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 195463 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 575 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59858 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 43575 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14594.735842 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 700816 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 57699 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 12.146068 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 59841 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 44456 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14684.761874 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 706823 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 58616 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 12.058534 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14193.075757 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.827460 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.968470 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 387.864155 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.866277 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000661 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023673 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.890792 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 356 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13738 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 202 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1791 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8656 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3349 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020264 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.842041 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 27731086 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 27731086 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # 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number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4397213785 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8742000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2358114500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2366856500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8742000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2358114500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2366856500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032405 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000009 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2784,118 +2810,118 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548609 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548609 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040220 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.421234 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.421234 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454940 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152511 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454940 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.547993 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.547993 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040833 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420784 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420784 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454370 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152482 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454370 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181923 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15057.285181 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43919.582187 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43919.582187 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15385.115411 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15385.115411 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14965.836404 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14965.836404 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 347499 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 347499 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36135.952203 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36135.952203 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33473.444676 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17022.085444 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17022.085444 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23121.460954 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24983.745301 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23121.460954 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43919.582187 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28045.136268 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88178.217822 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126201.562500 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124913.284133 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88178.217822 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 71127.299413 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 71457.781616 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1670520 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 844468 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12481 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 115035 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106284 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8751 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 31435 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 834833 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2230 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2230 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 146689 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 667575 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 29225 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 30255 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 73183 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41990 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85875 # Transaction distribution +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181893 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15118.372380 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43390.843564 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43390.843564 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15389.860788 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15389.860788 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14958.338620 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14958.338620 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 322999 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 322999 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36147.804558 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.804558 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34961.546316 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17061.421709 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17061.421709 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23138.926873 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25305.926764 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23138.926873 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43390.843564 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28230.155974 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164741.826184 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164193.999306 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90829.462291 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90812.895676 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1681326 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 850022 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12491 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 115149 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106381 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8768 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 43982 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 852476 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11648 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11648 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 147635 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 672194 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 29901 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30357 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 73327 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42065 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86118 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 68405 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 65523 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 595484 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 273707 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 370 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1786136 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839744 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14453 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38068 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2678401 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 76190416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29457424 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26024 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70244 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 105744108 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 346325 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4857548 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1179057 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.123952 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.351329 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadExReq 68535 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 65700 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 599608 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 274791 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 374 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1798508 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 885295 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16392 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38202 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2738397 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 76718288 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29683872 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29716 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70392 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 106502268 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 347702 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4882288 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1207717 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.121214 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.347910 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1041662 88.35% 88.35% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 128644 10.91% 99.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8751 0.74% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1070093 88.60% 88.60% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 128856 10.67% 99.27% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8768 0.73% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1179057 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1629779992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1207717 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1656031495 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80742792 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80775328 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 893427297 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 899618286 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 378082159 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 396030671 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 7957978 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8974477 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 20520473 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20614978 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31012 # Transaction distribution system.iobus.trans_dist::ReadResp 31012 # Transaction distribution system.iobus.trans_dist::WriteReq 59420 # Transaction distribution @@ -2946,19 +2972,19 @@ system.iobus.pkt_size_system.bridge.master::total 162792 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40388000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 40387001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 114000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 330000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 573500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2970,42 +2996,42 @@ system.iobus.reqLayer15.occupancy 12000 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 53000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6114001 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6115000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33826000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33791000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187862511 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187784301 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84716000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.554422 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.554359 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 255374847000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.554422 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909651 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909651 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 255387586000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.554359 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909647 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909647 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -3014,14 +3040,14 @@ system.iocache.demand_misses::realview.ide 36476 # system.iocache.demand_misses::total 36476 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36476 # number of overall misses system.iocache.overall_misses::total 36476 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 39163375 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 39163375 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4357678136 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4357678136 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4396841511 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4396841511 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4396841511 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4396841511 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 40605876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 40605876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4346476425 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4346476425 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4387082301 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4387082301 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4387082301 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4387082301 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -3038,19 +3064,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 155410.218254 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 155410.218254 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120298.093419 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120298.093419 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120540.670879 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120540.670879 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120540.670879 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120540.670879 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 87 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 161134.428571 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 161134.428571 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119988.858906 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119988.858906 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120273.119339 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120273.119339 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120273.119339 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120273.119339 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 191 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 21.750000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 63.666667 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks @@ -3062,14 +3088,14 @@ system.iocache.demand_mshr_misses::realview.ide 36476 system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 26563375 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 26563375 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2544616232 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2544616232 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2571179607 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2571179607 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2571179607 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2571179607 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 28005876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 28005876 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2533401277 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2533401277 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2561407153 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2561407153 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2561407153 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2561407153 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3078,621 +3104,622 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 105410.218254 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 105410.218254 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70246.693684 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70246.693684 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70489.626247 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70489.626247 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70489.626247 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70489.626247 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 137305 # number of replacements -system.l2c.tags.tagsinuse 65135.020938 # Cycle average of tags in use -system.l2c.tags.total_refs 548309 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 202660 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.705561 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 87489923000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6043.335191 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.875782 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.068168 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8238.246856 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6901.068519 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37215.588563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.685294 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909748 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1676.975803 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3036.574639 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2001.692374 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.092214 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000258 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111134.428571 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 111134.428571 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69937.093557 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69937.093557 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70221.711619 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70221.711619 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70221.711619 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70221.711619 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 137443 # number of replacements +system.l2c.tags.tagsinuse 65137.298659 # Cycle average of tags in use +system.l2c.tags.total_refs 547823 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 202801 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.701284 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 87493786000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6068.008119 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.951872 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.052619 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7988.261154 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6937.855049 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37116.430492 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 3.708460 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909745 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1897.444635 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3115.453147 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1993.223368 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.092590 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000228 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.125706 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.105302 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.567865 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.121891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.105863 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.566352 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000057 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025589 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.046334 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030543 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993882 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 33214 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32119 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.028953 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.047538 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993916 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33259 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32074 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6015 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 27014 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5974 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 27100 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4859 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27124 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.506805 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.490097 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6291007 # Number of tag accesses -system.l2c.tags.data_accesses 6291007 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 261222 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 261222 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 41572 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4769 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 46341 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2758 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2241 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4999 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3976 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1584 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5560 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 265 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 106 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 50549 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 57222 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46457 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 49 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 18 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 21200 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11593 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4929 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 192388 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 265 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 106 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 50549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 61198 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 46457 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 18 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 21200 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13177 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 4929 # number of demand (read+write) hits -system.l2c.demand_hits::total 197948 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 265 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 106 # number of overall hits -system.l2c.overall_hits::cpu0.inst 50549 # number of overall hits -system.l2c.overall_hits::cpu0.data 61198 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46457 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 18 # number of overall hits -system.l2c.overall_hits::cpu1.inst 21200 # number of overall hits -system.l2c.overall_hits::cpu1.data 13177 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 4929 # number of overall hits -system.l2c.overall_hits::total 197948 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 525 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 273 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 798 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 53 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 86 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 139 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11064 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8230 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19294 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 26 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 4 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 19971 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9413 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131312 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses +system.l2c.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4863 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 27079 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.507492 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000381 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.489410 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6288814 # Number of tag accesses +system.l2c.tags.data_accesses 6288814 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2826672558500 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86993.971364 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 113019.527764 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182747.188203 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70168.316832 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108315.954119 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167895.601937 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197314.914711 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146772.133324 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167867.713241 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96381.150107 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70168.316832 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 61019.189348 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92575.762633 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 504615 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 283930 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101896.024695 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80914.364960 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92556.947790 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 505078 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 284284 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 621 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 37994 # Transaction distribution -system.membus.trans_dist::ReadResp 209423 # Transaction distribution -system.membus.trans_dist::WriteReq 30912 # Transaction distribution -system.membus.trans_dist::WriteResp 30912 # Transaction distribution -system.membus.trans_dist::WritebackDirty 137105 # Transaction distribution -system.membus.trans_dist::CleanEvict 16916 # Transaction distribution -system.membus.trans_dist::UpgradeReq 65086 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38844 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 37997 # Transaction distribution +system.membus.trans_dist::ReadResp 209330 # Transaction distribution +system.membus.trans_dist::WriteReq 30917 # Transaction distribution +system.membus.trans_dist::WriteResp 30917 # Transaction distribution +system.membus.trans_dist::WritebackDirty 137351 # Transaction distribution +system.membus.trans_dist::CleanEvict 16880 # Transaction distribution +system.membus.trans_dist::UpgradeReq 65170 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38916 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 38910 # Transaction distribution -system.membus.trans_dist::ReadExResp 19275 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 171430 # Transaction distribution +system.membus.trans_dist::ReadExReq 39129 # Transaction distribution +system.membus.trans_dist::ReadExResp 19493 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171334 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 4600 # Transaction distribution +system.membus.trans_dist::InvalidateResp 4604 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 637823 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 759513 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13758 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638434 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 760140 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 832462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833089 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18694600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18885164 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27516 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18718152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18908748 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21203308 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 127782 # Total snoops (count) +system.membus.pkt_size::total 21226892 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 127972 # Total snoops (count) system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 419404 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012453 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.110898 # Request fanout histogram +system.membus.snoop_fanout::samples 419691 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012454 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.110902 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 414181 98.75% 98.75% # Request fanout histogram -system.membus.snoop_fanout::1 5223 1.25% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 414464 98.75% 98.75% # Request fanout histogram +system.membus.snoop_fanout::1 5227 1.25% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 419404 # Request fanout histogram -system.membus.reqLayer0.occupancy 81639999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 419691 # Request fanout histogram +system.membus.reqLayer0.occupancy 81605499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11433500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11449000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 984876925 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 986014542 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1099184232 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1099737525 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 7225285 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 7231369 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3724,82 +3751,82 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1044885 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 541195 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 200373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 29262 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 27938 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1324 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 37997 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 522881 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30912 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30912 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 362121 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 129726 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 111408 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43843 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 155251 # Transaction distribution +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1045202 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 540825 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 201129 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 29372 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 28126 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1246 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38000 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 522906 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30917 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30917 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 362294 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 129646 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 111513 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43869 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 155382 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50410 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50410 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 484889 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4647 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 3467 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1304964 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 322117 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1627081 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36107224 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5745684 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41852908 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 395541 # Total snoops (count) -system.toL2Bus.snoopTraffic 15858252 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 901455 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.406700 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.494199 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 50631 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50631 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 484911 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4651 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 3495 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1260717 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 366727 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1627444 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35956648 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5894436 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41851084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 396095 # Total snoops (count) +system.toL2Bus.snoopTraffic 15886732 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 901981 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.407509 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.494174 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 536157 59.48% 59.48% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 363974 40.38% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1324 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 535662 59.39% 59.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 365073 40.47% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1246 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 901455 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 896599840 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 901981 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 896811514 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2176474 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2185239 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 692364962 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 675176627 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 244002323 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 261628851 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1835 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2782 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2792 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 5548f90e7..d37cf635d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.829116 # Number of seconds simulated -sim_ticks 2829116273500 # Number of ticks simulated -final_tick 2829116273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.829112 # Number of seconds simulated +sim_ticks 2829111899000 # Number of ticks simulated +final_tick 2829111899000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175307 # Simulator instruction rate (inst/s) -host_op_rate 212638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4382427767 # Simulator tick rate (ticks/s) -host_mem_usage 587848 # Number of bytes of host memory used -host_seconds 645.56 # Real time elapsed on the host -sim_insts 113171321 # Number of instructions simulated -sim_ops 137270537 # Number of ops (including micro ops) simulated +host_inst_rate 175088 # Simulator instruction rate (inst/s) +host_op_rate 212371 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4377954653 # Simulator tick rate (ticks/s) +host_mem_usage 587752 # Number of bytes of host memory used +host_seconds 646.22 # Real time elapsed on the host +sim_insts 113144906 # Number of instructions simulated +sim_ops 137237936 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1316000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9472808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1316192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9473064 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10791176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1316000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1316000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8091200 # Number of bytes written to this memory +system.physmem.bytes_read::total 10791560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1316192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1316192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8091072 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8108724 # Number of bytes written to this memory +system.physmem.bytes_written::total 8108596 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22814 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 148533 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22817 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 148537 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171384 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126425 # Number of write requests responded to by this memory +system.physmem.num_reads::total 171390 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126423 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 130806 # Number of write requests responded to by this memory +system.physmem.num_writes::total 130804 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 465163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3348328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 465232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3348423 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3814327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 465163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 465163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2859974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3814469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 465232 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 465232 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2859934 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2866169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2859974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2866128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2859934 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 465163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3354522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 465232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3354617 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6680496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 171385 # Number of read requests accepted -system.physmem.writeReqs 130806 # Number of write requests accepted -system.physmem.readBursts 171385 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 130806 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10959936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue -system.physmem.bytesWritten 8121280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10791240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8108724 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6680597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 171391 # Number of read requests accepted +system.physmem.writeReqs 130804 # Number of write requests accepted +system.physmem.readBursts 171391 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 130804 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10959616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 8121152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10791624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8108596 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10685 # Per bank write bursts -system.physmem.perBankRdBursts::1 10044 # Per bank write bursts -system.physmem.perBankRdBursts::2 10839 # Per bank write bursts -system.physmem.perBankRdBursts::3 10919 # Per bank write bursts -system.physmem.perBankRdBursts::4 13721 # Per bank write bursts -system.physmem.perBankRdBursts::5 10679 # Per bank write bursts -system.physmem.perBankRdBursts::6 11440 # Per bank write bursts -system.physmem.perBankRdBursts::7 11401 # Per bank write bursts -system.physmem.perBankRdBursts::8 10106 # Per bank write bursts -system.physmem.perBankRdBursts::9 10397 # Per bank write bursts -system.physmem.perBankRdBursts::10 10359 # Per bank write bursts -system.physmem.perBankRdBursts::11 9487 # Per bank write bursts -system.physmem.perBankRdBursts::12 10224 # Per bank write bursts +system.physmem.perBankRdBursts::0 10684 # Per bank write bursts +system.physmem.perBankRdBursts::1 10046 # Per bank write bursts +system.physmem.perBankRdBursts::2 10837 # Per bank write bursts +system.physmem.perBankRdBursts::3 10895 # Per bank write bursts +system.physmem.perBankRdBursts::4 13724 # Per bank write bursts +system.physmem.perBankRdBursts::5 10674 # Per bank write bursts +system.physmem.perBankRdBursts::6 11441 # Per bank write bursts +system.physmem.perBankRdBursts::7 11403 # Per bank write bursts +system.physmem.perBankRdBursts::8 10108 # Per bank write bursts +system.physmem.perBankRdBursts::9 10400 # Per bank write bursts +system.physmem.perBankRdBursts::10 10362 # Per bank write bursts +system.physmem.perBankRdBursts::11 9483 # Per bank write bursts +system.physmem.perBankRdBursts::12 10233 # Per bank write bursts system.physmem.perBankRdBursts::13 11051 # Per bank write bursts -system.physmem.perBankRdBursts::14 10016 # Per bank write bursts -system.physmem.perBankRdBursts::15 9881 # Per bank write bursts -system.physmem.perBankWrBursts::0 8064 # Per bank write bursts -system.physmem.perBankWrBursts::1 7693 # Per bank write bursts -system.physmem.perBankWrBursts::2 8368 # Per bank write bursts -system.physmem.perBankWrBursts::3 8158 # Per bank write bursts -system.physmem.perBankWrBursts::4 8126 # Per bank write bursts -system.physmem.perBankWrBursts::5 8035 # Per bank write bursts -system.physmem.perBankWrBursts::6 8543 # Per bank write bursts -system.physmem.perBankWrBursts::7 8476 # Per bank write bursts -system.physmem.perBankWrBursts::8 7685 # Per bank write bursts +system.physmem.perBankRdBursts::14 10017 # Per bank write bursts +system.physmem.perBankRdBursts::15 9886 # Per bank write bursts +system.physmem.perBankWrBursts::0 8065 # Per bank write bursts +system.physmem.perBankWrBursts::1 7694 # Per bank write bursts +system.physmem.perBankWrBursts::2 8363 # Per bank write bursts +system.physmem.perBankWrBursts::3 8151 # Per bank write bursts +system.physmem.perBankWrBursts::4 8125 # Per bank write bursts +system.physmem.perBankWrBursts::5 8034 # Per bank write bursts +system.physmem.perBankWrBursts::6 8547 # Per bank write bursts +system.physmem.perBankWrBursts::7 8477 # Per bank write bursts +system.physmem.perBankWrBursts::8 7686 # Per bank write bursts system.physmem.perBankWrBursts::9 7978 # Per bank write bursts -system.physmem.perBankWrBursts::10 7774 # Per bank write bursts -system.physmem.perBankWrBursts::11 7091 # Per bank write bursts -system.physmem.perBankWrBursts::12 7777 # Per bank write bursts +system.physmem.perBankWrBursts::10 7776 # Per bank write bursts +system.physmem.perBankWrBursts::11 7088 # Per bank write bursts +system.physmem.perBankWrBursts::12 7779 # Per bank write bursts system.physmem.perBankWrBursts::13 8428 # Per bank write bursts -system.physmem.perBankWrBursts::14 7463 # Per bank write bursts -system.physmem.perBankWrBursts::15 7236 # Per bank write bursts +system.physmem.perBankWrBursts::14 7464 # Per bank write bursts +system.physmem.perBankWrBursts::15 7238 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 64 # Number of times write queue was full causing retry -system.physmem.totGap 2829116038500 # Total gap between requests +system.physmem.numWrRetry 67 # Number of times write queue was full causing retry +system.physmem.totGap 2829111664000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 3002 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 167827 # Read request sizes (log2) +system.physmem.readPktSize::6 167833 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126425 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 860 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126423 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 14975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -160,126 +160,125 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 176 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61274 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.408036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.010622 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.226456 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22407 36.57% 36.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14885 24.29% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6282 10.25% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3692 6.03% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2681 4.38% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1694 2.76% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1136 1.85% 86.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 990 1.62% 87.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7507 12.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61274 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6334 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.026050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 535.405637 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6332 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 180 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.370235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.627944 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.836836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22555 36.81% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14711 24.01% 60.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6399 10.44% 71.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3617 5.90% 77.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2643 4.31% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1730 2.82% 84.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1046 1.71% 86.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1020 1.66% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7559 12.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61280 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6329 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.046295 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 535.582122 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6327 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6334 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.033944 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.251538 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.603630 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5594 88.32% 88.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 89 1.41% 89.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 43 0.68% 90.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 45 0.71% 91.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 260 4.10% 95.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.33% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.35% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.19% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.16% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.17% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 137 2.16% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 98.85% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6329 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6329 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.049455 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.259917 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.703816 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5592 88.36% 88.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 89 1.41% 89.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 39 0.62% 90.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 43 0.68% 91.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 270 4.27% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 18 0.28% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 20 0.32% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.19% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.17% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.09% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.03% 96.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 144 2.28% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 98.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 7 0.11% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 5 0.08% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 10 0.16% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 6 0.09% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.21% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.06% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 8 0.13% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.24% 99.62% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 4 0.06% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 5 0.08% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6334 # Writes before turning the bus around for reads -system.physmem.totQLat 4767396000 # Total ticks spent queuing -system.physmem.totMemAccLat 7978314750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 856245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27838.81 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6329 # Writes before turning the bus around for reads +system.physmem.totQLat 4759784250 # Total ticks spent queuing +system.physmem.totMemAccLat 7970609250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 856220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27795.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46588.70 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 46545.06 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.87 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s @@ -289,52 +288,52 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.69 # Average write queue length when enqueuing -system.physmem.readRowHits 141756 # Number of row buffer hits during reads -system.physmem.writeRowHits 95114 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.94 # Row buffer hit rate for writes -system.physmem.avgGap 9362012.89 # Average gap between requests +system.physmem.avgWrQLen 22.41 # Average write queue length when enqueuing +system.physmem.readRowHits 141725 # Number of row buffer hits during reads +system.physmem.writeRowHits 95132 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.96 # Row buffer hit rate for writes +system.physmem.avgGap 9361874.50 # Average gap between requests system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 228894120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 121660110 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 640657920 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 341716860 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5259474480.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4230417450 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 318207360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10873180350 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 7365080640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 667265125080 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 696646226220 # Total energy per rank (pJ) -system.physmem_0.averagePower 246.241638 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2818840383250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 582284750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2236202000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2775981781500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 19179858500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7291367000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 23844779750 # Time in different power states -system.physmem_1.actEnergy 208602240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 110874720 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 582059940 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 320675040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5116263360.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4098436230 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 317114880 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10121131470 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 7324658880 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 667774632810 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 695976520350 # Total energy per rank (pJ) -system.physmem_1.averagePower 246.004919 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2819298070500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 592691750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2175820000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2778027972250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 19074668750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7049691250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22195429500 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.physmem_0.actEnergy 229315380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 121884015 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 640486560 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 341680320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5265620880.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4324767840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 323323200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10830363660 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 7337789280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 667252731645 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 696670151130 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.250476 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2818571248250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 597049500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2238844000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2775921295250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 19108902750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7495096250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23750711250 # Time in different power states +system.physmem_1.actEnergy 208223820 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 110673585 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 582195600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 320701140 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5120565840.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4126082940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 330709920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10081531860 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 7328179680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 667772142345 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 695983009200 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.007593 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2819198005500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 626918750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2177664000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2778005345250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 19083791250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7109310750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22108869000 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory @@ -347,30 +346,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 40 system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46888279 # Number of BP lookups -system.cpu.branchPred.condPredicted 24003428 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1174058 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29505954 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13539674 # Number of BTB hits +system.cpu.branchPred.lookups 46861889 # Number of BP lookups +system.cpu.branchPred.condPredicted 23994211 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1178677 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29377087 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13527695 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 45.887938 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11754876 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 34853 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7941192 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7796111 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 145081 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 60202 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 46.048456 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11745847 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 34771 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7932573 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7787517 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 145056 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 60304 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -400,91 +399,91 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 71258 # Table walker walks requested -system.cpu.dtb.walker.walksShort 71258 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29064 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23380 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 18814 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52444 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 391.093357 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2302.538664 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50603 96.49% 96.49% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 703 1.34% 97.83% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 574 1.09% 98.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 328 0.63% 99.55% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 67 0.13% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 32 0.06% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 70988 # Table walker walks requested +system.cpu.dtb.walker.walksShort 70988 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 28945 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23300 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 18743 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52245 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 398.564456 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2327.323415 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50380 96.43% 96.43% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 694 1.33% 97.76% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 600 1.15% 98.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 333 0.64% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 70 0.13% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 116 0.22% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 29 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.96% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::32768-36863 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::45056-49151 8 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 9 0.02% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52444 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 16825 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9444.665676 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7665.862074 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 6497.692830 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-8191 8271 49.16% 49.16% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::8192-16383 6932 41.20% 90.36% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-24575 1364 8.11% 98.47% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::24576-32767 166 0.99% 99.45% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-40959 23 0.14% 99.59% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::40960-49151 60 0.36% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::total 52245 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 16835 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9419.156519 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7648.743457 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6474.178852 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-8191 8274 49.15% 49.15% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::8192-16383 6961 41.35% 90.50% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-24575 1349 8.01% 98.51% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::24576-32767 164 0.97% 99.48% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-40959 19 0.11% 99.60% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::40960-49151 59 0.35% 99.95% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.96% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.96% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::90112-98303 2 0.01% 99.98% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::98304-106495 3 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::114688-122879 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 16825 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 118990825724 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.630270 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.488920 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 118944532224 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 32222000 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 6760000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 4376000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 965500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 468000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1159500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 331000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 11500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 118990825724 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6321 82.36% 82.36% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1354 17.64% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7675 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71258 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 16835 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 118986443724 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.628139 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.489522 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 118939907724 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 32370000 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 6888500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 4293000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 974500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 505000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1161500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 334500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 118986443724 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6321 82.34% 82.34% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1356 17.66% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7677 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 70988 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71258 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7675 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 70988 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7677 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7675 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 78933 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7677 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 78665 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25423698 # DTB read hits -system.cpu.dtb.read_misses 61603 # DTB read misses -system.cpu.dtb.write_hits 19869004 # DTB write hits +system.cpu.dtb.read_hits 25415823 # DTB read hits +system.cpu.dtb.read_misses 61333 # DTB read misses +system.cpu.dtb.write_hits 19865547 # DTB write hits system.cpu.dtb.write_misses 9655 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4259 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 365 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2214 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4258 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 385 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2212 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1308 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25485301 # DTB read accesses -system.cpu.dtb.write_accesses 19878659 # DTB write accesses +system.cpu.dtb.perms_faults 1098 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25477156 # DTB read accesses +system.cpu.dtb.write_accesses 19875202 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45292702 # DTB hits -system.cpu.dtb.misses 71258 # DTB misses -system.cpu.dtb.accesses 45363960 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 45281370 # DTB hits +system.cpu.dtb.misses 70988 # DTB misses +system.cpu.dtb.accesses 45352358 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -514,51 +513,57 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 12656 # Table walker walks requested -system.cpu.itb.walker.walksShort 12656 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3345 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7740 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 1571 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11085 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 575.732972 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2511.318158 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 10605 95.67% 95.67% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 108 0.97% 96.64% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 223 2.01% 98.66% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 110 0.99% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-20479 16 0.14% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::20480-24575 18 0.16% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 12746 # Table walker walks requested +system.cpu.itb.walker.walksShort 12746 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3372 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7811 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 1563 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11183 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 675.266029 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2802.587445 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 10603 94.81% 94.81% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 140 1.25% 96.07% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 267 2.39% 98.45% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 112 1.00% 99.45% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-20479 22 0.20% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::20480-24575 26 0.23% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-28671 5 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::40960-45055 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11085 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 4896 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 9060.763889 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7035.829304 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 11150.467524 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 4894 99.96% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::total 11183 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 4880 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 9080.327869 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7055.685836 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 11146.166993 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 4878 99.96% 99.96% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 4896 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 24500602212 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.693564 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.461068 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 7508480500 30.65% 30.65% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 16991502712 69.35% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 619000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 24500602212 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2990 89.92% 89.92% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 335 10.08% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3325 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 4880 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 24496220212 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.683787 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.465095 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 7747033500 31.63% 31.63% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 16748218212 68.37% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 952500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 3500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::5 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::6 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 24496220212 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2980 89.84% 89.84% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 337 10.16% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3317 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12656 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 12656 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12746 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 12746 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3325 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3325 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15981 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 65983065 # ITB inst hits -system.cpu.itb.inst_misses 12656 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3317 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3317 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 16063 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66035618 # ITB inst hits +system.cpu.itb.inst_misses 12746 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -567,21 +572,21 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3022 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3018 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2179 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2274 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 65995721 # ITB inst accesses -system.cpu.itb.hits 65983065 # DTB hits -system.cpu.itb.misses 12656 # DTB misses -system.cpu.itb.accesses 65995721 # DTB accesses +system.cpu.itb.inst_accesses 66048364 # ITB inst accesses +system.cpu.itb.hits 66035618 # DTB hits +system.cpu.itb.misses 12746 # DTB misses +system.cpu.itb.accesses 66048364 # DTB accesses system.cpu.numPwrStateTransitions 6078 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3039 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 886806915.729845 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17417893662.159683 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 886809089.600197 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17417893131.253975 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 2967 97.63% 97.63% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state @@ -589,91 +594,91 @@ system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499972056544 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499972215488 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3039 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 134110056597 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2695006216903 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 268220171 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 134099075705 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2695012823295 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 268198207 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 105042564 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 183946336 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46888279 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33090661 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 151947545 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6066122 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 177459 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8717 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 332750 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 861386 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 140 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65981974 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 958405 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5944 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 261403622 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.858325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.227883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 105002772 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184114970 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46861889 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33061059 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 151938402 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6072000 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 175966 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 334285 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 875612 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 143 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66034467 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1042471 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6106 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 261371159 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.859042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228291 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 162493227 62.16% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29157587 11.15% 73.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14046843 5.37% 78.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55705965 21.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 162416335 62.14% 62.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29147387 11.15% 73.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14040939 5.37% 78.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55766498 21.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 261403622 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.174813 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.685804 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78158537 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 112446013 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64386093 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3839619 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2573360 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3404101 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 467760 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157070559 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3511367 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2573360 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83910500 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11255138 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 76381178 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62476128 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24807318 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146500137 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 914744 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 477372 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 65897 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 19059 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22053744 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150295383 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 677299800 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164022340 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11055 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141831816 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8463561 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2844179 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2649010 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13862871 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26349559 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21216979 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1695969 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2055276 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143294681 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2116741 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143114526 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 260917 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8140881 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14283010 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121741 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 261403622 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.547485 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.874392 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 261371159 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.174729 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.686488 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78127678 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 112458141 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64373777 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3837716 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2573847 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 10211840 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 470330 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157024104 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3522922 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2573847 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83881832 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11236308 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 76411931 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62459889 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24807352 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146462333 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 915339 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 473585 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 65974 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 19134 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22055359 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150259400 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 677124866 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 163984739 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 11050 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141797655 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8461739 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2842470 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2647297 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13853647 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26344198 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21214401 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1696128 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2146370 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143256850 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2116673 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143077391 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 262359 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8135583 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14293372 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 121607 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 261371159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.547411 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.874705 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 173098069 66.22% 66.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45413284 17.37% 83.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31798683 12.16% 95.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10270501 3.93% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 823052 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 173167745 66.25% 66.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45242575 17.31% 83.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31871715 12.19% 95.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10265143 3.93% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 823948 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -681,9 +686,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 261403622 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 261371159 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7334511 32.77% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7332033 32.77% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available @@ -714,135 +719,135 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5619720 25.11% 57.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9419018 42.08% 99.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 2403 0.01% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 8747 0.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5621223 25.12% 57.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9411536 42.06% 99.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 2405 0.01% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 8745 0.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95906474 67.01% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114332 0.08% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8541 0.01% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95878441 67.01% 67.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114347 0.08% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8549 0.01% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26136950 18.26% 85.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20933494 14.63% 99.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26131013 18.26% 85.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20930310 14.63% 99.99% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 2708 0.00% 99.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 9690 0.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 9686 0.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143114526 # Type of FU issued -system.cpu.iq.rate 0.533571 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22384431 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156409 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 570242068 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 153557534 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140061190 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35954 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13312 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11500 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165473068 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23552 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 325058 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143077391 # Type of FU issued +system.cpu.iq.rate 0.533476 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22375974 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 570128328 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153514376 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140022897 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35946 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13304 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11498 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165427480 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23548 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 325201 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1430930 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 739 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18590 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 619959 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1431545 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 741 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18622 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 620213 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88583 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6407 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88247 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6406 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2573360 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1161160 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 410961 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145591536 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2573847 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1145032 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 405376 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145553638 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26349559 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21216979 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1093729 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17740 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 375076 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18590 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 276726 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471114 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 747840 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142217911 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25746602 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 825466 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26344198 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21214401 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1093740 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17692 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 369492 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18622 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 275358 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 475095 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 750453 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142177506 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25738555 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 828985 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 180114 # number of nop insts executed -system.cpu.iew.exec_refs 46577390 # number of memory reference insts executed -system.cpu.iew.exec_branches 26518344 # Number of branches executed -system.cpu.iew.exec_stores 20830788 # Number of stores executed -system.cpu.iew.exec_rate 0.530228 # Inst execution rate -system.cpu.iew.wb_sent 141848584 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140072690 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63277897 # num instructions producing a value -system.cpu.iew.wb_consumers 95827474 # num instructions consuming a value -system.cpu.iew.wb_rate 0.522230 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660331 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 7357031 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995000 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 714357 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258509266 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.531607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.132560 # Number of insts commited each cycle +system.cpu.iew.exec_nop 180115 # number of nop insts executed +system.cpu.iew.exec_refs 46565887 # number of memory reference insts executed +system.cpu.iew.exec_branches 26507471 # Number of branches executed +system.cpu.iew.exec_stores 20827332 # Number of stores executed +system.cpu.iew.exec_rate 0.530121 # Inst execution rate +system.cpu.iew.wb_sent 141808684 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140034395 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63259988 # num instructions producing a value +system.cpu.iew.wb_consumers 95801132 # num instructions consuming a value +system.cpu.iew.wb_rate 0.522130 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660326 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 7349911 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995066 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 716524 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258476519 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.531549 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.133767 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 184931767 71.54% 71.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43412717 16.79% 88.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15465745 5.98% 94.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4363425 1.69% 96.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6516677 2.52% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1538620 0.60% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 797794 0.31% 99.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 415780 0.16% 99.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1066741 0.41% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 185006238 71.58% 71.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43313968 16.76% 88.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15459084 5.98% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4363700 1.69% 96.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6431569 2.49% 98.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1619656 0.63% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 798464 0.31% 99.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 416455 0.16% 99.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1067385 0.41% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258509266 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113326226 # Number of instructions committed -system.cpu.commit.committedOps 137425442 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 258476519 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113299811 # Number of instructions committed +system.cpu.commit.committedOps 137392841 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45515649 # Number of memory references committed -system.cpu.commit.loads 24918629 # Number of loads committed -system.cpu.commit.membars 814537 # Number of memory barriers committed -system.cpu.commit.branches 26054301 # Number of branches committed +system.cpu.commit.refs 45506841 # Number of memory references committed +system.cpu.commit.loads 24912653 # Number of loads committed +system.cpu.commit.membars 814563 # Number of memory barriers committed +system.cpu.commit.branches 26044441 # Number of branches committed system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120244809 # Number of committed integer instructions. -system.cpu.commit.function_calls 4895095 # Number of function calls committed. +system.cpu.commit.int_insts 120215331 # Number of committed integer instructions. +system.cpu.commit.function_calls 4891729 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91788341 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112911 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91764545 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112906 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -868,43 +873,43 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8541 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8549 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24915921 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20588240 14.98% 99.99% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24909945 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20585408 14.98% 99.99% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 8780 0.01% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137425442 # Class of committed instruction -system.cpu.commit.bw_lim_events 1066741 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 379966373 # The number of ROB reads -system.cpu.rob.rob_writes 292446245 # The number of ROB writes -system.cpu.timesIdled 894795 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6816549 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5390012377 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113171321 # Number of Instructions Simulated -system.cpu.committedOps 137270537 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.370037 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.370037 # CPI: Total CPI of All Threads -system.cpu.ipc 0.421934 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.421934 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155596425 # number of integer regfile reads -system.cpu.int_regfile_writes 88542209 # number of integer regfile writes -system.cpu.fp_regfile_reads 9690 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137392841 # Class of committed instruction +system.cpu.commit.bw_lim_events 1067385 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 379915503 # The number of ROB reads +system.cpu.rob.rob_writes 292367166 # The number of ROB writes +system.cpu.timesIdled 894415 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6827048 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5390025592 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113144906 # Number of Instructions Simulated +system.cpu.committedOps 137237936 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.370396 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.370396 # CPI: Total CPI of All Threads +system.cpu.ipc 0.421870 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.421870 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155555257 # number of integer regfile reads +system.cpu.int_regfile_writes 88513526 # number of integer regfile writes +system.cpu.fp_regfile_reads 9686 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502428467 # number of cc regfile reads -system.cpu.cc_regfile_writes 53152553 # number of cc regfile writes -system.cpu.misc_regfile_reads 455632805 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521018 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 835071 # number of replacements +system.cpu.cc_regfile_reads 502284717 # number of cc regfile reads +system.cpu.cc_regfile_writes 53144427 # number of cc regfile writes +system.cpu.misc_regfile_reads 455456531 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521074 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 834899 # number of replacements system.cpu.dcache.tags.tagsinuse 511.950856 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40080644 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 835583 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.967280 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 40072104 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 835411 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.966934 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 291735500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.950856 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999904 # Average percentage of cache occupancy @@ -914,463 +919,463 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179195359 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179195359 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23277723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23277723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15551809 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15551809 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346190 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346190 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441882 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441882 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460162 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460162 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38829532 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38829532 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39175722 # number of overall hits -system.cpu.dcache.overall_hits::total 39175722 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 703752 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 703752 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3604950 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3604950 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 176883 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 176883 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26584 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26584 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179153223 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179153223 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23270451 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23270451 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15550335 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15550335 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346358 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346358 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441909 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460176 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460176 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38820786 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38820786 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39167144 # number of overall hits +system.cpu.dcache.overall_hits::total 39167144 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 703305 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 703305 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3603558 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3603558 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 176816 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 176816 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26536 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26536 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4308702 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4308702 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4485585 # number of overall misses -system.cpu.dcache.overall_misses::total 4485585 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11028419500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11028419500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 167321691201 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 167321691201 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 369201500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 369201500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4306863 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4306863 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4483679 # number of overall misses +system.cpu.dcache.overall_misses::total 4483679 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11004555500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11004555500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 167287466703 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 167287466703 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 367903000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 367903000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 196000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 196000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 178350110701 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 178350110701 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 178350110701 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 178350110701 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23981475 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23981475 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19156759 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19156759 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523073 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523073 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468466 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468466 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460166 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460166 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43138234 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43138234 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43661307 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43661307 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029346 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029346 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188182 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.188182 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338161 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338161 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056747 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056747 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 178292022203 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 178292022203 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 178292022203 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 178292022203 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23973756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23973756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19153893 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19153893 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523174 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523174 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468445 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468445 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460180 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460180 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43127649 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43127649 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43650823 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43650823 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029336 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029336 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188137 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.188137 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.337968 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.337968 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056647 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056647 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099881 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099881 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102736 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102736 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15670.889035 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15670.889035 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46414.427718 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46414.427718 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13888.109389 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13888.109389 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.099863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.099863 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102717 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102717 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15646.917767 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15646.917767 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46422.859491 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46422.859491 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13864.297558 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13864.297558 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 49000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 49000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41393.002046 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41393.002046 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39760.724789 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39760.724789 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 631534 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41397.189138 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41397.189138 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39764.671423 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39764.671423 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 631960 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7012 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7043 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 90.064746 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 89.728809 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 411800 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 411800 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299234 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299234 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119070 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119070 # number of SoftPFReq MSHR misses +system.cpu.dcache.writebacks::writebacks 693774 # number of writebacks +system.cpu.dcache.writebacks::total 693774 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291761 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 291761 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3304379 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3304379 # 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number of SoftPFReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8297 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 8297 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 711034 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 711034 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 830104 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 830104 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 710723 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 710723 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 829927 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 829927 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6169785000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6169785000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14920252482 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14920252482 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1648301500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1648301500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 125755000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 125755000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6158767500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6158767500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14913404483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14913404483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1645609500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1645609500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 125434500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 125434500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 192000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 192000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21090037482 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21090037482 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22738338982 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22738338982 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281915000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281915000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281915000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281915000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017172 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017172 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21072171983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21072171983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22717781483 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22717781483 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6282018000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6282018000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6282018000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6282018000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017166 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227636 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227636 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017711 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017711 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227848 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227848 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017712 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017712 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016483 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016483 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019012 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14982.479359 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14982.479359 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49861.487939 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49861.487939 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13843.130092 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13843.130092 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15156.683138 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15156.683138 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016480 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016480 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019013 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019013 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14965.028041 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14965.028041 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49847.764994 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49847.764994 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13804.985571 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13804.985571 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15118.054719 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15118.054719 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 48000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 48000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29661.081583 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29661.081583 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27392.156865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27392.156865 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201815.626305 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201815.626305 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106997.240722 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106997.240722 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1888135 # number of replacements -system.cpu.icache.tags.tagsinuse 511.315248 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 63998090 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1888647 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.885681 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 14109342500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.315248 # Average occupied blocks per requestor +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29648.923678 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29648.923678 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27373.228589 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27373.228589 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201818.935329 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201818.935329 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106998.995078 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106998.995078 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1887711 # number of replacements +system.cpu.icache.tags.tagsinuse 511.315276 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64050692 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1888223 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.921148 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 14108989500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.315276 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998663 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998663 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 67867650 # Number of tag accesses -system.cpu.icache.tags.data_accesses 67867650 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 63998090 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 63998090 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 63998090 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 63998090 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 63998090 # number of overall hits -system.cpu.icache.overall_hits::total 63998090 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1980875 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1980875 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1980875 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1980875 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1980875 # number of overall misses -system.cpu.icache.overall_misses::total 1980875 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27580080995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27580080995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27580080995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27580080995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27580080995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27580080995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65978965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65978965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65978965 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65978965 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65978965 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65978965 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.030023 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.030023 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.030023 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.030023 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.030023 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.030023 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13923.180915 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13923.180915 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13923.180915 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13923.180915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13923.180915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13923.180915 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2871 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 67919712 # Number of tag accesses +system.cpu.icache.tags.data_accesses 67919712 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 64050692 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64050692 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64050692 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64050692 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64050692 # number of overall hits +system.cpu.icache.overall_hits::total 64050692 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1980765 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1980765 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1980765 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1980765 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1980765 # number of overall misses +system.cpu.icache.overall_misses::total 1980765 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27590430995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27590430995 # 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miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029997 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029997 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029997 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029997 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029997 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13929.179380 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13929.179380 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13929.179380 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13929.179380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13929.179380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13929.179380 # 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number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209196500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892817000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6102013500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000352 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001787 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001787 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892920500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6102117000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000287 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000595 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000337 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001790 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001790 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455546 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455546 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010492 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024625 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024625 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177564 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060362 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177564 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060362 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 273181.818182 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18700 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455618 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455618 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010496 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010496 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024642 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024642 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000287 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000595 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010496 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177605 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060380 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000287 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000595 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010496 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177605 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060380 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 292300 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 344083.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 307095.238095 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18900 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18900 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84334.710101 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84334.710101 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97783.017916 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97783.017916 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 106957.322586 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 106957.322586 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97783.017916 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86358.613090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87728.833006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97783.017916 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86358.613090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87728.833006 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84289.765872 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84289.765872 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 98310.172570 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 98310.172570 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105979.555723 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105979.555723 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 292300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 344083.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 98310.172570 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86231.039851 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87681.689019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 292300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 344083.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 98310.172570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86231.039851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87681.689019 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189315.288977 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178755.961448 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189318.614065 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178758.993438 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100369.896612 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98866.064485 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5482504 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758205 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46081 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100371.659485 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98867.741413 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5481318 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757626 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46311 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 188 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 188 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 128785 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2556664 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 128675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2556003 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 784088 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1888135 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 149071 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2798 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 784007 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1887711 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 148986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2793 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888686 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 539247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888256 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 539126 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5671462 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28809 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128289 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8458023 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241760656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98078237 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 39936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 340088689 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 135331 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5917792 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2986371 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.026284 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.159980 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5670183 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2628937 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29081 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127780 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8455981 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241706320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98062173 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40348 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 208940 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 340017781 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135349 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5917412 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2985660 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026373 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.160242 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2907876 97.37% 97.37% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 78495 2.63% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2906919 97.36% 97.36% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 78741 2.64% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2986371 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5399114998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2985660 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5397955498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 298125 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2836925219 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2836300178 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1299904639 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1299640147 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18830489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19000487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75878391 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75596896 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30169 # Transaction distribution system.iobus.trans_dist::ReadResp 30169 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1602,11 +1607,11 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480117 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 43091500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 100000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 325500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1636,32 +1641,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6161000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6160500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33823000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33869500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187589137 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187578393 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36712000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.001834 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.001800 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 253684759000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.001834 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062615 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062615 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 253685816000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.001800 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062613 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062613 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327996 # Number of tag accesses system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1670,14 +1675,14 @@ system.iocache.demand_misses::realview.ide 36444 # system.iocache.demand_misses::total 36444 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36444 # number of overall misses system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 35729875 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 35729875 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4377211262 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4377211262 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4412941137 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4412941137 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4412941137 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4412941137 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 35734875 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 35734875 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4362724518 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4362724518 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4398459393 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4398459393 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4398459393 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4398459393 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1694,19 +1699,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 162408.522727 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162408.522727 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120837.325033 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120837.325033 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 121088.276177 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121088.276177 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 121088.276177 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121088.276177 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 444 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 162431.250000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162431.250000 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120437.403876 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120437.403876 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120690.906404 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120690.906404 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120690.906404 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120690.906404 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 222 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks @@ -1718,14 +1723,14 @@ system.iocache.demand_mshr_misses::realview.ide 36444 system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 24729875 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 24729875 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2564234451 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2564234451 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2588964326 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2588964326 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2588964326 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2588964326 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 24734875 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 24734875 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2549742484 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2549742484 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2574477359 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2574477359 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2574477359 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2574477359 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1734,91 +1739,91 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112408.522727 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 112408.522727 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70788.274376 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70788.274376 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 71039.521622 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 71039.521622 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 71039.521622 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 71039.521622 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 339223 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 139296 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112431.250000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112431.250000 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70388.209033 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70388.209033 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70642.008534 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70642.008534 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70642.008534 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70642.008534 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 339238 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 139305 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 511 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34136 # Transaction distribution -system.membus.trans_dist::ReadResp 67466 # Transaction distribution +system.membus.trans_dist::ReadResp 67474 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 126425 # Transaction distribution -system.membus.trans_dist::CleanEvict 8073 # Transaction distribution +system.membus.trans_dist::WritebackDirty 126423 # Transaction distribution +system.membus.trans_dist::CleanEvict 8081 # Transaction distribution system.membus.trans_dist::UpgradeReq 126 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 134978 # Transaction distribution -system.membus.trans_dist::ReadExResp 134978 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33331 # Transaction distribution +system.membus.trans_dist::ReadExReq 134976 # Transaction distribution +system.membus.trans_dist::ReadExResp 134976 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33339 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 4572 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 449994 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557556 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450012 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557574 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72869 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72869 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 630425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 630443 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16582780 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16746157 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16583036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16746413 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19063277 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19063533 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 5056 # Total snoops (count) system.membus.snoopTraffic 30848 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 266381 # Request fanout histogram +system.membus.snoop_fanout::samples 266387 # Request fanout histogram system.membus.snoop_fanout::mean 0.019149 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.137050 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.137048 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261280 98.09% 98.09% # Request fanout histogram +system.membus.snoop_fanout::0 261286 98.09% 98.09% # Request fanout histogram system.membus.snoop_fanout::1 5101 1.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 266381 # Request fanout histogram -system.membus.reqLayer0.occupancy 84417000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 266387 # Request fanout histogram +system.membus.reqLayer0.occupancy 84461000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1728499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1733999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 876893413 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 877020942 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 984678000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 984714000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 5966654 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 5968652 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1850,29 +1855,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 2db3ee4aa..ec1d5e30b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.356210 # Number of seconds simulated -sim_ticks 47356210126000 # Number of ticks simulated -final_tick 47356210126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.310816 # Number of seconds simulated +sim_ticks 47310816168000 # Number of ticks simulated +final_tick 47310816168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 269105 # Simulator instruction rate (inst/s) -host_op_rate 316551 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14489745940 # Simulator tick rate (ticks/s) -host_mem_usage 771556 # Number of bytes of host memory used -host_seconds 3268.26 # Real time elapsed on the host -sim_insts 879504495 # Number of instructions simulated -sim_ops 1034569807 # Number of ops (including micro ops) simulated +host_inst_rate 279196 # Simulator instruction rate (inst/s) +host_op_rate 332505 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15871048208 # Simulator tick rate (ticks/s) +host_mem_usage 770320 # Number of bytes of host memory used +host_seconds 2980.95 # Real time elapsed on the host +sim_insts 832269934 # Number of instructions simulated +sim_ops 991180133 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 139968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 127936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7960960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14481160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15033920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 105216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 97088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3386304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9267600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 11152448 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 451392 # Number of bytes read from this memory -system.physmem.bytes_read::total 62203992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7960960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3386304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11347264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74964928 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 133120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 103552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 5351360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14671112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 17389824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 166080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 153792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3559616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12274128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 15128448 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 452672 # Number of bytes read from this memory +system.physmem.bytes_read::total 69383704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 5351360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3559616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8910976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 84006336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74985512 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2187 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 124390 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 226281 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 234905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1644 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1517 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 52911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 144819 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 174257 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7053 # Number of read requests responded to by this memory -system.physmem.num_reads::total 971963 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1171327 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 84026920 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2080 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1618 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 83615 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 229249 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 271716 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2595 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 55619 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 191796 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 236382 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7073 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1084146 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1312599 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1173901 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 168108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 305792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 317465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 71507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 195700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 235501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1313534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 168108 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 71507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 239615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1583001 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1315173 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 113111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 310101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 367566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 75239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 259436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 319767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1466551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 113111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 75239 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1775626 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1583436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1583001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 168108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 306227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 317465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 71507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 195700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 235501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2896970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 971963 # Number of read requests accepted -system.physmem.writeReqs 1173901 # Number of write requests accepted -system.physmem.readBursts 971963 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1173901 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62180096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 25536 # Total number of bytes read from write queue -system.physmem.bytesWritten 74984000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62203992 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 74985512 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 399 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1776062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1775626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 113111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 310536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 367566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 75239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 259436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 319767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3242612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1084146 # Number of read requests accepted +system.physmem.writeReqs 1315173 # Number of write requests accepted +system.physmem.readBursts 1084146 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1315173 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 69357696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 27648 # Total number of bytes read from write queue +system.physmem.bytesWritten 84025344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 69383704 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 84026920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 432 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 55033 # Per bank write bursts -system.physmem.perBankRdBursts::1 62597 # Per bank write bursts -system.physmem.perBankRdBursts::2 50092 # Per bank write bursts -system.physmem.perBankRdBursts::3 57292 # Per bank write bursts -system.physmem.perBankRdBursts::4 55886 # Per bank write bursts -system.physmem.perBankRdBursts::5 65305 # Per bank write bursts -system.physmem.perBankRdBursts::6 62171 # Per bank write bursts -system.physmem.perBankRdBursts::7 60911 # Per bank write bursts -system.physmem.perBankRdBursts::8 55564 # Per bank write bursts -system.physmem.perBankRdBursts::9 110087 # Per bank write bursts -system.physmem.perBankRdBursts::10 50665 # Per bank write bursts -system.physmem.perBankRdBursts::11 58731 # Per bank write bursts -system.physmem.perBankRdBursts::12 55379 # Per bank write bursts -system.physmem.perBankRdBursts::13 59204 # Per bank write bursts -system.physmem.perBankRdBursts::14 58833 # Per bank write bursts -system.physmem.perBankRdBursts::15 53814 # Per bank write bursts -system.physmem.perBankWrBursts::0 70729 # Per bank write bursts -system.physmem.perBankWrBursts::1 73923 # Per bank write bursts -system.physmem.perBankWrBursts::2 67641 # Per bank write bursts -system.physmem.perBankWrBursts::3 73309 # Per bank write bursts -system.physmem.perBankWrBursts::4 73460 # Per bank write bursts -system.physmem.perBankWrBursts::5 77994 # Per bank write bursts -system.physmem.perBankWrBursts::6 75119 # Per bank write bursts -system.physmem.perBankWrBursts::7 77047 # Per bank write bursts -system.physmem.perBankWrBursts::8 72172 # Per bank write bursts -system.physmem.perBankWrBursts::9 76177 # Per bank write bursts -system.physmem.perBankWrBursts::10 69310 # Per bank write bursts -system.physmem.perBankWrBursts::11 74055 # Per bank write bursts -system.physmem.perBankWrBursts::12 71196 # Per bank write bursts -system.physmem.perBankWrBursts::13 73730 # Per bank write bursts -system.physmem.perBankWrBursts::14 72781 # Per bank write bursts -system.physmem.perBankWrBursts::15 72982 # Per bank write bursts +system.physmem.perBankRdBursts::0 69238 # Per bank write bursts +system.physmem.perBankRdBursts::1 72128 # Per bank write bursts +system.physmem.perBankRdBursts::2 62859 # Per bank write bursts +system.physmem.perBankRdBursts::3 64909 # Per bank write bursts +system.physmem.perBankRdBursts::4 64833 # Per bank write bursts +system.physmem.perBankRdBursts::5 74280 # Per bank write bursts +system.physmem.perBankRdBursts::6 68552 # Per bank write bursts +system.physmem.perBankRdBursts::7 74109 # Per bank write bursts +system.physmem.perBankRdBursts::8 62269 # Per bank write bursts +system.physmem.perBankRdBursts::9 70311 # Per bank write bursts +system.physmem.perBankRdBursts::10 59842 # Per bank write bursts +system.physmem.perBankRdBursts::11 70232 # Per bank write bursts +system.physmem.perBankRdBursts::12 64744 # Per bank write bursts +system.physmem.perBankRdBursts::13 72876 # Per bank write bursts +system.physmem.perBankRdBursts::14 66012 # Per bank write bursts +system.physmem.perBankRdBursts::15 66520 # Per bank write bursts +system.physmem.perBankWrBursts::0 83559 # Per bank write bursts +system.physmem.perBankWrBursts::1 83793 # Per bank write bursts +system.physmem.perBankWrBursts::2 79464 # Per bank write bursts +system.physmem.perBankWrBursts::3 82775 # Per bank write bursts +system.physmem.perBankWrBursts::4 80648 # Per bank write bursts +system.physmem.perBankWrBursts::5 87124 # Per bank write bursts +system.physmem.perBankWrBursts::6 80406 # Per bank write bursts +system.physmem.perBankWrBursts::7 83854 # Per bank write bursts +system.physmem.perBankWrBursts::8 77300 # Per bank write bursts +system.physmem.perBankWrBursts::9 82321 # Per bank write bursts +system.physmem.perBankWrBursts::10 78447 # Per bank write bursts +system.physmem.perBankWrBursts::11 84798 # Per bank write bursts +system.physmem.perBankWrBursts::12 79286 # Per bank write bursts +system.physmem.perBankWrBursts::13 85569 # Per bank write bursts +system.physmem.perBankWrBursts::14 81705 # Per bank write bursts +system.physmem.perBankWrBursts::15 81847 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 338 # Number of times write queue was full causing retry -system.physmem.totGap 47356208030500 # Total gap between requests +system.physmem.numWrRetry 404 # Number of times write queue was full causing retry +system.physmem.totGap 47310814104000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 971933 # Read request sizes (log2) +system.physmem.readPktSize::6 1084116 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1171327 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 599542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 159109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 23819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1312599 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 617903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 194931 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 35439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 32251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 29577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 23659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 6340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1051 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -189,187 +189,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 66279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 71432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 74216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 76183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 73010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 71262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 72325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 67464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 769 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 927860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 147.827612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.770435 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 195.442358 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 609464 65.68% 65.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 190800 20.56% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 46263 4.99% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21195 2.28% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15500 1.67% 95.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9774 1.05% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7067 0.76% 97.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5586 0.60% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22211 2.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 927860 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 57099 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.014939 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 164.898277 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 57097 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 57099 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 57099 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.519186 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.696547 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.054604 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49168 86.11% 86.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2307 4.04% 90.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 623 1.09% 91.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 607 1.06% 92.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 970 1.70% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 377 0.66% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 342 0.60% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 248 0.43% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 171 0.30% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 147 0.26% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 125 0.22% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 141 0.25% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 491 0.86% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 181 0.32% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 140 0.25% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 149 0.26% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 103 0.18% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 79 0.14% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 87 0.15% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 90 0.16% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 76 0.13% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 61 0.11% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 62 0.11% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 70 0.12% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 41 0.07% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 40 0.07% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 42 0.07% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 34 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 42 0.07% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 20 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 12 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 13 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 4 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 25826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 51697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 67549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 71954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 74550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 77056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 80172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 80848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 83842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 85747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 81110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 82972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 86524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 78237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 73594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 917 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1043685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.962350 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.815605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 191.425821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 685015 65.63% 65.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 212974 20.41% 86.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53995 5.17% 91.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24749 2.37% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18577 1.78% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11845 1.13% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7907 0.76% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6706 0.64% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21917 2.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1043685 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.510147 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 26.150337 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 65626 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 65638 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65638 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.002072 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.384137 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.246607 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 57560 87.69% 87.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2491 3.80% 91.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 689 1.05% 92.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 564 0.86% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 947 1.44% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 301 0.46% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 320 0.49% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 211 0.32% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 208 0.32% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 135 0.21% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 147 0.22% 96.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 134 0.20% 97.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 619 0.94% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 144 0.22% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 133 0.20% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 128 0.20% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 93 0.14% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 63 0.10% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 64 0.10% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 96 0.15% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 75 0.11% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 71 0.11% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 89 0.14% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 57 0.09% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 53 0.08% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 43 0.07% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 44 0.07% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 41 0.06% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 43 0.07% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 17 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 9 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 14 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 4 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 57099 # Writes before turning the bus around for reads -system.physmem.totQLat 49354955217 # Total ticks spent queuing -system.physmem.totMemAccLat 67571780217 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4857820000 # Total ticks spent in databus transfers -system.physmem.avgQLat 50799.49 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 7 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 65638 # Writes before turning the bus around for reads +system.physmem.totQLat 57570179828 # Total ticks spent queuing +system.physmem.totMemAccLat 77889817328 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5418570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 53123.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 69549.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 71873.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.53 # Average write queue length when enqueuing -system.physmem.readRowHits 725116 # Number of row buffer hits during reads -system.physmem.writeRowHits 490210 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.84 # Row buffer hit rate for writes -system.physmem.avgGap 22068597.09 # Average gap between requests -system.physmem.pageHitRate 56.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3347988840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1779490680 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3350709180 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3075738840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 40224500160.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 43885079760 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2109996960 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 79595636190 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 56472597600 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11270458828185 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11504320668105 # Total energy per rank (pJ) -system.physmem_0.averagePower 242.931616 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47254429054365 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3740889550 # Time in different power states -system.physmem_0.memoryStateTime::REF 17088544000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 46932815651000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 147063936092 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80948731835 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 174552373523 # Time in different power states -system.physmem_1.actEnergy 3276952980 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1741738020 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3586257780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3040143660 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 38004420480.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 43585213590 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1995622560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 72860280210 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 53203975680 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11275978868760 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11497290812280 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.783170 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47255392508641 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3486165610 # Time in different power states -system.physmem_1.memoryStateTime::REF 16146094000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 46957059679500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 138551420004 # Time in different power states -system.physmem_1.memoryStateTime::ACT 81185307499 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 159781459387 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.92 # Average write queue length when enqueuing +system.physmem.readRowHits 798943 # Number of row buffer hits during reads +system.physmem.writeRowHits 553978 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.72 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 42.19 # Row buffer hit rate for writes +system.physmem.avgGap 19718434.32 # Average gap between requests +system.physmem.pageHitRate 56.45 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3802085700 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2020848885 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3933483120 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3453672060 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 39277339920.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 44911710750 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1916970240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 82436275650 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 52427154240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11259457849125 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11493654896520 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.939265 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47207292873414 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3245693994 # Time in different power states +system.physmem_0.memoryStateTime::REF 16679736000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 46889984158000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 136529047983 # Time in different power states +system.physmem_0.memoryStateTime::ACT 83596561092 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 180780970931 # Time in different power states +system.physmem_1.actEnergy 3649853760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1939935690 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3804234840 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3399645060 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 37874116800.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 45213068040 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1883953920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 76352255250 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 50620183680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11263627504680 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11488379615340 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.827762 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47206725446684 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3212291316 # Time in different power states +system.physmem_1.memoryStateTime::REF 16085928000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 46907462906500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 131823013391 # Time in different power states +system.physmem_1.memoryStateTime::ACT 84792497000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 167439531793 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory @@ -396,30 +396,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 135721275 # Number of BP lookups -system.cpu0.branchPred.condPredicted 95221356 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6297780 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 101561419 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 70514394 # Number of BTB hits +system.cpu0.branchPred.lookups 116746639 # Number of BP lookups +system.cpu0.branchPred.condPredicted 74661681 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6562912 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 81659728 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 48398116 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 69.430296 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16061922 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1062204 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 3676908 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2416966 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1259942 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 447333 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 59.268035 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16692830 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1123660 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 3717417 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2487467 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1229950 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 447789 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -449,64 +449,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 280305 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 280305 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9673 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80745 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 280305 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 280305 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 280305 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 90418 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 24557.682099 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 22462.475848 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 18823.909973 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 89075 98.51% 98.51% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1011 1.12% 99.63% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 175 0.19% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 66 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 41 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 5 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 21 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 90418 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1049600704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1049600704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1049600704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 80745 89.30% 89.30% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9673 10.70% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 90418 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 280305 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 291933 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 291933 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10456 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84439 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 291933 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 291933 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 291933 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 94895 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 24023.404816 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22175.510022 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15850.715577 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 93828 98.88% 98.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.82% 99.70% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 167 0.18% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 53 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 94895 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 490774000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 490774000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 490774000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 84439 88.98% 88.98% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10456 11.02% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 94895 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 291933 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 280305 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90418 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 291933 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94895 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90418 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 370723 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94895 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 386828 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 85620412 # DTB read hits -system.cpu0.dtb.read_misses 232360 # DTB read misses -system.cpu0.dtb.write_hits 76323418 # DTB write hits -system.cpu0.dtb.write_misses 47945 # DTB write misses +system.cpu0.dtb.read_hits 91107490 # DTB read hits +system.cpu0.dtb.read_misses 238663 # DTB read misses +system.cpu0.dtb.write_hits 81148084 # DTB write hits +system.cpu0.dtb.write_misses 53270 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37568 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2099 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 10030 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37379 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9352 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11718 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 85852772 # DTB read accesses -system.cpu0.dtb.write_accesses 76371363 # DTB write accesses +system.cpu0.dtb.perms_faults 11764 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91346153 # DTB read accesses +system.cpu0.dtb.write_accesses 81201354 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 161943830 # DTB hits -system.cpu0.dtb.misses 280305 # DTB misses -system.cpu0.dtb.accesses 162224135 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 172255574 # DTB hits +system.cpu0.dtb.misses 291933 # DTB misses +system.cpu0.dtb.accesses 172547507 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -536,767 +536,773 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 68220 # Table walker walks requested -system.cpu0.itb.walker.walksLong 68220 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 613 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59689 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 68220 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 68220 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 68220 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 60302 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26595.826009 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24233.258451 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 21809.844701 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 58891 97.66% 97.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1009 1.67% 99.33% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 274 0.45% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 71 0.12% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 21 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 60302 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1048830204 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1048830204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1048830204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 59689 98.98% 98.98% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 613 1.02% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 60302 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 65131 # Table walker walks requested +system.cpu0.itb.walker.walksLong 65131 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 651 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56721 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 65131 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 65131 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 65131 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 57372 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26035.845012 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23914.977730 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19217.419826 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 56364 98.24% 98.24% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 674 1.17% 99.42% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 235 0.41% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 63 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 11 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 15 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 57372 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 490003500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 490003500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 490003500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 56721 98.87% 98.87% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 651 1.13% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 57372 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 68220 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 68220 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65131 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65131 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60302 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60302 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 128522 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 240780512 # ITB inst hits -system.cpu0.itb.inst_misses 68220 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57372 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57372 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 122503 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 201165320 # ITB inst hits +system.cpu0.itb.inst_misses 65131 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26473 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26201 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 160298 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 173484 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 240848732 # ITB inst accesses -system.cpu0.itb.hits 240780512 # DTB hits -system.cpu0.itb.misses 68220 # DTB misses -system.cpu0.itb.accesses 240848732 # DTB accesses -system.cpu0.numPwrStateTransitions 27604 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13802 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3395512179.708375 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 87569621243.897629 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3847 27.87% 27.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9929 71.94% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 201230451 # ITB inst accesses +system.cpu0.itb.hits 201165320 # DTB hits +system.cpu0.itb.misses 65131 # DTB misses +system.cpu0.itb.accesses 201230451 # DTB accesses +system.cpu0.numPwrStateTransitions 27066 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13533 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3461850354.100126 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 88555833572.600677 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3597 26.58% 26.58% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9910 73.23% 99.81% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7470353787292 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13802 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 491351021665 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46864859104335 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 982743358 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7470353817972 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13533 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 461595325963 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46849220842037 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 923231946 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 443442317 # Number of instructions committed -system.cpu0.committedOps 521139520 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 46171758 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4942 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93730487058 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.216170 # CPI: cycles per instruction -system.cpu0.ipc 0.451229 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 361587453 69.38% 69.38% # Class of committed instruction -system.cpu0.op_class_0::IntMult 1073144 0.21% 69.59% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 57197 0.01% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 8 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 13 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 21 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatMultAcc 0 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatMisc 48874 0.01% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::MemRead 82336787 15.80% 85.41% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 75604792 14.51% 99.92% # Class of committed instruction -system.cpu0.op_class_0::FloatMemRead 54276 0.01% 99.93% # Class of committed instruction -system.cpu0.op_class_0::FloatMemWrite 376955 0.07% 100.00% # Class of committed instruction +system.cpu0.committedInsts 433947137 # Number of instructions committed +system.cpu0.committedOps 516803462 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 22098859 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4673 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93699151861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.127522 # CPI: cycles per instruction +system.cpu0.ipc 0.470030 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 346907240 67.13% 67.13% # Class of committed instruction +system.cpu0.op_class_0::IntMult 1217129 0.24% 67.36% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 58486 0.01% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 8 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 13 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 21 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatMultAcc 0 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatMisc 70436 0.01% 67.39% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::MemRead 87685666 16.97% 84.35% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 80429583 15.56% 99.92% # Class of committed instruction +system.cpu0.op_class_0::FloatMemRead 59649 0.01% 99.93% # Class of committed instruction +system.cpu0.op_class_0::FloatMemWrite 375230 0.07% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 521139520 # Class of committed instruction +system.cpu0.op_class_0::total 516803462 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13802 # number of quiesce instructions executed -system.cpu0.tickCycles 716804238 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 265939120 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5714630 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.374360 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 153605175 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5715141 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.876883 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5354308000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.374360 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983153 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.983153 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 326958988 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 326958988 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 78624149 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78624149 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 70655306 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 70655306 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268473 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 268473 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 172491 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 172491 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1691736 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1691736 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1666426 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1666426 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149451946 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149451946 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 149720419 # number of overall hits -system.cpu0.dcache.overall_hits::total 149720419 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3212821 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3212821 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2434459 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2434459 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 667240 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 667240 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831306 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 831306 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 163515 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 163515 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187633 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 187633 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6478586 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6478586 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 7145826 # number of overall misses -system.cpu0.dcache.overall_misses::total 7145826 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52300502500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 52300502500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52442906000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 52442906000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26430842500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 26430842500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2572412500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2572412500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4480220000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4480220000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2147000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2147000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 131174251000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 131174251000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 131174251000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 131174251000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 81836970 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 81836970 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73089765 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73089765 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 935713 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 935713 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1003797 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1003797 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1855251 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1855251 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1854059 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1854059 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 155930532 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 155930532 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 156866245 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 156866245 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039259 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039259 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033308 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033308 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.713082 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.713082 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.828161 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.828161 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088136 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088136 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101201 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101201 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041548 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.041548 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045554 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.045554 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16278.685461 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16278.685461 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21541.913830 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21541.913830 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31794.360320 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31794.360320 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15731.966486 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15731.966486 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23877.569511 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23877.569511 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13533 # number of quiesce instructions executed +system.cpu0.tickCycles 653190940 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 270041006 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6005277 # number of replacements +system.cpu0.dcache.tags.tagsinuse 502.540168 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 163513084 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6005789 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.225912 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 500703000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.540168 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981524 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.981524 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 347779597 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 347779597 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 83636950 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83636950 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75142855 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75142855 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 275029 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 275029 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 178111 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 178111 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878303 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1878303 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1839620 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1839620 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 158957916 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 158957916 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 159232945 # number of overall hits +system.cpu0.dcache.overall_hits::total 159232945 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3392683 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3392683 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2596834 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2596834 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 729933 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 729933 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 807715 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 807715 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164864 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 164864 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202355 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 202355 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 6797232 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6797232 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 7527165 # number of overall misses +system.cpu0.dcache.overall_misses::total 7527165 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55240233000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 55240233000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55000663500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 55000663500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26000939500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 26000939500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2528136500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2528136500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4851897500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4851897500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2304500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2304500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 136241836000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 136241836000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 136241836000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 136241836000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 87029633 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 87029633 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77739689 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77739689 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1004962 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1004962 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 985826 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 985826 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2043167 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2043167 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2041975 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2041975 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 165755148 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 165755148 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 166760110 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 166760110 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038983 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.038983 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033404 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033404 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.726329 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.726329 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.819328 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.819328 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080690 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080690 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099098 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099098 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041008 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041008 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045138 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045138 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16282.167535 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16282.167535 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21179.891938 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21179.891938 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32190.734975 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32190.734975 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15334.678887 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15334.678887 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23977.156482 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23977.156482 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20247.358143 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20247.358143 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18356.765334 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18356.765334 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20043.723092 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20043.723092 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18100.019861 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18100.019861 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5714633 # number of writebacks -system.cpu0.dcache.writebacks::total 5714633 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202792 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 202792 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1014502 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1014502 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 93 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 93 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43372 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43372 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 49 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 49 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1217387 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1217387 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1217387 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1217387 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3010029 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3010029 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1419957 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1419957 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664995 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 664995 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 831213 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 831213 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120143 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120143 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187584 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 187584 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5261199 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5261199 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5926194 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5926194 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31550 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31201 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62751 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44196910500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44196910500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29509664500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29509664500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16065417000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16065417000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25593186000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25593186000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1671520500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1671520500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4291457000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4291457000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1958500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1958500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99299761000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 99299761000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115365178000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 115365178000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6087891000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6087891000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6087891000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6087891000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036781 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036781 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019428 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019428 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.710683 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.710683 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.828069 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.828069 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064758 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064758 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101175 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101175 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033741 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033741 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037779 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.037779 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14683.217504 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14683.217504 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20782.083190 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20782.083190 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24158.703449 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24158.703449 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30790.165698 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30790.165698 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13912.758130 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13912.758130 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22877.521537 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22877.521537 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 6005280 # number of writebacks +system.cpu0.dcache.writebacks::total 6005280 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 217816 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 217816 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1084214 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1084214 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 111 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 111 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44378 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44378 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 58 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1302141 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1302141 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1302141 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1302141 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3174867 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3174867 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1512620 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1512620 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 727670 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 727670 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 807604 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 807604 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120486 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120486 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202297 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 202297 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5495091 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5495091 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6222761 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6222761 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32770 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65503 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46331358000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46331358000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30906822000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30906822000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18329110000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18329110000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25186211500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25186211500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1650103500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1650103500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4648318000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4648318000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1886000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1886000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102424391500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 102424391500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 120753501500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 120753501500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6287102500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6287102500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6287102500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6287102500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036480 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036480 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019458 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019458 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.724077 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.724077 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.819216 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.819216 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058970 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058970 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099069 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099069 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033152 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033152 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037316 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.037316 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14593.165005 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14593.165005 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20432.641377 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20432.641377 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25188.766886 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25188.766886 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31186.338230 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31186.338230 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13695.396146 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13695.396146 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22977.691216 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22977.691216 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18873.979296 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18873.979296 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19466.993149 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19466.993149 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 192960.095087 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192960.095087 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97016.637185 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97016.637185 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 9611464 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.928699 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 231001616 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9611976 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.032688 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 22883257000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.928699 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999861 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18639.253017 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18639.253017 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19405.132465 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19405.132465 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191855.431797 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191855.431797 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95981.901592 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95981.901592 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 9998472 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.981180 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 190986664 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9998984 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 19.100607 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 18008070000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.981180 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999963 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 426 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 490839190 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 490839190 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 231001616 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 231001616 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 231001616 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 231001616 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 231001616 # number of overall hits -system.cpu0.icache.overall_hits::total 231001616 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9611986 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9611986 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9611986 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9611986 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9611986 # number of overall misses -system.cpu0.icache.overall_misses::total 9611986 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 98657772000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 98657772000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 98657772000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 98657772000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 98657772000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 98657772000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 240613602 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 240613602 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 240613602 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 240613602 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 240613602 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 240613602 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039948 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.039948 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039948 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.039948 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039948 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.039948 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10264.036173 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10264.036173 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10264.036173 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10264.036173 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10264.036173 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10264.036173 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 411970312 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 411970312 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 190986664 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 190986664 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 190986664 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 190986664 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 190986664 # number of overall hits +system.cpu0.icache.overall_hits::total 190986664 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9998995 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9998995 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9998995 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9998995 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9998995 # number of overall misses +system.cpu0.icache.overall_misses::total 9998995 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104315202000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 104315202000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 104315202000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 104315202000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 104315202000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 104315202000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 200985659 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 200985659 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 200985659 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 200985659 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 200985659 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 200985659 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.049750 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.049750 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.049750 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.049750 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.049750 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.049750 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.568673 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.568673 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10432.568673 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10432.568673 # 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average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 99886.644875 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 99886.644875 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8169933 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8171403 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1304 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 974582 # 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Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.935015 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002613 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001606 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.018238 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.957472 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 263 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 99 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15410 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 82 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 89 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 92 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2136 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5462 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5455 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2257 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016052 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006042 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.940552 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 526460646 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 526460646 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522971 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 177971 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 700942 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3820006 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3820006 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 11503050 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 11503050 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 900259 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 900259 # 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number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 177971 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 8923530 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3724768 # number of overall hits -system.cpu0.l2cache.overall_hits::total 13349240 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20616 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9971 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 30587 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 242554 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 242554 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 187582 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 187582 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # 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number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1972860 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20616 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9971 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 688455 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1253818 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1972860 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 693953500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 416737500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1110691000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 877430000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 877430000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 285529500 # 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number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 774823 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1074161 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1074161 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 597920 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 597920 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 21943 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10378 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 774823 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1353277 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 2160421 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 21943 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10378 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 774823 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1353277 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 836449 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2996870 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 37053 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69786 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 328079000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 911857500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44903675775 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4788332493 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4788332493 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3126512997 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3126512997 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1538999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1538999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12740129497 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12740129497 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23972456500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23972456500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34238693990 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34238693990 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18919213000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18919213000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 328079000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23972456500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46978823487 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 71863137487 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 328079000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23972456500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46978823487 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 116766813262 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 393550500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6024557000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6418107500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 393550500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6024557000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6418107500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1305,137 +1311,138 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.232027 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.232027 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071624 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.255427 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255427 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.723907 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.723907 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.249863 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128108 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.249863 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221344 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221344 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077490 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.267022 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267022 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.740363 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.740363 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134861 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.179167 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30382.508370 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49338.751608 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18457.034285 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18457.034285 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15352.509820 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15352.509820 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 791500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 791500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45737.585095 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45737.585095 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31076.764582 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32649.424572 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32649.424572 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31797.018884 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31797.018884 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35539.317014 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33894.108396 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35539.317014 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38295.567374 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184952.345483 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126184.847437 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92990.494175 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91959.668796 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 31463839 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16044170 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3048 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 652134 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 652077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 57 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 887708 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14387458 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31201 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31200 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5457517 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 11506087 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1359708 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 999352 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 454749 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343952 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 493156 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1220335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1191280 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9611986 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4900402 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 909564 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 832554 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28940003 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18484921 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 391848 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1143553 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 48960325 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1233646912 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 690994144 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1503536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4348696 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1930493288 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5822948 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 111810824 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 22356517 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.042093 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.200815 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187076 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28212.539835 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53683.698319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18574.475032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18574.475032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15455.369177 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15455.369177 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 384749.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 384749.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45644.568914 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45644.568914 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30939.268065 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31874.825087 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31874.825087 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31641.712938 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31641.712938 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33263.487759 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38962.922403 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183843.667989 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173214.247159 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91973.756927 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91968.410569 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 32883708 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16795845 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 670544 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 670518 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 26 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 856926 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14963454 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32733 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32733 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5790144 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 12027561 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1570458 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1077933 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 422877 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361846 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 518769 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1292875 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1268569 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9998995 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5030713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 860724 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 808588 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30005026 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19391293 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370102 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1186574 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 50952995 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1280111872 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 728610541 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404176 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4490264 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 2014616853 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6115163 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 122669856 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 23320085 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.043025 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.202918 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 21415512 95.79% 95.79% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 940948 4.21% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 57 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 22316772 95.70% 95.70% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 1003287 4.30% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 26 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 22356517 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 31390166976 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 23320085 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 32742058478 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 183129639 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 168693686 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14498904485 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 15007733348 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8149348322 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8612588664 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 204016279 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 194673313 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 600088255 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 625412257 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 132997996 # Number of BP lookups -system.cpu1.branchPred.condPredicted 94215152 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6033479 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 99520242 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 69476937 # Number of BTB hits +system.cpu1.branchPred.lookups 106657949 # Number of BP lookups +system.cpu1.branchPred.condPredicted 68318136 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5862525 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 74400025 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 44246966 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 69.811865 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15575496 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1022946 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3462102 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2360825 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1101277 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 401735 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 59.471709 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15290670 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 972922 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3525874 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2416919 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1108955 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 399586 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1465,63 +1472,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 271949 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 271949 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9428 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76874 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 271949 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 271949 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 271949 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 86302 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23685.366504 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21920.409810 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15487.631024 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 85344 98.89% 98.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 718 0.83% 99.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 138 0.16% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 39 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 32 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 86302 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 114608944 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 114608944 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 114608944 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 76874 89.08% 89.08% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9428 10.92% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 86302 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 271949 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 277975 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 277975 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11649 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87046 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 277975 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 277975 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 277975 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 98695 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24377.552054 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22321.248739 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 18122.441336 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 97210 98.50% 98.50% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1115 1.13% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 185 0.19% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 61 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 98695 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -466757760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -466757760 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -466757760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 87046 88.20% 88.20% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11649 11.80% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 98695 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 277975 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 271949 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86302 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 277975 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98695 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86302 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 358251 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98695 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 376670 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 86154833 # DTB read hits -system.cpu1.dtb.read_misses 225974 # DTB read misses -system.cpu1.dtb.write_hits 74805729 # DTB write hits -system.cpu1.dtb.write_misses 45975 # DTB write misses +system.cpu1.dtb.read_hits 85144665 # DTB read hits +system.cpu1.dtb.read_misses 232605 # DTB read misses +system.cpu1.dtb.write_hits 73861979 # DTB write hits +system.cpu1.dtb.write_misses 45370 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36571 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1221 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7188 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 39387 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7458 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10263 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 86380807 # DTB read accesses -system.cpu1.dtb.write_accesses 74851704 # DTB write accesses +system.cpu1.dtb.perms_faults 10689 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 85377270 # DTB read accesses +system.cpu1.dtb.write_accesses 73907349 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 160960562 # DTB hits -system.cpu1.dtb.misses 271949 # DTB misses -system.cpu1.dtb.accesses 161232511 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 159006644 # DTB hits +system.cpu1.dtb.misses 277975 # DTB misses +system.cpu1.dtb.accesses 159284619 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1551,908 +1558,889 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 60899 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60899 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 513 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50941 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60899 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60899 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60899 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 51454 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25618.018036 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23516.416553 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19409.340181 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 50489 98.12% 98.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 670 1.30% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 212 0.41% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 46 0.09% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 13 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 51454 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 113972444 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 113972444 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 113972444 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 50941 99.00% 99.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 513 1.00% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 51454 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 63204 # Table walker walks requested +system.cpu1.itb.walker.walksLong 63204 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 495 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53495 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 63204 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 63204 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 63204 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 53990 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26610.918689 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23983.875694 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 21231.525332 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 52488 97.22% 97.22% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1070 1.98% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 308 0.57% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.14% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 53990 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -467394260 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -467394260 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -467394260 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 53495 99.08% 99.08% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 495 0.92% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 53990 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60899 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60899 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63204 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63204 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51454 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51454 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 112353 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 236231380 # ITB inst hits -system.cpu1.itb.inst_misses 60899 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53990 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53990 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 117194 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 184175570 # ITB inst hits +system.cpu1.itb.inst_misses 63204 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26538 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 27907 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 178013 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 163451 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 236292279 # ITB inst accesses -system.cpu1.itb.hits 236231380 # DTB hits -system.cpu1.itb.misses 60899 # DTB misses -system.cpu1.itb.accesses 236292279 # DTB accesses -system.cpu1.numPwrStateTransitions 9440 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 4720 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9937322156.794067 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 214697400239.899719 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3380 71.61% 71.61% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1320 27.97% 99.58% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.11% 99.68% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.75% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 10 0.21% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 184238774 # ITB inst accesses +system.cpu1.itb.hits 184175570 # DTB hits +system.cpu1.itb.misses 63204 # DTB misses +system.cpu1.itb.accesses 184238774 # DTB accesses +system.cpu1.numPwrStateTransitions 10058 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 5029 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9328191006.192484 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 208028914614.416260 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3721 73.99% 73.99% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1288 25.61% 99.60% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.10% 99.70% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.76% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 10 0.20% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813594348000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 4720 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 452049545932 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46904160580068 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 904105497 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 11813597602000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 5029 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 399343597858 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46911472570142 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 798693745 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 436062178 # Number of instructions committed -system.cpu1.committedOps 513430287 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 45590191 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4720 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93808990671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.073341 # CPI: cycles per instruction -system.cpu1.ipc 0.482313 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 354600208 69.06% 69.06% # Class of committed instruction -system.cpu1.op_class_0::IntMult 1143323 0.22% 69.29% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 59569 0.01% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatMisc 63096 0.01% 69.31% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::MemRead 82989666 16.16% 85.48% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 74191847 14.45% 99.93% # Class of committed instruction -system.cpu1.op_class_0::FloatMemRead 64253 0.01% 99.94% # Class of committed instruction -system.cpu1.op_class_0::FloatMemWrite 318324 0.06% 100.00% # Class of committed instruction +system.cpu1.committedInsts 398322797 # Number of instructions committed +system.cpu1.committedOps 474376671 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 19914789 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5029 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93823705865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.005142 # CPI: cycles per instruction +system.cpu1.ipc 0.498718 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 317550239 66.94% 66.94% # Class of committed instruction +system.cpu1.op_class_0::IntMult 1035693 0.22% 67.16% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 58506 0.01% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatMultAcc 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatMisc 40875 0.01% 67.18% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::MemRead 82080782 17.30% 84.48% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 73258893 15.44% 99.93% # Class of committed instruction +system.cpu1.op_class_0::FloatMemRead 48388 0.01% 99.94% # Class of committed instruction +system.cpu1.op_class_0::FloatMemWrite 303295 0.06% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 513430287 # Class of committed instruction +system.cpu1.op_class_0::total 474376671 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4720 # number of quiesce instructions executed -system.cpu1.tickCycles 704305988 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 199799509 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5048947 # number of replacements -system.cpu1.dcache.tags.tagsinuse 416.228585 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 153590869 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5049459 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.417292 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8378525599500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.228585 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.812946 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.812946 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5029 # number of quiesce instructions executed +system.cpu1.tickCycles 594788003 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 203905742 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5132038 # number of replacements +system.cpu1.dcache.tags.tagsinuse 426.485512 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 151527650 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5132550 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.522878 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8373589022500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.485512 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832980 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.832980 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 324622701 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 324622701 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 79356977 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79356977 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 69837106 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 69837106 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 233112 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 233112 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 147127 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 147127 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1782955 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1782955 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1749534 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1749534 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 149341210 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 149341210 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 149574322 # number of overall hits -system.cpu1.dcache.overall_hits::total 149574322 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3104936 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3104936 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2154320 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2154320 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 600203 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 600203 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 416637 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 416637 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162547 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 162547 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194652 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 194652 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5675893 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5675893 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6276096 # number of overall misses -system.cpu1.dcache.overall_misses::total 6276096 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 47629871000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 47629871000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40774475000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 40774475000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9727566000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 9727566000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2415502000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2415502000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4643846000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4643846000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2158500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2158500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 98131912000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 98131912000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 98131912000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 98131912000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82461913 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82461913 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 71991426 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 71991426 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 833315 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 833315 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 563764 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 563764 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1945502 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1945502 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1944186 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1944186 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 155017103 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 155017103 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 155850418 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 155850418 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037653 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037653 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029925 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029925 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.720259 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.720259 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.739027 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.739027 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083550 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083550 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100120 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100120 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036615 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.036615 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040270 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040270 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15340.049199 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15340.049199 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18926.842345 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18926.842345 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23347.820765 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23347.820765 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14860.329628 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14860.329628 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23857.170746 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23857.170746 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 320787282 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 320787282 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 78335043 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78335043 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68878259 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68878259 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235022 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 235022 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 144067 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 144067 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1753147 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1753147 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1717747 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1717747 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 147357369 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 147357369 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 147592391 # number of overall hits +system.cpu1.dcache.overall_hits::total 147592391 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3132424 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3132424 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2174513 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2174513 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 607658 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 607658 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 439275 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 439275 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165234 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 165234 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199402 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 199402 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5746212 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5746212 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6353870 # number of overall misses +system.cpu1.dcache.overall_misses::total 6353870 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50822417500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 50822417500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41404734500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 41404734500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10557419500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10557419500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2612130500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2612130500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4773809500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4773809500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2292000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2292000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 102784571500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 102784571500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 102784571500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 102784571500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 81467467 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 81467467 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 71052772 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 71052772 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 842680 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 842680 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 583342 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 583342 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1918381 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1918381 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1917149 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1917149 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 153103581 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 153103581 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 153946261 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 153946261 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038450 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038450 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030604 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030604 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.721102 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.721102 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.753032 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.753032 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086132 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086132 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104010 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104010 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037532 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.037532 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041273 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.041273 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16224.629073 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16224.629073 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19040.922956 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19040.922956 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24033.736270 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24033.736270 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15808.674365 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15808.674365 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23940.629984 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23940.629984 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17289.246291 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17289.246291 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15635.820740 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15635.820740 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17887.361535 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17887.361535 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16176.687830 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16176.687830 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5048949 # number of writebacks -system.cpu1.dcache.writebacks::total 5048949 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 157294 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 157294 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 878635 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 878635 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 59 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 59 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39126 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39126 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 65 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1035988 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1035988 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1035988 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1035988 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2947642 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2947642 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1275685 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1275685 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 599894 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 599894 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 416578 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 416578 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123421 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 123421 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194587 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 194587 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4639905 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4639905 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5239799 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5239799 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6968 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6968 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7187 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14155 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14155 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41244047000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41244047000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23526690000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23526690000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13870615000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13870615000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9306680500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9306680500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1636714500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1636714500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4447799000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4447799000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1876000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1876000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74077417500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 74077417500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87948032500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 87948032500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 882714500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 882714500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 882714500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 882714500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035745 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035745 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017720 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.719889 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.719889 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738923 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738923 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063439 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063439 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100087 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100087 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033621 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033621 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13992.217169 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13992.217169 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18442.397614 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18442.397614 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23121.776514 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23121.776514 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22340.787320 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22340.787320 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13261.231881 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13261.231881 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22857.636944 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22857.636944 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5132050 # number of writebacks +system.cpu1.dcache.writebacks::total 5132050 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 160382 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 160382 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 885255 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 885255 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 52 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 52 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41570 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41570 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1045689 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1045689 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1045689 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1045689 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2972042 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2972042 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1289258 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1289258 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607473 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 607473 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 439223 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 439223 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123664 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 123664 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199344 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 199344 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4700523 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4700523 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5307996 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5307996 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5330 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10596 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43920578500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43920578500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24016685500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24016685500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14415408000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14415408000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10114952000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10114952000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1723729000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1723729000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4572940000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4572940000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2004000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2004000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78052216000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 78052216000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 92467624000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 92467624000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 634565500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 634565500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 634565500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 634565500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036481 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018145 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018145 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.720882 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.720882 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.752943 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.752943 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064463 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064463 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103979 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103979 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030702 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030702 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034480 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034480 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14777.913132 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14777.913132 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18628.300542 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18628.300542 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23730.121339 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23730.121339 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23029.194737 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23029.194737 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13938.810001 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13938.810001 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22939.943013 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22939.943013 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15965.287544 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15965.287544 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16784.619505 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16784.619505 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126681.185419 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 126681.185419 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62360.614624 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62360.614624 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 9106015 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.214941 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 226941610 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9106527 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 24.920764 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8368863514500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.214941 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990654 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990654 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16605.006719 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16605.006719 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17420.439654 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17420.439654 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119055.440901 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 119055.440901 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59887.268781 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59887.268781 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 8722673 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.263120 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 175283400 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8723185 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 20.093968 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8363988306000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.263120 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990748 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990748 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 481202803 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 481202803 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 226941610 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 226941610 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 226941610 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 226941610 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 226941610 # number of overall hits -system.cpu1.icache.overall_hits::total 226941610 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9106528 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9106528 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9106528 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9106528 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9106528 # number of overall misses -system.cpu1.icache.overall_misses::total 9106528 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93334039500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 93334039500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 93334039500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 93334039500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 93334039500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 93334039500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 236048138 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 236048138 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 236048138 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 236048138 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 236048138 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 236048138 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038579 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.038579 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038579 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.038579 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038579 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.038579 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10249.135510 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10249.135510 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10249.135510 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10249.135510 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10249.135510 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10249.135510 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 376736355 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 376736355 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 175283400 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 175283400 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 175283400 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 175283400 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 175283400 # number of overall hits +system.cpu1.icache.overall_hits::total 175283400 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8723185 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8723185 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8723185 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8723185 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 8723185 # number of overall misses +system.cpu1.icache.overall_misses::total 8723185 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 89772651500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 89772651500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 89772651500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 89772651500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 89772651500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 89772651500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 184006585 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 184006585 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 184006585 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 184006585 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 184006585 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 184006585 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.047407 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.047407 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.047407 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.047407 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.047407 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.047407 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10291.269932 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10291.269932 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10291.269932 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10291.269932 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 9106015 # number of writebacks -system.cpu1.icache.writebacks::total 9106015 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9106528 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9106528 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9106528 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9106528 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 9106528 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 9106528 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 8722673 # number of writebacks +system.cpu1.icache.writebacks::total 8722673 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8723185 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8723185 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8723185 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8723185 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8723185 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8723185 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 88780776000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 88780776000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 88780776000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 88780776000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 88780776000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 88780776000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9602500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9602500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9602500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9602500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038579 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.038579 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.038579 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9749.135565 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9749.135565 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9749.135565 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101078.947368 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101078.947368 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7104941 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7105044 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 91 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85411059000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 85411059000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85411059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 85411059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85411059000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 85411059000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9620500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9620500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9620500 # 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average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101268.421053 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101268.421053 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7056390 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7056554 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 145 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 891372 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2193537 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13101.642441 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 12964075 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2209317 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.867911 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 902638 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2217652 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13067.579403 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 12709221 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2233219 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.690987 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12819.727283 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 29.247108 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.647207 # 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Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 74 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1753 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6630 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5167 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1593 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021851 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 27 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 328 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1567 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5612 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2311 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017517 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004272 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.928345 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 477362276 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 477362276 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 532002 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159372 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 691374 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3201676 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3201676 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 10651334 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 10651334 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 860878 # 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mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258138 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.622282 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.622282 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250211 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.131744 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250211 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197229 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197229 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077033 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255230 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255230 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.605915 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.605915 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130867 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181418 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26249.340195 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41279.535876 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18946.023968 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18946.023968 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15335.070361 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.070361 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 507499.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 507499.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36295.761406 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36295.761406 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28796.745581 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29009.738661 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29009.738661 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23270.062377 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23270.062377 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30459.410352 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29784.321781 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30459.410352 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32931.828565 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 118671.713548 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118327.481240 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58417.838220 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58648.912281 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 29139456 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14890637 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1736 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 592017 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 591980 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 37 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 780515 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13649954 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7187 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7187 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4195318 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 11056894 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1429217 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 912059 # Transaction distribution +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182864 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30928.658785 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50497.672698 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18872.719322 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18872.719322 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15417.751476 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15417.751476 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 547333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 547333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 41458.896369 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 41458.896369 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29291.826767 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32341.000946 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32341.000946 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 25018.092526 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 25018.092526 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32262.599426 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37447.694650 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111042.307692 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110731.059908 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55856.502454 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56188.943972 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 28529787 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14583123 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1708 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 606717 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 606667 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 50 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 808882 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13324164 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5266 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5266 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4382442 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 10653044 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1404546 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 947399 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 423433 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346671 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 478761 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1089502 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1063784 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9106528 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4703864 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 480825 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 417736 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27319260 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16358508 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 344119 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1118457 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 45140344 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1165608768 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 632082996 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1297016 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4215976 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1803204756 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5174570 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 77236160 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 20377107 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.044844 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.206971 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeReq 393688 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362209 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 470974 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1116382 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1090257 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8723185 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4832581 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 501349 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 440463 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26169233 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16578335 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 358731 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1168114 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 44274413 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1116540992 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 640957756 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1358376 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4428728 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1763285852 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5350505 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 82373864 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 20276302 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.045824 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.209116 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 19463345 95.52% 95.52% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 913725 4.48% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 37 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 19347205 95.42% 95.42% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 929047 4.58% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 50 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 20377107 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 28962136490 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 20276302 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 28368994985 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 181919759 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 177802789 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13662646557 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13087773257 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7521057995 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7613339196 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 182080323 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 189022822 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 591562794 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 614644257 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40336 # Transaction distribution -system.iobus.trans_dist::ReadResp 40336 # Transaction distribution -system.iobus.trans_dist::WriteReq 136646 # Transaction distribution -system.iobus.trans_dist::WriteResp 136645 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47799 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40225 # Transaction distribution +system.iobus.trans_dist::ReadResp 40225 # Transaction distribution +system.iobus.trans_dist::WriteReq 136513 # Transaction distribution +system.iobus.trans_dist::WriteResp 136513 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47228 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2463,15 +2451,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122681 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231202 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122162 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353963 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47820 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2482,105 +2470,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155812 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155269 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496722 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42736003 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496307 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42338500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 316501 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25813003 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25881501 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34441500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34511002 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569849738 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570151601 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92766000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92380000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147898000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147930000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115581 # number of replacements -system.iocache.tags.tagsinuse 11.283387 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115597 # number of replacements +system.iocache.tags.tagsinuse 11.280611 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115597 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9167357489000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.841167 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.442220 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240073 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465139 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705212 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9162473233000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.844749 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.435862 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240297 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.464741 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705038 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040766 # Number of tag accesses -system.iocache.tags.data_accesses 1040766 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040910 # Number of tag accesses +system.iocache.tags.data_accesses 1040910 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8873 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8910 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115601 # number of demand (read+write) misses -system.iocache.demand_misses::total 115641 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115617 # number of demand (read+write) misses +system.iocache.demand_misses::total 115657 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115601 # number of overall misses -system.iocache.overall_misses::total 115641 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5212500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1870801980 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1876014480 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115617 # number of overall misses +system.iocache.overall_misses::total 115657 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1980206431 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1985402931 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13212782258 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13212782258 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5581500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15083584238 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15089165738 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5581500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15083584238 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15089165738 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13190432670 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13190432670 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15170639101 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15176204601 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15170639101 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15176204601 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8873 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115601 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115641 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115617 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115657 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115601 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115641 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115617 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115657 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2594,53 +2582,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140878.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 210842.103009 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 210551.569024 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 222770.438857 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 222429.187878 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123798.649445 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 123798.649445 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130479.703791 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130482.836866 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130479.703791 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130482.836866 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 43615 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123589.242467 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 123589.242467 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131217.346127 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131217.346127 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 49271 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3583 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.338048 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.751326 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106693 # number of writebacks system.iocache.writebacks::total 106693 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8873 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115601 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115641 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115617 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115657 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115601 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115641 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3362500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1427151980 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1430514480 # 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number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3565500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9383611618 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9387177118 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2654,655 +2642,653 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90878.378378 # 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average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80430.519009 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80433.669097 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80430.519009 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80433.669097 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1414426 # number of replacements -system.l2c.tags.tagsinuse 65137.583571 # Cycle average of tags in use -system.l2c.tags.total_refs 6994560 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1476169 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.738319 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8133240500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 11569.884492 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 195.527132 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 189.575172 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5571.537349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 16752.169298 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10126.474274 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 243.722413 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 247.067471 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3668.697792 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 7415.172357 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9157.755820 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.176542 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002984 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002893 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.085015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.255618 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.154518 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003719 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003770 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055980 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.113147 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.139736 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993921 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10627 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 250 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50866 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 125 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 764 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9737 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4265 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 44783 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.162155 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003815 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.776154 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 76792424 # Number of tag accesses -system.l2c.tags.data_accesses 76792424 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2702608 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2702608 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 192434 # 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number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10640 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4481 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 647147 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 570987 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 311044 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3065515 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 124497 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 122676 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 247173 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 13231 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5451 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 616225 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 637581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 304510 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10640 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4481 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 647147 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 623092 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 311044 # number of demand (read+write) hits -system.l2c.demand_hits::total 3173402 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 13231 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5451 # number of overall hits -system.l2c.overall_hits::cpu0.inst 616225 # number of overall hits -system.l2c.overall_hits::cpu0.data 637581 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 304510 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10640 # 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number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2187 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1999 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 72224 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 145719 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 234962 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1644 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1517 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 52978 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 99810 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 174436 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 787476 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 432248 # 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average overall miss latency -system.l2c.blocked_cycles::no_mshrs 159 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73531.361845 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73531.361845 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1609900 # number of replacements +system.l2c.tags.tagsinuse 65157.020292 # Cycle average of tags in use +system.l2c.tags.total_refs 7484861 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1671770 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.477207 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 3329231500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10396.250510 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.300313 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 163.171529 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4900.186700 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 12808.046984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9631.875704 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 290.820455 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 308.484030 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3535.017429 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11523.081214 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11426.785423 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.158634 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002644 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074771 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.195435 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.146971 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004438 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.004707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.053940 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.175828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.174359 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994217 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10593 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 251 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 51026 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 126 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 461 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10006 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 251 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1785 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4614 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 44401 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.161636 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003830 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.778595 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 82772579 # Number of tag accesses +system.l2c.tags.data_accesses 82772579 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2960473 # 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average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166945.911410 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100691.717485 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105844.975070 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83937.204268 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49559.704939 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74416.427597 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3622014 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2135906 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2993 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.085764 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129643 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.104423 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010986 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016697 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.198682 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.225948 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.755318 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.473091 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.672296 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.243715 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.243715 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20198.853484 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20490.546689 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20352.846720 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24189.871835 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24350.849257 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24286.212834 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 95738.372205 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 96148.357144 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 95899.699774 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101195.083485 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 99405.485455 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116188.020453 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20693.800748 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19264.244872 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20397.878494 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165838.922795 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93065.784722 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 146926.923463 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82966.299253 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46805.220030 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77550.394545 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3927234 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2267569 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 90895 # Transaction distribution -system.membus.trans_dist::ReadResp 886992 # Transaction distribution -system.membus.trans_dist::WriteReq 38388 # Transaction distribution -system.membus.trans_dist::WriteResp 38387 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1171327 # Transaction distribution -system.membus.trans_dist::CleanEvict 257625 # Transaction distribution -system.membus.trans_dist::UpgradeReq 339183 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 279038 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 42476 # Transaction distribution +system.membus.trans_dist::ReadResp 989688 # Transaction distribution +system.membus.trans_dist::WriteReq 37999 # Transaction distribution +system.membus.trans_dist::WriteResp 37999 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1312599 # Transaction distribution +system.membus.trans_dist::CleanEvict 291937 # Transaction distribution +system.membus.trans_dist::UpgradeReq 286456 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 289177 # Transaction distribution system.membus.trans_dist::UpgradeResp 24 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 141595 # Transaction distribution -system.membus.trans_dist::ReadExResp 126059 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 796097 # Transaction distribution -system.membus.trans_dist::InvalidateReq 636810 # Transaction distribution -system.membus.trans_dist::InvalidateResp 29788 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122681 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 150791 # Transaction distribution +system.membus.trans_dist::ReadExResp 135122 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 947213 # Transaction distribution +system.membus.trans_dist::InvalidateReq 648655 # Transaction distribution +system.membus.trans_dist::InvalidateResp 27962 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122162 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4412900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4561541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238275 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238275 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4799816 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4782183 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4929211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238327 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238327 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5167538 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155269 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51812 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129909760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 130118772 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7279744 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7279744 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 137398516 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 631660 # Total snoops (count) -system.membus.snoopTraffic 165184 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2322011 # Request fanout histogram -system.membus.snoop_fanout::mean 0.014128 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.118018 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146129536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 146335817 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7281024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 153616841 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 586564 # Total snoops (count) +system.membus.snoopTraffic 164864 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2402773 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012913 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.112899 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2289206 98.59% 98.59% # Request fanout histogram -system.membus.snoop_fanout::1 32805 1.41% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2371746 98.71% 98.71% # Request fanout histogram +system.membus.snoop_fanout::1 31027 1.29% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2322011 # Request fanout histogram -system.membus.reqLayer0.occupancy 103411493 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2402773 # Request fanout histogram +system.membus.reqLayer0.occupancy 103148497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21687499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20826497 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8057234059 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8952131044 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5202386097 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5789704061 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 79808698 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 78011284 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3345,79 +3331,79 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12161965 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6407928 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2357892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 209457 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 187271 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 22186 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 90897 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4728170 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38388 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38387 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3767242 # Transaction distribution +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12820673 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6781255 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2351025 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 247233 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 222755 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 24478 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 42478 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4925290 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 37999 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 37999 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4166379 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2958537 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 681779 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 382073 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1063852 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 289918 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 289918 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4637675 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 890912 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 871981 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9721848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8056306 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17778154 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 242672912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 195596708 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 438269620 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2964469 # Total snoops (count) -system.toL2Bus.snoopTraffic 121867728 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8426211 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.390204 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.493164 # Request fanout histogram +system.toL2Bus.trans_dist::CleanEvict 3160031 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 651791 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 401547 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1053338 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 305355 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 305355 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4883226 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 892239 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 875311 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10573421 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8142599 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18716020 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267921245 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 204226604 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 472147849 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3035429 # Total snoops (count) +system.toL2Bus.snoopTraffic 127161424 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8824674 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.367843 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.487937 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5160452 61.24% 61.24% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3243573 38.49% 99.74% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 22186 0.26% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5603059 63.49% 63.49% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3197137 36.23% 99.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 24478 0.28% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8426211 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9265268057 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8824674 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9845744502 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 8336972 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 8465131 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4478456950 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4808552711 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4027071928 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4013025600 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 6bb63026a..0eefafc2a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.688741 # Number of seconds simulated -sim_ticks 51688741391000 # Number of ticks simulated -final_tick 51688741391000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.643658 # Number of seconds simulated +sim_ticks 51643657651000 # Number of ticks simulated +final_tick 51643657651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 269524 # Simulator instruction rate (inst/s) -host_op_rate 316717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14692427127 # Simulator tick rate (ticks/s) -host_mem_usage 686428 # Number of bytes of host memory used -host_seconds 3518.05 # Real time elapsed on the host -sim_insts 948199503 # Number of instructions simulated -sim_ops 1114227092 # Number of ops (including micro ops) simulated +host_inst_rate 290656 # Simulator instruction rate (inst/s) +host_op_rate 346501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16573581112 # Simulator tick rate (ticks/s) +host_mem_usage 686852 # Number of bytes of host memory used +host_seconds 3116.02 # Real time elapsed on the host +sim_insts 905689769 # Number of instructions simulated +sim_ops 1079705427 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 396416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 330752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10254464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 65885128 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 402816 # Number of bytes read from this memory -system.physmem.bytes_read::total 77269576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10254464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10254464 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 94159808 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 481856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 390720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 7301696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 78480968 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 396608 # Number of bytes read from this memory +system.physmem.bytes_read::total 87051848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 7301696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7301696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 106840192 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 94180388 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6194 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 160226 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1029468 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6294 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1207350 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1471247 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 106860772 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 7529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 114089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1226278 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1360198 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1669378 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1473820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7669 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 198389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1274651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1494901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 198389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 198389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1821670 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1822068 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1821670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 198389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1275050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3316969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1207350 # Number of read requests accepted -system.physmem.writeReqs 1473820 # Number of write requests accepted -system.physmem.readBursts 1207350 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1473820 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 77222592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 47808 # Total number of bytes read from write queue -system.physmem.bytesWritten 94178368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 77269576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 94180388 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 747 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one +system.physmem.num_writes::total 1671951 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 9330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 7566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 141386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1519663 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1685625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 141386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2068796 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2069194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2068796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 9330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 7566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 141386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1520062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3754820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1360198 # Number of read requests accepted +system.physmem.writeReqs 1671951 # Number of write requests accepted +system.physmem.readBursts 1360198 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1671951 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 86990528 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 62144 # Total number of bytes read from write queue +system.physmem.bytesWritten 106858944 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 87051848 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 106860772 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 971 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 73856 # Per bank write bursts -system.physmem.perBankRdBursts::1 76732 # Per bank write bursts -system.physmem.perBankRdBursts::2 71137 # Per bank write bursts -system.physmem.perBankRdBursts::3 69219 # Per bank write bursts -system.physmem.perBankRdBursts::4 73839 # Per bank write bursts -system.physmem.perBankRdBursts::5 75948 # Per bank write bursts -system.physmem.perBankRdBursts::6 69505 # Per bank write bursts -system.physmem.perBankRdBursts::7 70913 # Per bank write bursts -system.physmem.perBankRdBursts::8 66486 # Per bank write bursts -system.physmem.perBankRdBursts::9 126372 # Per bank write bursts -system.physmem.perBankRdBursts::10 74130 # Per bank write bursts -system.physmem.perBankRdBursts::11 75275 # Per bank write bursts -system.physmem.perBankRdBursts::12 69111 # Per bank write bursts -system.physmem.perBankRdBursts::13 75650 # Per bank write bursts -system.physmem.perBankRdBursts::14 65166 # Per bank write bursts -system.physmem.perBankRdBursts::15 73264 # Per bank write bursts -system.physmem.perBankWrBursts::0 92929 # Per bank write bursts -system.physmem.perBankWrBursts::1 92717 # Per bank write bursts -system.physmem.perBankWrBursts::2 91280 # Per bank write bursts -system.physmem.perBankWrBursts::3 89601 # Per bank write bursts -system.physmem.perBankWrBursts::4 92792 # Per bank write bursts -system.physmem.perBankWrBursts::5 94531 # Per bank write bursts -system.physmem.perBankWrBursts::6 90574 # Per bank write bursts -system.physmem.perBankWrBursts::7 91937 # Per bank write bursts -system.physmem.perBankWrBursts::8 87601 # Per bank write bursts -system.physmem.perBankWrBursts::9 94297 # Per bank write bursts -system.physmem.perBankWrBursts::10 91232 # Per bank write bursts -system.physmem.perBankWrBursts::11 93669 # Per bank write bursts -system.physmem.perBankWrBursts::12 91213 # Per bank write bursts -system.physmem.perBankWrBursts::13 96164 # Per bank write bursts -system.physmem.perBankWrBursts::14 87189 # Per bank write bursts -system.physmem.perBankWrBursts::15 93811 # Per bank write bursts +system.physmem.perBankRdBursts::0 83237 # Per bank write bursts +system.physmem.perBankRdBursts::1 85225 # Per bank write bursts +system.physmem.perBankRdBursts::2 82489 # Per bank write bursts +system.physmem.perBankRdBursts::3 80125 # Per bank write bursts +system.physmem.perBankRdBursts::4 87648 # Per bank write bursts +system.physmem.perBankRdBursts::5 94125 # Per bank write bursts +system.physmem.perBankRdBursts::6 89556 # Per bank write bursts +system.physmem.perBankRdBursts::7 88166 # Per bank write bursts +system.physmem.perBankRdBursts::8 78937 # Per bank write bursts +system.physmem.perBankRdBursts::9 92012 # Per bank write bursts +system.physmem.perBankRdBursts::10 85547 # Per bank write bursts +system.physmem.perBankRdBursts::11 87304 # Per bank write bursts +system.physmem.perBankRdBursts::12 77322 # Per bank write bursts +system.physmem.perBankRdBursts::13 84061 # Per bank write bursts +system.physmem.perBankRdBursts::14 80795 # Per bank write bursts +system.physmem.perBankRdBursts::15 82678 # Per bank write bursts +system.physmem.perBankWrBursts::0 101181 # Per bank write bursts +system.physmem.perBankWrBursts::1 102649 # Per bank write bursts +system.physmem.perBankWrBursts::2 102280 # Per bank write bursts +system.physmem.perBankWrBursts::3 101626 # Per bank write bursts +system.physmem.perBankWrBursts::4 106705 # Per bank write bursts +system.physmem.perBankWrBursts::5 111943 # Per bank write bursts +system.physmem.perBankWrBursts::6 107546 # Per bank write bursts +system.physmem.perBankWrBursts::7 108809 # Per bank write bursts +system.physmem.perBankWrBursts::8 101631 # Per bank write bursts +system.physmem.perBankWrBursts::9 107791 # Per bank write bursts +system.physmem.perBankWrBursts::10 102979 # Per bank write bursts +system.physmem.perBankWrBursts::11 104017 # Per bank write bursts +system.physmem.perBankWrBursts::12 98121 # Per bank write bursts +system.physmem.perBankWrBursts::13 104909 # Per bank write bursts +system.physmem.perBankWrBursts::14 102656 # Per bank write bursts +system.physmem.perBankWrBursts::15 104828 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 476 # Number of times write queue was full causing retry -system.physmem.totGap 51688739531000 # Total gap between requests +system.physmem.numWrRetry 458 # Number of times write queue was full causing retry +system.physmem.totGap 51643655791000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1207335 # Read request sizes (log2) +system.physmem.readPktSize::6 1360183 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1471247 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1136082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 447 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1669378 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1282957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 444 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 74 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,186 +160,171 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 79220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 85555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 88116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 84810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 88690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 87321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 89133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 85642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 88726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 90107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 87724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 84525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 83639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 82667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 80351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 80396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1031 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 665465 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 257.565125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.597276 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 293.769616 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 284377 42.73% 42.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 171033 25.70% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 61820 9.29% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34355 5.16% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24207 3.64% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 15228 2.29% 88.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11511 1.73% 90.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9122 1.37% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 53812 8.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 665465 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 77525 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.563805 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 141.518145 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 77523 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 77525 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 77525 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.981451 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.132244 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.585951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 65037 83.89% 83.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 3875 5.00% 88.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3091 3.99% 92.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 2418 3.12% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1125 1.45% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 202 0.26% 97.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 259 0.33% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 156 0.20% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 148 0.19% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 64 0.08% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 86 0.11% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 78 0.10% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 560 0.72% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 82 0.11% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 101 0.13% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 77 0.10% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 43 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 18 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 7 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 20 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 10 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 77525 # Writes before turning the bus around for reads -system.physmem.totQLat 38963077638 # Total ticks spent queuing -system.physmem.totMemAccLat 61586883888 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6033015000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32291.55 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 31821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 90821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 97628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 100256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 96883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 101095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 99439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 101345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 97950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 101005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 102593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 99923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 96951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 96056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 95043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 92451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 92535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1009 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 752315 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 257.670024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 155.219861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 291.691185 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 319843 42.51% 42.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 192789 25.63% 68.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 70379 9.35% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 39533 5.25% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 27835 3.70% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 18762 2.49% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14354 1.91% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11626 1.55% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 57194 7.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 752315 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 89671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.157342 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 22.777727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 89658 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 89671 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 89671 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.619966 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.881543 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.948219 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 81046 90.38% 90.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 5562 6.20% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 1304 1.45% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 395 0.44% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 213 0.24% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 159 0.18% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 654 0.73% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 203 0.23% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 30 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 17 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 4 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 4 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 32 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 13 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 89671 # Writes before turning the bus around for reads +system.physmem.totQLat 40684785332 # Total ticks spent queuing +system.physmem.totMemAccLat 66170291582 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6796135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29932.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51041.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.82 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48682.30 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.69 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.07 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.17 # Average write queue length when enqueuing -system.physmem.readRowHits 937085 # Number of row buffer hits during reads -system.physmem.writeRowHits 1075589 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.09 # Row buffer hit rate for writes -system.physmem.avgGap 19278426.78 # Average gap between requests -system.physmem.pageHitRate 75.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2387508900 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1268991075 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4149403860 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3843804420 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50777254320.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 43920274980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3215166720 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 97172465130 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 73954032000 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12292934061825 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12573646841220 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.256974 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51583978414040 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 5941628250 # Time in different power states -system.physmem_0.memoryStateTime::REF 21591460000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51178312983500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 192588592528 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77208837210 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 213097889512 # Time in different power states -system.physmem_1.actEnergy 2363918340 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1256448600 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4465741560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3837618720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 51996700080.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 45282427920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3208431840 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 99358559340 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 75199350240 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12290630942340 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12577622785650 # Total energy per rank (pJ) -system.physmem_1.averagePower 243.333895 # Core power per rank (mW) -system.physmem_1.totalIdleTime 51581032449783 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 5840657750 # Time in different power states -system.physmem_1.memoryStateTime::REF 22110720000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51167308964000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 195831815407 # Time in different power states -system.physmem_1.memoryStateTime::ACT 79757518717 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 217891715126 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing +system.physmem.readRowHits 1052962 # Number of row buffer hits during reads +system.physmem.writeRowHits 1223619 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes +system.physmem.avgGap 17032031.01 # Average gap between requests +system.physmem.pageHitRate 75.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2732670780 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1452445170 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4930676940 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4399097580 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 51881762400.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47976087180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3104058720 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 109980529290 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71485388640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12273611587950 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12571576503750 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.429243 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51530314812756 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 5413929000 # Time in different power states +system.physmem_0.memoryStateTime::REF 22045432000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51102968874750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 186159553736 # Time in different power states +system.physmem_0.memoryStateTime::ACT 85883432494 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 241186429020 # Time in different power states +system.physmem_1.actEnergy 2638872600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1402590255 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4774203840 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4316585040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 51214263360.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 48316306500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3067085280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 106463182980 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 70942598400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12275647651350 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12568805141895 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.375580 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51529660585796 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5336166484 # Time in different power states +system.physmem_1.memoryStateTime::REF 21762952000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51111446865750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 184746715790 # Time in different power states +system.physmem_1.memoryStateTime::ACT 86892179220 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 233472771756 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory @@ -356,30 +341,30 @@ system.realview.nvmem.bw_inst_read::total 14 # I system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 261998834 # Number of BP lookups -system.cpu.branchPred.condPredicted 182856277 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12304668 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 193336179 # Number of BTB lookups -system.cpu.branchPred.BTBHits 130354436 # Number of BTB hits +system.cpu.branchPred.lookups 230671595 # Number of BP lookups +system.cpu.branchPred.condPredicted 148977251 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12591272 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 161205478 # Number of BTB lookups +system.cpu.branchPred.BTBHits 94166388 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 67.423716 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31812925 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2139415 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7174940 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 5106056 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2068884 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 846506 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 58.413888 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 32707519 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2199358 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7428890 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 5357971 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2070919 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 851352 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -409,65 +394,66 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 578626 # Table walker walks requested -system.cpu.dtb.walker.walksLong 578626 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22326 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 190823 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 578626 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 578626 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 578626 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 213149 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 25594.731854 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21754.484647 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 18075.189624 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 210684 98.84% 98.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2067 0.97% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 93 0.04% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 125 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 100 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 34 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 213149 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 316311704 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 316311704 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 316311704 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 190824 89.53% 89.53% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 22326 10.47% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 213150 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 578626 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 612824 # Table walker walks requested +system.cpu.dtb.walker.walksLong 612824 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 25045 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 213625 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 612824 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 612824 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 612824 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 238670 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26656.848368 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 22869.063207 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18178.269726 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 235680 98.75% 98.75% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2495 1.05% 99.79% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 126 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 157 0.07% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 125 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 14 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 28 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 238670 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 411876000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 411876000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 411876000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 213626 89.51% 89.51% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 25045 10.49% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 238671 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 612824 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 578626 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213150 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 612824 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 238671 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213150 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 791776 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 238671 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 851495 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 182986827 # DTB read hits -system.cpu.dtb.read_misses 476580 # DTB read misses -system.cpu.dtb.write_hits 162437421 # DTB write hits -system.cpu.dtb.write_misses 102046 # DTB write misses +system.cpu.dtb.read_hits 191427667 # DTB read hits +system.cpu.dtb.read_misses 503751 # DTB read misses +system.cpu.dtb.write_hits 170371453 # DTB write hits +system.cpu.dtb.write_misses 109073 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47208 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 80100 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1397 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15136 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 50563 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1145 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 82805 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 891 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 16210 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23302 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183463407 # DTB read accesses -system.cpu.dtb.write_accesses 162539467 # DTB write accesses +system.cpu.dtb.perms_faults 24062 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 191931418 # DTB read accesses +system.cpu.dtb.write_accesses 170480526 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 345424248 # DTB hits -system.cpu.dtb.misses 578626 # DTB misses -system.cpu.dtb.accesses 346002874 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 361799120 # DTB hits +system.cpu.dtb.misses 612824 # DTB misses +system.cpu.dtb.accesses 362411944 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -497,834 +483,833 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 136092 # Table walker walks requested -system.cpu.itb.walker.walksLong 136092 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1064 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 118204 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136092 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136092 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136092 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 119268 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28638.176208 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24049.001367 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 28797.920728 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 116455 97.64% 97.64% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2388 2.00% 99.64% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 112 0.09% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 99 0.08% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 27 0.02% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 23 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 4 0.00% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 153 0.13% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 119268 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 315425204 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 315425204 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 315425204 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 118204 99.11% 99.11% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1064 0.89% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 119268 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 137744 # Table walker walks requested +system.cpu.itb.walker.walksLong 137744 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1060 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 119122 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 137744 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 137744 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 137744 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 120182 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28731.482252 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24330.551658 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24049.037609 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 116919 97.28% 97.28% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2876 2.39% 99.68% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 146 0.12% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 107 0.09% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 36 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 28 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 64 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 120182 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 411203500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 411203500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 411203500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 119122 99.12% 99.12% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1060 0.88% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 120182 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136092 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136092 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 137744 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 137744 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119268 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 119268 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 255360 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 453450761 # ITB inst hits -system.cpu.itb.inst_misses 136092 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120182 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 120182 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 257926 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 367199991 # ITB inst hits +system.cpu.itb.inst_misses 137744 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47208 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57496 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 50563 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1145 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 59110 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 333218 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 331525 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 453586853 # ITB inst accesses -system.cpu.itb.hits 453450761 # DTB hits -system.cpu.itb.misses 136092 # DTB misses -system.cpu.itb.accesses 453586853 # DTB accesses -system.cpu.numPwrStateTransitions 33202 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16601 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3037201042.152340 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59610606886.622597 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7303 43.99% 43.99% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9263 55.80% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 367337735 # ITB inst accesses +system.cpu.itb.hits 367199991 # DTB hits +system.cpu.itb.misses 137744 # DTB misses +system.cpu.itb.accesses 367337735 # DTB accesses +system.cpu.numPwrStateTransitions 33588 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16794 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3006267839.468917 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59370181603.459618 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7493 44.62% 44.62% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9266 55.17% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988777738856 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16601 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1268166890229 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50420574500771 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2536387791 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988777658384 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16794 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1156395554959 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50487262096041 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2312845645 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 948199503 # Number of instructions committed -system.cpu.committedOps 1114227092 # Number of ops (including micro ops) committed -system.cpu.discardedOps 98303819 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7741 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100842203450 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.674952 # CPI: cycles per instruction -system.cpu.ipc 0.373839 # IPC: instructions per cycle +system.cpu.committedInsts 905689769 # Number of instructions committed +system.cpu.committedOps 1079705427 # Number of ops (including micro ops) committed +system.cpu.discardedOps 38872378 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7934 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100975614107 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.553684 # CPI: cycles per instruction +system.cpu.ipc 0.391591 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 772296777 69.31% 69.31% # Class of committed instruction -system.cpu.op_class_0::IntMult 2306158 0.21% 69.52% # Class of committed instruction -system.cpu.op_class_0::IntDiv 98958 0.01% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 8 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 13 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 21 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 108924 0.01% 69.54% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::MemRead 177418599 15.92% 85.46% # Class of committed instruction -system.cpu.op_class_0::MemWrite 161212850 14.47% 99.93% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 115060 0.01% 99.94% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 669723 0.06% 100.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 721452382 66.82% 66.82% # Class of committed instruction +system.cpu.op_class_0::IntMult 2371003 0.22% 67.04% # Class of committed instruction +system.cpu.op_class_0::IntDiv 100622 0.01% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 8 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 13 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 21 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 107773 0.01% 67.06% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::MemRead 185747611 17.20% 84.26% # Class of committed instruction +system.cpu.op_class_0::MemWrite 169152555 15.67% 99.93% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 112557 0.01% 99.94% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 660881 0.06% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1114227092 # Class of committed instruction +system.cpu.op_class_0::total 1079705427 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16601 # number of quiesce instructions executed -system.cpu.tickCycles 1794953387 # Number of cycles that the object actually ticked -system.cpu.idleCycles 741434404 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11118153 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.954086 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 329643971 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11118665 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.647801 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4655908500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.954086 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16794 # number of quiesce instructions executed +system.cpu.tickCycles 1555844114 # Number of cycles that the object actually ticked +system.cpu.idleCycles 757001531 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11832637 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.995677 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 345046750 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11833149 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.159335 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 456752500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995677 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999992 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1383364255 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1383364255 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 168779255 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 168779255 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 151620030 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 151620030 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 521599 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 521599 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 337919 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 337919 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4018497 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4018497 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4332994 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4332994 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 320737204 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320737204 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 321258803 # number of overall hits -system.cpu.dcache.overall_hits::total 321258803 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6105244 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6105244 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4304073 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4304073 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1482683 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1482683 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1242865 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1242865 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 316228 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 316228 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1449239878 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1449239878 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 176307264 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 176307264 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158900158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158900158 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 537417 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 537417 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 337852 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 337852 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4300418 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4300418 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4627725 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4627725 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 335545274 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 335545274 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 336082691 # number of overall hits +system.cpu.dcache.overall_hits::total 336082691 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6490291 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6490291 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4646590 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4646590 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1620869 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1620869 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1254011 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1254011 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 329077 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 329077 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # 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number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5074922000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 12390892 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12390892 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 14011761 # number of overall misses +system.cpu.dcache.overall_misses::total 14011761 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114759870500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114759870500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 196713087999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 196713087999 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27879484500 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 27879484500 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5348350500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5348350500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 304984448500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 304984448500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 304984448500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 304984448500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 174884499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 174884499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 155924103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 155924103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2004282 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2004282 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1580784 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1580784 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4334725 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4334725 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4332995 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4332995 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 332389386 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 332389386 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 334393668 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 334393668 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034910 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.034910 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027604 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027604 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.739758 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.739758 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786233 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786233 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.072952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.072952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 339352442999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 339352442999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 339352442999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 339352442999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 182797555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 182797555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 163546748 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 163546748 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2158286 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2158286 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1591863 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1591863 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4629495 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4629495 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4627726 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4627726 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 347936166 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 347936166 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 350094452 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 350094452 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035505 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035505 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028411 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.028411 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.750998 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.750998 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787763 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.787763 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.071083 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.071083 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035056 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035056 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039280 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039280 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.779426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.779426 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39551.139700 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39551.139700 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21972.308738 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 21972.308738 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16048.300593 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16048.300593 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.035613 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035613 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.040023 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.040023 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.775825 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17681.775825 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42334.935512 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42334.935512 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22232.248760 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22232.248760 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16252.580703 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16252.580703 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26174.020325 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26174.020325 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23219.458175 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23219.458175 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27387.248876 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27387.248876 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24219.114428 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24219.114428 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 135 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8530547 # number of writebacks -system.cpu.dcache.writebacks::total 8530547 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 315482 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 315482 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1904891 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1904891 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 158 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 158 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70720 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 70720 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2220531 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2220531 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2220531 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2220531 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5789762 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5789762 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2399182 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2399182 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1475215 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1475215 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1242707 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1242707 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 245508 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 245508 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 9058668 # number of writebacks +system.cpu.dcache.writebacks::total 9058668 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 331345 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 331345 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2059664 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2059664 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 161 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 161 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 73138 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 73138 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2391170 # 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number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 255939 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9431651 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9431651 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 10906866 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 10906866 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 94938379000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 94938379000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89047691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 89047691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 25686251500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 25686251500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26061179000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26061179000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3474287500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3474287500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9999722 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9999722 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 11613158 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 11613158 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33608 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33608 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33620 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33620 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67228 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67228 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 101472833000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 101472833000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 102652778000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 102652778000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 27900020500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 27900020500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26619580500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26619580500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3678632000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3678632000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 210047249000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 210047249000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 235733500500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 235733500500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6230847500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6230847500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6230847500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6230847500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033106 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033106 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015387 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015387 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.736032 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.736032 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786133 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786133 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056638 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056638 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230745191500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230745191500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 258645212000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 258645212000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6209488500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6209488500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6209488500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6209488500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033693 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033693 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015818 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015818 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.747554 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.747554 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787662 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787662 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.055284 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.055284 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028375 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028375 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032617 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032617 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16397.630680 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16397.630680 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37115.854904 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37115.854904 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17411.869795 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17411.869795 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20971.298142 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20971.298142 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14151.422764 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14151.422764 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028740 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028740 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.033171 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.033171 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16475.681553 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16475.681553 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39681.373955 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39681.373955 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17292.300717 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17292.300717 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21230.275153 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21230.275153 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14373.081086 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14373.081086 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.464524 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.464524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21613.312248 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21613.312248 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184913.565408 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184913.565408 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92441.693990 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92441.693990 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24600209 # number of replacements -system.cpu.icache.tags.tagsinuse 511.926335 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 428505873 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24600721 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.418427 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 21430954500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.926335 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999856 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999856 # Average percentage of cache occupancy +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23075.160639 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23075.160639 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22271.737972 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22271.737972 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184762.214354 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184762.214354 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92364.617421 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92364.617421 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 477707334 # Number of tag accesses -system.cpu.icache.tags.data_accesses 477707334 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 428505873 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 428505873 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 428505873 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 428505873 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13428.664385 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24600209 # number of writebacks -system.cpu.icache.writebacks::total 24600209 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24600731 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24600731 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24600731 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24600731 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24600731 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24600731 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52291 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 52291 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52291 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 52291 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305886016500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 305886016500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305886016500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 305886016500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305886016500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 305886016500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4421533000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4421533000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4421533000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 4421533000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054293 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.054293 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.054293 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12434.021432 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12434.021432 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12434.021432 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12434.021432 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12434.021432 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12434.021432 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 84556.290757 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 84556.290757 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 84556.290757 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 84556.290757 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1601564 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65405.294347 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 69675530 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1664947 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 41.848497 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6255171000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9201.337762 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 431.981496 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 403.879639 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8049.770162 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47318.325288 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.140401 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006592 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006163 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122830 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.722020 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998006 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 257 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63126 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 257 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 803 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5965 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56053 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963226 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 583673795 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 120560235052 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 801715000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 583775000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10594574503 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108580170549 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 120560235052 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 299820000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5789264500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6089084500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 299820000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5789264500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6089084500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.119391 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.119391 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.111080 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.111080 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.296811 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.296811 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004389 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043736 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043736 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.437470 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.437470 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006677 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.019472 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104360 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.032240 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006677 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.019472 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104360 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.032240 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132527.635980 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19094.527363 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19094.527363 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.337030 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.337030 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004372 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045792 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045792 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.451358 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.451358 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.116025 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.036514 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.116025 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.036514 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 101620.214170 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19087.365254 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19087.365254 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86157.418261 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86157.418261 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97320.791795 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97320.791795 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103206.522637 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103206.522637 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20646.604324 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20646.604324 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97320.791795 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91590.850920 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92533.245432 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97320.791795 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91590.850920 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92533.245432 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172410.508666 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109557.880842 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86191.185852 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78705.311043 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 72189026 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 36469595 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4452 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1946 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1946 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83654.399923 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 83654.399923 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96468.663525 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96468.663525 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99696.569130 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99696.569130 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20598.429150 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20598.429150 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96468.663525 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88458.945068 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89242.928202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96468.663525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88458.945068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89242.928202 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69871.824749 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172258.524756 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160666.099369 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69871.824749 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86113.888558 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85139.396524 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 74678701 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 37723093 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4208 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1985 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1985 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1780354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33892071 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9895163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24600209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2824554 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 33674 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1826986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 34978302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 10621415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 25121901 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3034475 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 35914 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 33675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2365793 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2365793 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24600731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7513010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1271678 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1242738 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73906251 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33558527 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 672286 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2215155 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 110352219 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3152206656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1178259346 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2123232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7421360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4340010594 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2135457 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 91396008 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 39200512 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134637 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 35915 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2551242 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2551242 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 25122423 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 8030982 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1284314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1253880 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75375327 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35706122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 683214 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2401023 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 114165686 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3215911232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1257073518 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2170984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 8190216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4483345950 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2351379 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104018568 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 40708735 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018149 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133491 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 38476553 98.15% 98.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 723959 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 39969899 98.19% 98.19% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 738836 1.81% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 39200512 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 69790374998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 40708735 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 72100713496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1501881 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1533365 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36983722099 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 37694541038 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15503705051 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 16565349400 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 406910942 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 411872936 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1287502964 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1377265960 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40334 # Transaction distribution -system.iobus.trans_dist::ReadResp 40334 # Transaction distribution -system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 136571 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40237 # Transaction distribution +system.iobus.trans_dist::ReadResp 40237 # Transaction distribution +system.iobus.trans_dist::WriteReq 136485 # Transaction distribution +system.iobus.trans_dist::WriteResp 136485 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1337,13 +1322,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353810 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353444 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1356,19 +1341,19 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492456 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37695500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37126500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 339500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1378,81 +1363,81 @@ system.iobus.reqLayer13.occupancy 11000 # La system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25148500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25225000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36444000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36490500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569308376 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569036756 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147786000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147764000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115495 # number of replacements -system.iocache.tags.tagsinuse 10.448162 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115484 # number of replacements +system.iocache.tags.tagsinuse 10.444243 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115511 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13141692173000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.519394 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.928768 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219962 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433048 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653010 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13137487927000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.867221 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.577022 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.366701 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.286064 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652765 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039974 # Number of tag accesses -system.iocache.tags.data_accesses 1039974 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039875 # Number of tag accesses +system.iocache.tags.data_accesses 1039875 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8849 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8886 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115513 # number of demand (read+write) misses -system.iocache.demand_misses::total 115553 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115502 # number of demand (read+write) misses +system.iocache.demand_misses::total 115542 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115513 # number of overall misses -system.iocache.overall_misses::total 115553 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 2011459152 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 2016544652 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115502 # number of overall misses +system.iocache.overall_misses::total 115542 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 2014766150 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 2019852150 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13390572724 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13390572724 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15402031876 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15407468376 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15402031876 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15407468376 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13376583606 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13376583606 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15391349756 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15396786756 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15391349756 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15396786756 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8849 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8886 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115513 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115553 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115502 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115542 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115513 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115553 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115502 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115542 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1466,53 +1451,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 227309.204656 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 226935.027234 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 227966.298936 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 227588.974648 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125539.757781 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125539.757781 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 133335.917827 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 133336.809741 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 133335.917827 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 133336.809741 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 51202 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125408.606521 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125408.606521 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 133256.131980 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 133257.055928 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 133256.131980 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 133257.055928 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51744 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3365 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3369 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 15.216048 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 15.358860 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8849 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8886 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115513 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115553 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115502 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115542 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115513 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115553 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1569009152 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1572244652 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115502 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115542 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1572866150 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1576102150 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8051866391 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8051866391 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9620875543 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9624312043 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9620875543 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9624312043 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8037847459 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8037847459 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9610713609 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9614150609 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9610713609 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9614150609 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1526,96 +1511,96 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177309.204656 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 176935.027234 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177966.298936 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 177588.974648 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75488.134619 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75488.134619 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 83288.249314 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 83289.157728 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 83288.249314 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 83289.157728 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 3529625 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1749962 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3622 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75356.703846 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75356.703846 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 83208.200802 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 83209.141343 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 83208.200802 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 83209.141343 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 3974449 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1973040 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3773 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 85987 # Transaction distribution -system.membus.trans_dist::ReadResp 542659 # Transaction distribution -system.membus.trans_dist::WriteReq 33707 # Transaction distribution -system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1471247 # Transaction distribution -system.membus.trans_dist::CleanEvict 244702 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4583 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 37899 # Transaction distribution +system.membus.trans_dist::ReadResp 537851 # Transaction distribution +system.membus.trans_dist::WriteReq 33620 # Transaction distribution +system.membus.trans_dist::WriteResp 33620 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1669378 # Transaction distribution +system.membus.trans_dist::CleanEvict 268224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4552 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 701633 # Transaction distribution -system.membus.trans_dist::ReadExResp 701633 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 456672 # Transaction distribution -system.membus.trans_dist::InvalidateReq 650311 # Transaction distribution -system.membus.trans_dist::InvalidateResp 28814 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 859285 # Transaction distribution +system.membus.trans_dist::ReadExResp 859285 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 499952 # Transaction distribution +system.membus.trans_dist::InvalidateReq 672599 # Transaction distribution +system.membus.trans_dist::InvalidateResp 30234 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4556598 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4686250 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237342 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237342 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4923592 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5106407 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5235709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5472932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164222764 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164393170 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7227200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7227200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 171620370 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 32071 # Total snoops (count) -system.membus.snoopTraffic 208000 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1932895 # Request fanout histogram -system.membus.snoop_fanout::mean 0.016796 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.128505 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 186691628 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 186861678 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 194082670 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 33575 # Total snoops (count) +system.membus.snoopTraffic 213376 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2107909 # Request fanout histogram +system.membus.snoop_fanout::mean 0.016147 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.126040 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1900431 98.32% 98.32% # Request fanout histogram -system.membus.snoop_fanout::1 32464 1.68% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2073873 98.39% 98.39% # Request fanout histogram +system.membus.snoop_fanout::1 34036 1.61% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1932895 # Request fanout histogram -system.membus.reqLayer0.occupancy 99728500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2107909 # Request fanout histogram +system.membus.reqLayer0.occupancy 99276000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5568000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5601000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9720767792 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10934593718 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6477610584 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7287611424 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 75150025 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 76573457 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1658,28 +1643,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 37952af83..6dc4ab397 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.384940 # Number of seconds simulated -sim_ticks 47384940455000 # Number of ticks simulated -final_tick 47384940455000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.341923 # Number of seconds simulated +sim_ticks 47341923254000 # Number of ticks simulated +final_tick 47341923254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 206357 # Simulator instruction rate (inst/s) -host_op_rate 242664 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10614318936 # Simulator tick rate (ticks/s) -host_mem_usage 793572 # Number of bytes of host memory used -host_seconds 4464.25 # Real time elapsed on the host -sim_insts 921230293 # Number of instructions simulated -sim_ops 1083311023 # Number of ops (including micro ops) simulated +host_inst_rate 198941 # Simulator instruction rate (inst/s) +host_op_rate 237233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10723675807 # Simulator tick rate (ticks/s) +host_mem_usage 786956 # Number of bytes of host memory used +host_seconds 4414.71 # Real time elapsed on the host +sim_insts 878265186 # Number of instructions simulated +sim_ops 1047316960 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 222656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 215552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4481312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 16941064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 21659840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 116096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 80000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2978912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10395024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12881984 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 421760 # Number of bytes read from this memory -system.physmem.bytes_read::total 70394200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4481312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2978912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7460224 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 86479488 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 242176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 233728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4193568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 18888648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 25252160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 159808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 110720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3691360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 11578384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 16897024 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 434368 # Number of bytes read from this memory +system.physmem.bytes_read::total 81681944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4193568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3691360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7884928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 97721664 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 86500072 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 85973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 264717 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 338435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1814 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1250 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 46589 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 162435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 201281 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6590 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1115931 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1351242 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 97742248 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3652 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 67077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 295148 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 394565 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1730 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 57721 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 180925 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 264016 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6787 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1277902 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1526901 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1353816 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 4549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 94572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 357520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 457104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 62866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 219374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 271858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1485582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 94572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 62866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 157439 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1825042 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1529475 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 5115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 88580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 398984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 533400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 244569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 356915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1725362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 88580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 166553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2064168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1825476 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1825042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 4549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 94572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 357954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 457104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 62866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 219374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 271858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3311058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1115931 # Number of read requests accepted -system.physmem.writeReqs 1353816 # Number of write requests accepted -system.physmem.readBursts 1115931 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1353816 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 71392384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 27200 # Total number of bytes read from write queue -system.physmem.bytesWritten 86499392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 70394200 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 86500072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 425 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 2064602 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2064168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 5115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 88580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 399418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 533400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 244569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 356915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3789964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1277902 # Number of read requests accepted +system.physmem.writeReqs 1529475 # Number of write requests accepted +system.physmem.readBursts 1277902 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1529475 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 81759232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 26496 # Total number of bytes read from write queue +system.physmem.bytesWritten 97740224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 81681944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 97742248 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 414 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 66640 # Per bank write bursts -system.physmem.perBankRdBursts::1 69755 # Per bank write bursts -system.physmem.perBankRdBursts::2 65507 # Per bank write bursts -system.physmem.perBankRdBursts::3 67407 # Per bank write bursts -system.physmem.perBankRdBursts::4 65920 # Per bank write bursts -system.physmem.perBankRdBursts::5 70505 # Per bank write bursts -system.physmem.perBankRdBursts::6 65125 # Per bank write bursts -system.physmem.perBankRdBursts::7 71371 # Per bank write bursts -system.physmem.perBankRdBursts::8 68061 # Per bank write bursts -system.physmem.perBankRdBursts::9 95897 # Per bank write bursts -system.physmem.perBankRdBursts::10 65782 # Per bank write bursts -system.physmem.perBankRdBursts::11 68970 # Per bank write bursts -system.physmem.perBankRdBursts::12 60174 # Per bank write bursts -system.physmem.perBankRdBursts::13 71971 # Per bank write bursts -system.physmem.perBankRdBursts::14 71235 # Per bank write bursts -system.physmem.perBankRdBursts::15 71186 # Per bank write bursts -system.physmem.perBankWrBursts::0 81261 # Per bank write bursts -system.physmem.perBankWrBursts::1 86034 # Per bank write bursts -system.physmem.perBankWrBursts::2 81926 # Per bank write bursts -system.physmem.perBankWrBursts::3 83311 # Per bank write bursts -system.physmem.perBankWrBursts::4 82546 # Per bank write bursts -system.physmem.perBankWrBursts::5 86081 # Per bank write bursts -system.physmem.perBankWrBursts::6 81799 # Per bank write bursts -system.physmem.perBankWrBursts::7 86537 # Per bank write bursts -system.physmem.perBankWrBursts::8 86254 # Per bank write bursts -system.physmem.perBankWrBursts::9 89944 # Per bank write bursts -system.physmem.perBankWrBursts::10 82817 # Per bank write bursts -system.physmem.perBankWrBursts::11 84554 # Per bank write bursts -system.physmem.perBankWrBursts::12 78968 # Per bank write bursts -system.physmem.perBankWrBursts::13 86566 # Per bank write bursts -system.physmem.perBankWrBursts::14 86628 # Per bank write bursts -system.physmem.perBankWrBursts::15 86327 # Per bank write bursts +system.physmem.perBankRdBursts::0 74308 # Per bank write bursts +system.physmem.perBankRdBursts::1 87985 # Per bank write bursts +system.physmem.perBankRdBursts::2 79775 # Per bank write bursts +system.physmem.perBankRdBursts::3 80704 # Per bank write bursts +system.physmem.perBankRdBursts::4 79279 # Per bank write bursts +system.physmem.perBankRdBursts::5 87661 # Per bank write bursts +system.physmem.perBankRdBursts::6 78349 # Per bank write bursts +system.physmem.perBankRdBursts::7 78833 # Per bank write bursts +system.physmem.perBankRdBursts::8 69442 # Per bank write bursts +system.physmem.perBankRdBursts::9 78370 # Per bank write bursts +system.physmem.perBankRdBursts::10 69793 # Per bank write bursts +system.physmem.perBankRdBursts::11 81996 # Per bank write bursts +system.physmem.perBankRdBursts::12 80451 # Per bank write bursts +system.physmem.perBankRdBursts::13 82396 # Per bank write bursts +system.physmem.perBankRdBursts::14 80116 # Per bank write bursts +system.physmem.perBankRdBursts::15 88030 # Per bank write bursts +system.physmem.perBankWrBursts::0 92185 # Per bank write bursts +system.physmem.perBankWrBursts::1 101129 # Per bank write bursts +system.physmem.perBankWrBursts::2 94103 # Per bank write bursts +system.physmem.perBankWrBursts::3 97328 # Per bank write bursts +system.physmem.perBankWrBursts::4 94264 # Per bank write bursts +system.physmem.perBankWrBursts::5 99023 # Per bank write bursts +system.physmem.perBankWrBursts::6 94391 # Per bank write bursts +system.physmem.perBankWrBursts::7 95568 # Per bank write bursts +system.physmem.perBankWrBursts::8 90026 # Per bank write bursts +system.physmem.perBankWrBursts::9 95851 # Per bank write bursts +system.physmem.perBankWrBursts::10 88927 # Per bank write bursts +system.physmem.perBankWrBursts::11 96294 # Per bank write bursts +system.physmem.perBankWrBursts::12 94934 # Per bank write bursts +system.physmem.perBankWrBursts::13 97047 # Per bank write bursts +system.physmem.perBankWrBursts::14 95210 # Per bank write bursts +system.physmem.perBankWrBursts::15 100911 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 51513 # Number of times write queue was full causing retry -system.physmem.totGap 47384938876500 # Total gap between requests +system.physmem.numWrRetry 51774 # Number of times write queue was full causing retry +system.physmem.totGap 47341921675500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) -system.physmem.readPktSize::4 21333 # Read request sizes (log2) +system.physmem.readPktSize::4 2133 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1094573 # Read request sizes (log2) +system.physmem.readPktSize::6 1275744 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1351242 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 480312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 254385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 111988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 44885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 34371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 8446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1526901 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 505708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 298665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 136731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 85460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 55927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 46831 # 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What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see @@ -189,147 +189,147 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 36819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 42386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 51611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 56891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 68066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 74729 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 120772 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1035166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 152.526679 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.371009 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.170623 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 664281 64.17% 64.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 215041 20.77% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 59106 5.71% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 25397 2.45% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20542 1.98% 95.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11502 1.11% 96.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7604 0.73% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6193 0.60% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25500 2.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1035166 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 63814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.480459 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 70.581857 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 63808 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 63814 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 63814 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.179569 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.530322 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 597.849869 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-4095 63812 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 24179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 39999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 46492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 52355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 57811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 64510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 71167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 77564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 80217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 85971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 89992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 89616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 91327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 98798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 107236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 96475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 90527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 10742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 2040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 6171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 25276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 121442 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1170396 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 153.366156 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.854296 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 197.868960 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 748847 63.98% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 241823 20.66% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 67607 5.78% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 29756 2.54% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24374 2.08% 95.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14066 1.20% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9299 0.79% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7338 0.63% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 27286 2.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1170396 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 74463 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.155890 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 20.196232 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 74449 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 74463 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 74463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.509394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.370303 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 552.030208 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 74461 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 63814 # Writes before turning the bus around for reads -system.physmem.totQLat 67332860089 # Total ticks spent queuing -system.physmem.totMemAccLat 88248597589 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5577530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 60360.82 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 74463 # Writes before turning the bus around for reads +system.physmem.totQLat 79629370316 # Total ticks spent queuing +system.physmem.totMemAccLat 103582270316 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6387440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 62332.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 79110.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.51 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 81082.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.79 # Average write queue length when enqueuing -system.physmem.readRowHits 837889 # Number of row buffer hits during reads -system.physmem.writeRowHits 593994 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.95 # Row buffer hit rate for writes -system.physmem.avgGap 19186151.00 # Average gap between requests -system.physmem.pageHitRate 58.04 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3662384460 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1946584530 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3871522200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3494763900 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 31929318720.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 40834926540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1598586240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 62046559410 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 43455299520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11294770338285 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11487626755995 # Total energy per rank (pJ) -system.physmem_0.averagePower 242.432018 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47291190900816 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 2771331378 # Time in different power states -system.physmem_0.memoryStateTime::REF 13558872000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 47041958774500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 113164787559 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77419210306 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 136067479257 # Time in different power states -system.physmem_1.actEnergy 3728772180 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1981870440 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4093190640 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3560342760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33599910240.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 42188393820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1621939680 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 66725147910 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 45519792000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11290481164380 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11493516343440 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.556311 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47288162727367 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 2732090205 # Time in different power states -system.physmem_1.memoryStateTime::REF 14267508000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 47023294872500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 118540781222 # Time in different power states -system.physmem_1.memoryStateTime::ACT 79778077178 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 146327125895 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.physmem.readRowHits 958718 # Number of row buffer hits during reads +system.physmem.writeRowHits 675564 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 44.23 # Row buffer hit rate for writes +system.physmem.avgGap 16863400.13 # Average gap between requests +system.physmem.pageHitRate 58.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4260723600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2264628300 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4618823160 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4008913020 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 30164687280.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 41855751510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1419463680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 63813765750 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 36794590560 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11286440815140 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11475654576000 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.399417 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47246408217619 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 2341242543 # Time in different power states +system.physmem_0.memoryStateTime::REF 12803196000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 47010648524500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 95818811721 # Time in different power states +system.physmem_0.memoryStateTime::ACT 80368685838 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 139942793398 # Time in different power states +system.physmem_1.actEnergy 4095910980 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2177024520 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4502441160 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3963024000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 30680370240.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 42163353720 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1422051360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 64060335210 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 38109219360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11285470021935 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11476656465255 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.420579 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47245728134436 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2323672783 # Time in different power states +system.physmem_1.memoryStateTime::REF 13022950000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 47006002235750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 99242546502 # Time in different power states +system.physmem_1.memoryStateTime::ACT 80848444531 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 140483404434 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -356,30 +356,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 139151101 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91634411 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6732234 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 97916993 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 61670085 # Number of BTB hits +system.cpu0.branchPred.lookups 135771616 # Number of BP lookups +system.cpu0.branchPred.condPredicted 86347947 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6838936 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 91129477 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 54316721 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 62.982005 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 19220371 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 194045 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4187621 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2676103 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1511518 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 384250 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 59.603899 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20002366 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 187416 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4394152 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2878401 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1515751 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 382217 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -409,89 +409,88 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 608743 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 608743 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13705 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96942 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 292908 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 315835 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2627.591939 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 15089.582893 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 312900 99.07% 99.07% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 2131 0.67% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 548 0.17% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 139 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 23 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 315835 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 324732 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22165.202382 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18853.631715 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 18861.810606 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 320100 98.57% 98.57% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3009 0.93% 99.50% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 694 0.21% 99.71% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 681 0.21% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 132 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 68 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 19 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 324732 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 522550016344 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.577122 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.559179 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 521035310844 99.71% 99.71% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 819753000 0.16% 99.87% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 323762500 0.06% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 144297000 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 115791000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 61783500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 19805000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 28515500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 990500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 522550016344 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 96943 87.61% 87.61% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 13705 12.39% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 110648 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 608743 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 656993 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 656993 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15295 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 109934 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 315620 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 341373 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2464.513889 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14057.964276 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 338378 99.12% 99.12% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 2127 0.62% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 591 0.17% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 168 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 341373 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 358442 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21996.103972 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18865.832829 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 18729.819330 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 353579 98.64% 98.64% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3217 0.90% 99.54% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 596 0.17% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 697 0.19% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 228 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 358442 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 470936013252 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.670912 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.545830 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 469324214752 99.66% 99.66% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 904884000 0.19% 99.85% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 330855500 0.07% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 151555000 0.03% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 116006500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 57420000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 24613500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 25389500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 1013500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 61000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 470936013252 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 109934 87.79% 87.79% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 15295 12.21% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 125229 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656993 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 608743 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110648 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656993 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 125229 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110648 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 719391 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 125229 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 782222 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 101564011 # DTB read hits -system.cpu0.dtb.read_misses 439385 # DTB read misses -system.cpu0.dtb.write_hits 82403711 # DTB write hits -system.cpu0.dtb.write_misses 169358 # DTB write misses -system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 107772870 # DTB read hits +system.cpu0.dtb.read_misses 484010 # DTB read misses +system.cpu0.dtb.write_hits 87417439 # DTB write hits +system.cpu0.dtb.write_misses 172983 # DTB write misses +system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 43119 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 431 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7683 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 44511 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 282 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7018 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 39881 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 102003396 # DTB read accesses -system.cpu0.dtb.write_accesses 82573069 # DTB write accesses +system.cpu0.dtb.perms_faults 39566 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 108256880 # DTB read accesses +system.cpu0.dtb.write_accesses 87590422 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 183967722 # DTB hits -system.cpu0.dtb.misses 608743 # DTB misses -system.cpu0.dtb.accesses 184576465 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 195190309 # DTB hits +system.cpu0.dtb.misses 656993 # DTB misses +system.cpu0.dtb.accesses 195847302 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -521,1187 +520,1194 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 85247 # Table walker walks requested -system.cpu0.itb.walker.walksLong 85247 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1031 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58619 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10594 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 74653 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1640.215397 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 15358.310447 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-65535 74120 99.29% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-131071 439 0.59% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-196607 37 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-262143 19 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-327679 10 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-393215 2 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::524288-589823 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::589824-655359 19 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 74653 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 70244 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 27495.914242 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23588.322709 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 27529.617952 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 67750 96.45% 96.45% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1764 2.51% 98.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 417 0.59% 99.55% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 170 0.24% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 48 0.07% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 42 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 26 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 70244 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 419443065740 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.871284 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.335229 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 54034549916 12.88% 12.88% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 365365302324 87.11% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 40992500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 2004000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 217000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 419443065740 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58619 98.27% 98.27% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1031 1.73% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 59650 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 88518 # Table walker walks requested +system.cpu0.itb.walker.walksLong 88518 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 982 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60760 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10909 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 77609 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1509.006687 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 11301.495781 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-65535 77034 99.26% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-131071 519 0.67% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-196607 33 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-393215 8 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 77609 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72651 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 27149.240891 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23393.498423 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 24986.363412 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 70103 96.49% 96.49% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1723 2.37% 98.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 517 0.71% 99.58% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 199 0.27% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 35 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 72651 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 367854316648 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.912736 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.282646 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 32141827252 8.74% 8.74% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 335673383896 91.25% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 36841000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 2085000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 179500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 367854316648 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 60760 98.41% 98.41% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 982 1.59% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 61742 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85247 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85247 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88518 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88518 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59650 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59650 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 144897 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 219469803 # ITB inst hits -system.cpu0.itb.inst_misses 85247 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61742 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61742 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 150260 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 209275517 # ITB inst hits +system.cpu0.itb.inst_misses 88518 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 31398 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 31869 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 204530 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 214657 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 219555050 # ITB inst accesses -system.cpu0.itb.hits 219469803 # DTB hits -system.cpu0.itb.misses 85247 # DTB misses -system.cpu0.itb.accesses 219555050 # DTB accesses -system.cpu0.numPwrStateTransitions 27212 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13606 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3453780783.684036 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 93985708249.621262 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3589 26.38% 26.38% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9986 73.39% 99.77% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 6914083139000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13606 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 392799112195 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46992141342805 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 785608211 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 209364035 # ITB inst accesses +system.cpu0.itb.hits 209275517 # DTB hits +system.cpu0.itb.misses 88518 # DTB misses +system.cpu0.itb.accesses 209364035 # DTB accesses +system.cpu0.numPwrStateTransitions 11060 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 5530 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 8500198165.069259 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 152149510782.295166 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 4198 75.91% 75.91% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1307 23.63% 99.55% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.66% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.71% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 12 0.22% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 6914082541000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 5530 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 335827401167 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 47006095852833 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 671656145 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 89154333 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 616347679 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 139151101 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 83566559 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 651741352 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14592652 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2033431 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 298378 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6056906 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 755254 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 834704 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 219265865 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1675112 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 28029 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 758170684 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.951385 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.212910 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 89746186 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 605326172 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 135771616 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 77197488 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 539879458 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14767666 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2125862 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 314132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6298223 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 772099 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 851881 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 209041727 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1674502 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 29298 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 647371674 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.105525 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.248840 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 412487393 54.41% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 134584185 17.75% 72.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 46569297 6.14% 78.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 164529809 21.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 308576951 47.67% 47.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 127594651 19.71% 67.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 45508982 7.03% 74.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 165691090 25.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 758170684 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.177125 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.784548 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 107249627 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 379334150 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 227390625 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 38947644 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5248638 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19981467 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2087891 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 636989334 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23191131 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5248638 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 143394034 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 56142021 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 253850770 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 229681319 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 69853902 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 619319594 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6178554 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10862186 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 388792 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 930621 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 33162716 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11693 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 591176589 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 957415604 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 731049781 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 649204 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 532948721 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 58227868 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16256269 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14199870 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 78279720 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 101593087 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 85666218 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9630459 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8075180 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 596126359 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16460453 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 601474893 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2699291 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54684336 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 35421563 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 283328 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 758170684 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.793324 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.057959 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 647371674 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.202145 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.901244 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 102332613 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 273941666 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 237936691 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 27831297 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5329407 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 50359670 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2095113 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 630187004 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23557218 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5329407 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 133079950 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 61214716 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 153180346 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 234286149 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 60281106 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 612391061 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6345537 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 11623022 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 442390 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 950471 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 35105207 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 13004 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 561787552 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 866106072 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 720689595 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 706575 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 502207885 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 59579653 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 6816633 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 4684361 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 58564314 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 107690406 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90791382 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 10221267 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8541253 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 598417989 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 7027379 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 594218555 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2775784 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 55969109 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 36418491 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 281604 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 647371674 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.917894 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.123620 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 428799597 56.56% 56.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 139371286 18.38% 74.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 115828942 15.28% 90.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 66243104 8.74% 98.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7922364 1.04% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5391 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 341377364 52.73% 52.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 105270736 16.26% 68.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 121758490 18.81% 87.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 70435170 10.88% 98.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8524242 1.32% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5671 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 758170684 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 647371674 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 61955212 45.30% 45.30% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 62513 0.05% 45.34% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 16729 0.01% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 21 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 36421436 26.63% 71.99% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 37996782 27.78% 99.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 31053 0.02% 99.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 287360 0.21% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 65687551 45.22% 45.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 64582 0.04% 45.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 15638 0.01% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 12 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 38738584 26.67% 71.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 40389693 27.81% 99.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 34528 0.02% 99.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 315988 0.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 30 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 411361741 68.39% 68.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1567778 0.26% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 78948 0.01% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMisc 39915 0.01% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 104723474 17.41% 86.08% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 83352955 13.86% 99.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 49350 0.01% 99.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 300687 0.05% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 70 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 392733469 66.09% 66.09% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1547002 0.26% 66.35% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 82083 0.01% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 53 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 15 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 25 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 42153 0.01% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 111068257 18.69% 85.07% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88363067 14.87% 99.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 53874 0.01% 99.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 328485 0.06% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 601474893 # Type of FU issued -system.cpu0.iq.rate 0.765617 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 136771106 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.227393 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2099488112 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 667007258 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 583889559 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1102755 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 413748 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 385073 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 737537568 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 708401 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2768605 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 594218555 # Type of FU issued +system.cpu0.iq.rate 0.884706 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 145246576 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.244433 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1982627676 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 661129837 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 575942513 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1203467 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 445947 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 420205 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 738689926 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 775135 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2992085 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12684669 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17846 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 151274 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5522197 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13179956 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 18072 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 162311 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5715015 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2796342 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4797484 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3005258 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4976098 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5248638 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8055865 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1895421 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 612718172 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5329407 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8694006 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1907824 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 605581185 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 101593087 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 85666218 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13907446 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 58112 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1764578 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 151274 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1949210 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3085558 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5034768 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 593488019 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 101560351 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7385409 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 107690406 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90791382 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 4430701 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 69738 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1753830 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 162311 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2018069 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3124602 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5142671 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 586012257 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 107766715 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7557397 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 131360 # number of nop insts executed -system.cpu0.iew.exec_refs 183963466 # number of memory reference insts executed -system.cpu0.iew.exec_branches 111638269 # Number of branches executed -system.cpu0.iew.exec_stores 82403115 # Number of stores executed -system.cpu0.iew.exec_rate 0.755450 # Inst execution rate -system.cpu0.iew.wb_sent 585082868 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 584274632 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 284506732 # num instructions producing a value -system.cpu0.iew.wb_consumers 466304278 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.743723 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.610131 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 47796807 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16177125 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4684546 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 749065087 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.744798 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.551758 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 135817 # number of nop insts executed +system.cpu0.iew.exec_refs 195183772 # number of memory reference insts executed +system.cpu0.iew.exec_branches 107644173 # Number of branches executed +system.cpu0.iew.exec_stores 87417057 # Number of stores executed +system.cpu0.iew.exec_rate 0.872488 # Inst execution rate +system.cpu0.iew.wb_sent 577164047 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 576362718 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 283557258 # num instructions producing a value +system.cpu0.iew.wb_consumers 461921851 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.858122 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.613864 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 48922079 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 6745775 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4784510 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 638061728 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.861165 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.699392 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 504468440 67.35% 67.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 127495809 17.02% 84.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 53846196 7.19% 91.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 17894232 2.39% 93.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 12874355 1.72% 95.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8922431 1.19% 96.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5996417 0.80% 97.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3594154 0.48% 98.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13973053 1.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 421096864 66.00% 66.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 93116977 14.59% 80.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 56739989 8.89% 89.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18882229 2.96% 92.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13609968 2.13% 94.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9457933 1.48% 96.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6466471 1.01% 97.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3826133 0.60% 97.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14865164 2.33% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 749065087 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 475226157 # Number of instructions committed -system.cpu0.commit.committedOps 557902476 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 638061728 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 461890383 # Number of instructions committed +system.cpu0.commit.committedOps 549476248 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 169052439 # Number of memory references committed -system.cpu0.commit.loads 88908418 # Number of loads committed -system.cpu0.commit.membars 3969625 # Number of memory barriers committed -system.cpu0.commit.branches 106090436 # Number of branches committed -system.cpu0.commit.fp_insts 377224 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 511981133 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14308761 # Number of function calls committed. +system.cpu0.commit.refs 179586814 # Number of memory references committed +system.cpu0.commit.loads 94510447 # Number of loads committed +system.cpu0.commit.membars 4189650 # Number of memory barriers committed +system.cpu0.commit.branches 102007560 # Number of branches committed +system.cpu0.commit.fp_insts 412941 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 511246578 # Number of committed integer instructions. +system.cpu0.commit.function_calls 15004572 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 387443640 69.45% 69.45% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1310567 0.23% 69.68% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 61901 0.01% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 33929 0.01% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 88862033 15.93% 85.63% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 79847111 14.31% 99.94% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemRead 46385 0.01% 99.95% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemWrite 296910 0.05% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 368489017 67.06% 67.06% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1298564 0.24% 67.30% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 64848 0.01% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 8 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 13 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 21 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 36963 0.01% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 94459041 17.19% 84.51% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84751837 15.42% 99.93% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 51406 0.01% 99.94% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 324530 0.06% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 557902476 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13973053 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1336174255 # The number of ROB reads -system.cpu0.rob.rob_writes 1220466867 # The number of ROB writes -system.cpu0.timesIdled 1005352 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27437527 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93984272695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 475226157 # Number of Instructions Simulated -system.cpu0.committedOps 557902476 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.653125 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.653125 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.604915 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.604915 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 700618930 # number of integer regfile reads -system.cpu0.int_regfile_writes 416450651 # number of integer regfile writes -system.cpu0.fp_regfile_reads 634669 # number of floating regfile reads -system.cpu0.fp_regfile_writes 293776 # number of floating regfile writes -system.cpu0.cc_regfile_reads 128889270 # number of cc regfile reads -system.cpu0.cc_regfile_writes 129563151 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1347671553 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16172806 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6286438 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.582319 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 156315528 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6286950 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 24.863492 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 2049282000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.582319 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946450 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.946450 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 549476248 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14865164 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1217272285 # The number of ROB reads +system.cpu0.rob.rob_writes 1206069871 # The number of ROB writes +system.cpu0.timesIdled 983506 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24284471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 94012190405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 461890383 # Number of Instructions Simulated +system.cpu0.committedOps 549476248 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.454146 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.454146 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.687689 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.687689 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 689648120 # number of integer regfile reads +system.cpu0.int_regfile_writes 419367317 # number of integer regfile writes +system.cpu0.fp_regfile_reads 692130 # number of floating regfile reads +system.cpu0.fp_regfile_writes 320584 # number of floating regfile writes +system.cpu0.cc_regfile_reads 105285978 # number of cc regfile reads +system.cpu0.cc_regfile_writes 105978286 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1168751660 # number of misc regfile reads +system.cpu0.misc_regfile_writes 6863582 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6620968 # number of replacements +system.cpu0.dcache.tags.tagsinuse 481.361219 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 165967454 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6621480 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.065009 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 204144000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.361219 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940159 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.940159 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 433 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 351060755 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 351060755 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 82089512 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 82089512 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69232216 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69232216 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209823 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 209823 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 173405 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 173405 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1868090 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1868090 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1930069 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1930069 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 151495133 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 151495133 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 151704956 # number of overall hits -system.cpu0.dcache.overall_hits::total 151704956 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7010414 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7010414 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7797174 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7797174 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 751824 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 751824 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 805427 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 805427 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 284725 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 284725 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 186829 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 186829 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 15613015 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15613015 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 16364839 # number of overall misses -system.cpu0.dcache.overall_misses::total 16364839 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112159926000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 112159926000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 158052575270 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 158052575270 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29573159898 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 29573159898 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4301491500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4301491500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4484661500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4484661500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2134500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2134500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 299785661168 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 299785661168 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 299785661168 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 299785661168 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 89099926 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 89099926 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77029390 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77029390 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 961647 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 961647 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 978832 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 978832 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2152815 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2152815 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2116898 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2116898 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 167108148 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 167108148 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 168069795 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 168069795 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078680 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.078680 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101223 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.101223 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781809 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781809 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822845 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822845 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132257 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132257 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088256 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088256 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.093431 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.093431 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097369 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097369 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15999.044564 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15999.044564 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20270.494832 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20270.494832 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36717.368424 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36717.368424 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15107.530073 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15107.530073 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24004.097330 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24004.097330 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 372530825 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 372530825 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 87044023 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 87044023 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73673205 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73673205 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 219185 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 219185 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 153997 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 153997 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2008223 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2008223 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2072988 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2072988 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 160871225 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 160871225 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 161090410 # number of overall hits +system.cpu0.dcache.overall_hits::total 161090410 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7470146 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7470146 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 8166848 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 8166848 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 789396 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 789396 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 800299 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 800299 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 307874 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 307874 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202740 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 202740 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 16437293 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 16437293 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 17226689 # number of overall misses +system.cpu0.dcache.overall_misses::total 17226689 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 120830384000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 120830384000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 166078687815 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 166078687815 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29848601951 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 29848601951 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4689476000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4689476000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4883927500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4883927500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2141000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2141000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 316757673766 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 316757673766 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 316757673766 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 316757673766 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 94514169 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 94514169 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81840053 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81840053 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1008581 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1008581 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954296 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 954296 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2316097 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2316097 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2275728 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2275728 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 177308518 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 177308518 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 178317099 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 178317099 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079037 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.079037 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099790 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.099790 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782680 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.782680 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.838628 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.838628 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132928 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132928 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089088 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089088 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092704 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092704 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096607 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096607 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16175.103405 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16175.103405 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20335.714319 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20335.714319 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37296.812755 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37296.812755 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15231.802621 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15231.802621 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24089.609845 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24089.609845 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19201.010258 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19201.010258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18318.888513 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18318.888513 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8999058 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 24447381 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 751224 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 774000 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.979194 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 31.585764 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6286527 # number of writebacks -system.cpu0.dcache.writebacks::total 6286527 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3589298 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3589298 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6265824 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6265824 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4129 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4129 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 147493 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 147493 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9859251 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9859251 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9859251 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9859251 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3421116 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3421116 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1531350 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1531350 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 745052 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 745052 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801298 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 801298 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 137232 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137232 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 186825 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 186825 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5753764 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5753764 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6498816 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6498816 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29615 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29691 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59306 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51678055000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51678055000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34197879948 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34197879948 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17704904500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17704904500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28602356899 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28602356899 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1885182000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1885182000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4297888500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4297888500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2082500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2082500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 114478291847 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 114478291847 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132183196347 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 132183196347 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5594868000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5594868000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5594868000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5594868000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038396 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038396 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019880 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019880 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774767 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774767 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.818627 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.818627 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063745 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063745 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088254 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088254 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034431 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034431 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038667 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.038667 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15105.613198 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15105.613198 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22331.850947 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22331.850947 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23763.313836 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23763.313836 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35695.030936 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35695.030936 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13737.189577 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13737.189577 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23004.889603 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23004.889603 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19270.671501 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19270.671501 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18387.612023 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18387.612023 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9058407 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 25757393 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 741437 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 811492 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.217366 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 31.740785 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 6621095 # number of writebacks +system.cpu0.dcache.writebacks::total 6621095 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3832878 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3832878 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6557291 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6557291 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4455 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4455 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 156975 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 156975 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 10394624 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 10394624 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 10394624 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 10394624 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3637268 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3637268 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1609557 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1609557 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 782554 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 782554 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 795844 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 795844 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 150899 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 150899 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202732 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 202732 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 6042669 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 6042669 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6825223 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6825223 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15843 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17283 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 33126 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 55872486000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 55872486000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 35889720367 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 35889720367 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18736140000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18736140000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28877247951 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28877247951 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2069296000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2069296000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4681247500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4681247500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2089000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2089000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 120639454318 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 120639454318 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 139375594318 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 139375594318 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897214000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897214000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2897214000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2897214000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038484 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038484 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775896 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775896 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.833959 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.833959 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065152 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065152 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089084 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089084 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034080 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034080 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038276 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.038276 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15361.113341 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15361.113341 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22297.887162 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22297.887162 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23942.296634 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23942.296634 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36285.060830 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36285.060830 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13713.119371 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13713.119371 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23090.816941 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23090.816941 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19896.243893 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19896.243893 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20339.581294 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20339.581294 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188920.074287 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188920.074287 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 94338.987624 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94338.987624 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5974428 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.960293 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 212911456 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5974940 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.634074 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13477910000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960293 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999922 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19964.597485 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19964.597485 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20420.665276 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20420.665276 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182870.289718 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182870.289718 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87460.423836 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87460.423836 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 6024041 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.980173 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 202652654 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6024553 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 33.637791 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 11640760000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.980173 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999961 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 293 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 444450377 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 444450377 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 212911456 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 212911456 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 212911456 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 212911456 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 212911456 # number of overall hits -system.cpu0.icache.overall_hits::total 212911456 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6326229 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6326229 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6326229 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6326229 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6326229 # number of overall misses -system.cpu0.icache.overall_misses::total 6326229 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70930890398 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 70930890398 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 70930890398 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 70930890398 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 70930890398 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 70930890398 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 219237685 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 219237685 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 219237685 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 219237685 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 219237685 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 219237685 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028856 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028856 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028856 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028856 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028856 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028856 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11212.191402 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11212.191402 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11212.191402 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11212.191402 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11212.191402 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11212.191402 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10513720 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1665 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 740505 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.198041 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 128.076923 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5974428 # number of writebacks -system.cpu0.icache.writebacks::total 5974428 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351221 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 351221 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 351221 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 351221 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 351221 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 351221 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5975008 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5975008 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5975008 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5975008 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5975008 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5975008 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 63931230447 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 63931230447 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 63931230447 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 63931230447 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 63931230447 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 63931230447 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2027158498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 2027158498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027254 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027254 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027254 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10699.773196 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10699.773196 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10699.773196 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8714333 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8724211 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 8793 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.tags.tag_accesses 424090067 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 424090067 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 202652654 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 202652654 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 202652654 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 202652654 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 202652654 # number of overall hits +system.cpu0.icache.overall_hits::total 202652654 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6379961 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6379961 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6379961 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6379961 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6379961 # number of overall misses +system.cpu0.icache.overall_misses::total 6379961 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71606822648 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 71606822648 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 71606822648 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 71606822648 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 71606822648 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 71606822648 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 209032615 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 209032615 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 209032615 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 209032615 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 209032615 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 209032615 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030521 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.030521 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030521 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.030521 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030521 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.030521 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11223.708522 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11223.708522 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11223.708522 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11223.708522 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10553176 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 2682 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 731110 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.434457 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 243.818182 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 6024041 # number of writebacks +system.cpu0.icache.writebacks::total 6024041 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355124 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 355124 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 355124 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 355124 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 355124 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 355124 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6024837 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6024837 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6024837 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6024837 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6024837 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6024837 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 2093 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 2093 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64522792922 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 64522792922 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64522792922 # 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Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 268.450517 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.947223 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002052 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001174 # Average percentage of cache occupancy +system.cpu0.l2cache.prefetcher.pfSpanPage 1224644 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2885626 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15865.684381 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 11160732 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2901096 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.847074 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 512573000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15504.354139 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.001688 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 17.597153 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000007 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 313.731394 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.946311 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001831 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001074 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016385 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.966835 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 381 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14929 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 75 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 118 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 93 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 95 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 69 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.019149 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.968365 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 318 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 120 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 81 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 114 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 37 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 499 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1082 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5719 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5657 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1972 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.023254 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.911194 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 427199165 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 427199165 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # 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number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 602660 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 185799 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5386829 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4241826 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10417114 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 25200 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12620 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 37820 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 257381 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 257381 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 186815 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 186815 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2178 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7928 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2613 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2218 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019409 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 441303495 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 441303495 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 661323 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 192664 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 853987 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4337132 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4337132 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 8306124 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 8306124 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 35 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1063752 # 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number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 661323 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 192664 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5420251 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 4515209 # number of overall hits +system.cpu0.l2cache.overall_hits::total 10789447 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 24436 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12223 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 36659 # number of ReadReq misses +system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses +system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 266353 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 266353 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202724 # 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number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2769951000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 2955481000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.040548 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999876 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999876 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999973 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999973 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999869 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999869 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999985 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999985 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213971 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213971 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098432 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.241664 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241664 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.771029 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.771029 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235307 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156576 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235307 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.195572 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.195572 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100281 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.243030 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243030 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.779439 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.779439 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156971 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230440 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33826.797210 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 62512.865639 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18642.512439 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18642.512439 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15488.103172 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15488.103172 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338200 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338200 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 49922.328195 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 49922.328195 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31976.977722 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35008.457299 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35008.457299 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35079.711207 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35079.711207 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38121.219028 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36174.979696 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38121.219028 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44617.169730 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180904.136417 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141921.426888 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 90336.154858 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89640.516632 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 25418604 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13061865 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 690419 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 690321 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 98 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 966476 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11336947 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 29691 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 29691 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5857040 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8164049 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1344034 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1151380 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 469212 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 335795 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 509398 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1315239 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1289150 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5975008 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5298799 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 872203 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 802449 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17966980 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20229549 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 416579 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1325266 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 39938374 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 765101392 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 766341777 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1587352 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5022880 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1538053401 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5977120 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 119917960 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 19518051 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.053731 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.225509 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231066 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35519.009248 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69685.737512 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18689.969694 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18689.969694 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15574.182095 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15574.182095 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 339699.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 339699.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53111.575687 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53111.575687 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31515.273152 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35793.164971 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35793.164971 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35483.491366 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35483.491366 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36778.321675 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47330.602445 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174837.530771 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164779.270740 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83618.637928 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83917.232176 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 26242800 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13504787 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 4079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 709472 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 709425 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 47 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 1004788 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11688716 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 17283 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 17283 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 6246434 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8308001 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1424808 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1208828 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 455562 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363537 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 533487 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1384860 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1359346 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6024837 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5574197 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 855548 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 797069 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18077450 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21220350 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 431264 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1446232 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 41175296 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 771132816 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 809027527 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1639096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5486072 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1587285511 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6254740 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 129367088 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 20223636 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.054517 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.227045 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 18469421 94.63% 94.63% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 1048532 5.37% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 98 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 19121152 94.55% 94.55% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 1102437 5.45% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 47 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 19518051 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 25305808947 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 20223636 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 26091767715 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 186983903 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 182386585 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 8989974042 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9045827975 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9049403091 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9544267214 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 218640527 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 226891962 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 698295209 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 761324284 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 130931248 # Number of BP lookups -system.cpu1.branchPred.condPredicted 87112041 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6567659 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91792654 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 56129151 # Number of BTB hits +system.cpu1.branchPred.lookups 124325317 # Number of BP lookups +system.cpu1.branchPred.condPredicted 79272164 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6778632 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 83479161 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 47841396 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 61.147759 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17311793 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 174850 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4346649 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2655837 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1690812 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 417178 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 57.309388 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17874464 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 195085 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4411145 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2666966 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1744179 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 432386 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1731,88 +1737,88 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 551219 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 551219 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11436 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86181 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 255688 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 295531 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2259.422869 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13315.556253 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 293454 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1395 0.47% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 424 0.14% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 158 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 50 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 38 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 295531 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 283173 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21265.600887 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18470.492322 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14814.339876 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 281324 99.35% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1404 0.50% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 195 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 146 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 27 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 13 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 283173 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 475307081088 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.614132 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.549956 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 474122952588 99.75% 99.75% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 603814500 0.13% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 247441500 0.05% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 130616500 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 93327500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 62495500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 19627500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 26354000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 445000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 475307081088 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 86181 88.28% 88.28% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11436 11.72% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 97617 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 551219 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 580775 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 580775 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12302 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93041 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 266909 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 313866 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2454.023373 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13953.006998 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 311371 99.21% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1689 0.54% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 507 0.16% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 189 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 54 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 44 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 313866 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 295327 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 21717.315044 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.510143 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 17673.432878 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 292731 99.12% 99.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1780 0.60% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 365 0.12% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 243 0.08% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 66 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 35 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 14 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 295327 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 389340230128 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.666551 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.555298 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 388038620628 99.67% 99.67% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 674944000 0.17% 99.84% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 273419500 0.07% 99.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 140502000 0.04% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 100194000 0.03% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 59021000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 22755500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 30241000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 482500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 50000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 389340230128 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 93042 88.32% 88.32% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 12302 11.68% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 105344 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 580775 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 551219 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97617 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 580775 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105344 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97617 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 648836 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105344 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 686119 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 95947338 # DTB read hits -system.cpu1.dtb.read_misses 376138 # DTB read misses -system.cpu1.dtb.write_hits 79464123 # DTB write hits -system.cpu1.dtb.write_misses 175081 # DTB write misses -system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 97816184 # DTB read hits +system.cpu1.dtb.read_misses 397931 # DTB read misses +system.cpu1.dtb.write_hits 81264416 # DTB write hits +system.cpu1.dtb.write_misses 182844 # DTB write misses +system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35142 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 372 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6075 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36337 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7662 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 39563 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 96323476 # DTB read accesses -system.cpu1.dtb.write_accesses 79639204 # DTB write accesses +system.cpu1.dtb.perms_faults 41901 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 98214115 # DTB read accesses +system.cpu1.dtb.write_accesses 81447260 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 175411461 # DTB hits -system.cpu1.dtb.misses 551219 # DTB misses -system.cpu1.dtb.accesses 175962680 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 179080600 # DTB hits +system.cpu1.dtb.misses 580775 # DTB misses +system.cpu1.dtb.accesses 179661375 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1842,1180 +1848,1175 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 82567 # Table walker walks requested -system.cpu1.itb.walker.walksLong 82567 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 985 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60088 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9957 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 72610 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 937.467291 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 7808.036609 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 72461 99.79% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 121 0.17% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 15 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 72610 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71030 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24890.468816 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22675.930059 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19295.215598 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70173 98.79% 98.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 554 0.78% 99.57% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 204 0.29% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 8 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 25 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71030 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 397994478260 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.871343 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.334985 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 51225264788 12.87% 12.87% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 346750110472 87.12% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 17741500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1276000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 85500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 397994478260 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 60088 98.39% 98.39% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 985 1.61% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 61073 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 87135 # Table walker walks requested +system.cpu1.itb.walker.walksLong 87135 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1092 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62581 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 10397 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 76738 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1034.422320 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 9201.232348 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 76494 99.68% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 186 0.24% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 34 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 76738 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 74070 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25472.262724 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22851.948587 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 20227.385308 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 72813 98.30% 98.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 775 1.05% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 316 0.43% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.12% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 74070 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 329207699984 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.888226 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.315322 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 36820179964 11.18% 11.18% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 292365319520 88.81% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 21267000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 903500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 30000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 329207699984 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 62581 98.28% 98.28% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1092 1.72% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63673 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82567 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82567 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 87135 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 87135 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61073 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61073 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 143640 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 204871540 # ITB inst hits -system.cpu1.itb.inst_misses 82567 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63673 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63673 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 150808 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 190777093 # ITB inst hits +system.cpu1.itb.inst_misses 87135 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 24862 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25727 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205327 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 222647 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 204954107 # ITB inst accesses -system.cpu1.itb.hits 204871540 # DTB hits -system.cpu1.itb.misses 82567 # DTB misses -system.cpu1.itb.accesses 204954107 # DTB accesses -system.cpu1.numPwrStateTransitions 10338 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 5169 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9100042413.076223 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 142913287882.442078 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3563 68.93% 68.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1580 30.57% 99.50% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.10% 99.63% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.04% 99.67% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.27% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 190864228 # ITB inst accesses +system.cpu1.itb.hits 190777093 # DTB hits +system.cpu1.itb.misses 87135 # DTB misses +system.cpu1.itb.accesses 190864228 # DTB accesses +system.cpu1.numPwrStateTransitions 27368 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 13684 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3437541610.585575 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 87855050570.390015 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3277 23.95% 23.95% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10379 75.85% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7390880676264 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 5169 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 346821221809 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47038119233191 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 693644050 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 7351150614736 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 13684 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 302603854747 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47039319399253 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 605218102 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 87527745 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 578391241 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 130931248 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 76096781 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 569305331 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 14062296 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1768387 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 291884 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5735168 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 727906 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 800824 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 204645173 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1664411 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 27214 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 673188393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.008077 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.227099 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 90677216 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 553360207 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 124325317 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 68382826 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 474472155 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 14605284 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1912826 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 316489 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6235887 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 776312 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 869780 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 190532631 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1731041 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28903 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 582563307 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.126942 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.253057 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 348457754 51.76% 51.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 126514971 18.79% 70.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 42536092 6.32% 76.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 155679576 23.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 272142185 46.71% 46.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 117259342 20.13% 66.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 40229436 6.91% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 152932344 26.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 673188393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.188759 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.833844 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 102787429 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 312284706 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 218180532 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 34930241 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5005485 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18306368 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2064498 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 600925596 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22793962 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5005485 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 136395689 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 44912882 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 210797905 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 219085305 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 56991127 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 584399745 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 6001663 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9489847 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 242679 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 273258 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 24369803 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 10662 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 555653486 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 898470064 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 689649249 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 841085 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 500004101 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 55649379 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14907079 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13060204 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 70305418 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 96437745 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 82644936 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8695524 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7557089 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 562795340 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15022202 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 566786483 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2618124 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 52408988 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 33720273 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 259964 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 673188393 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.841943 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.073212 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 582563307 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.205422 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.914315 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 100710093 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 231252575 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 221227930 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 24164908 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5207801 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 44439760 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2135059 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 575305987 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 23412205 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5207801 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 129334574 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 47434760 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 137391497 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 216168101 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 47026574 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 558184675 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 6143864 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9881225 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 309237 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 251476 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 25589786 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 13193 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 510403185 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 786411891 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 655895321 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 811726 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 453487095 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 56916084 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 6219044 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 4304916 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 51458924 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 98128925 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 84474197 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8967706 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7764120 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 545083370 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6336595 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 540345314 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2650065 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 53579246 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 34592760 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 257601 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 582563307 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.927531 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.122571 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 363862102 54.05% 54.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 129787759 19.28% 73.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 109122281 16.21% 89.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 62914886 9.35% 98.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7497321 1.11% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4044 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 303220433 52.05% 52.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 97196070 16.68% 68.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 110913519 19.04% 87.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 63614426 10.92% 98.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7615367 1.31% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3492 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 673188393 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 582563307 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 57388953 44.23% 44.23% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 51651 0.04% 44.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 16856 0.01% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 103 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 34250281 26.40% 70.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 37595364 28.98% 99.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 47943 0.04% 99.70% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 388183 0.30% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 57271310 43.60% 43.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 51119 0.04% 43.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 18601 0.01% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 112 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 35025270 26.66% 70.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 38581798 29.37% 99.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 47664 0.04% 99.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 368619 0.28% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 385773007 68.06% 68.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1187343 0.21% 68.27% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 69773 0.01% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 13 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 27 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 84205 0.01% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 2 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 98926523 17.45% 85.75% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 80304665 14.17% 99.92% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 64060 0.01% 99.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 376846 0.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 76 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 355477037 65.79% 65.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1278002 0.24% 66.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 69863 0.01% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 79928 0.01% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 100880874 18.67% 84.72% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 82125393 15.20% 99.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 69486 0.01% 99.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 364646 0.07% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 566786483 # Type of FU issued -system.cpu1.iq.rate 0.817114 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 129739334 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.228903 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1937625833 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 629808815 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 550243700 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1492982 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 556682 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 518492 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 695564416 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 961390 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2525668 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 540345314 # Type of FU issued +system.cpu1.iq.rate 0.892811 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 131364493 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.243112 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1795817951 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 604594628 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 523100921 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1450540 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 543567 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 507957 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 670779267 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 930464 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2614124 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12072145 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16264 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 139965 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5400546 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 12461558 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 17016 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 140230 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5490502 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2506634 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3911021 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2570995 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4304841 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5005485 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6180671 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1541266 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 577948873 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 5207801 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6764064 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1538743 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 551558167 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 96437745 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 82644936 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12856669 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 62955 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1418771 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 139965 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1860771 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 3017279 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4878050 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 559031023 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 95939165 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 7216233 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 98128925 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 84474197 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 4043182 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 70701 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1397089 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 140230 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1929682 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 3114694 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5044376 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 532413736 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 97811900 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 7363284 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 131331 # number of nop insts executed -system.cpu1.iew.exec_refs 175402489 # number of memory reference insts executed -system.cpu1.iew.exec_branches 104887487 # Number of branches executed -system.cpu1.iew.exec_stores 79463324 # Number of stores executed -system.cpu1.iew.exec_rate 0.805934 # Inst execution rate -system.cpu1.iew.wb_sent 551451357 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 550762192 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 266030186 # num instructions producing a value -system.cpu1.iew.wb_consumers 436524752 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.794013 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.609427 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 45696838 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14762238 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4541996 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 664504904 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.790677 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.583374 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 138202 # number of nop insts executed +system.cpu1.iew.exec_refs 179076621 # number of memory reference insts executed +system.cpu1.iew.exec_branches 97312103 # Number of branches executed +system.cpu1.iew.exec_stores 81264721 # Number of stores executed +system.cpu1.iew.exec_rate 0.879706 # Inst execution rate +system.cpu1.iew.wb_sent 524373694 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 523608878 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 254758095 # num instructions producing a value +system.cpu1.iew.wb_consumers 415275761 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.865157 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.613467 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 46732947 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 6078994 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4683791 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 573586803 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.867943 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.693393 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 434201366 65.34% 65.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 119136384 17.93% 83.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 51278197 7.72% 90.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 17339439 2.61% 93.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 12299899 1.85% 95.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8244778 1.24% 96.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5665589 0.85% 97.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3433584 0.52% 98.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12905668 1.94% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 375218582 65.42% 65.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 85397429 14.89% 80.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 52348334 9.13% 89.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 17503204 3.05% 92.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12415456 2.16% 94.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8370820 1.46% 96.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5748485 1.00% 97.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3445775 0.60% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 13138718 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 664504904 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 446004136 # Number of instructions committed -system.cpu1.commit.committedOps 525408547 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 573586803 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 416374803 # Number of instructions committed +system.cpu1.commit.committedOps 497840712 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 161609989 # Number of memory references committed -system.cpu1.commit.loads 84365599 # Number of loads committed -system.cpu1.commit.membars 3561329 # Number of memory barriers committed -system.cpu1.commit.branches 99629625 # Number of branches committed -system.cpu1.commit.fp_insts 509948 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 482210935 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12864051 # Number of function calls committed. +system.cpu1.commit.refs 164651061 # Number of memory references committed +system.cpu1.commit.loads 85667366 # Number of loads committed +system.cpu1.commit.membars 3698541 # Number of memory barriers committed +system.cpu1.commit.branches 91988554 # Number of branches committed +system.cpu1.commit.fp_insts 499479 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 463071817 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13152854 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 362699186 69.03% 69.03% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 966499 0.18% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 55760 0.01% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 8 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 13 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 21 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 77071 0.01% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84306280 16.05% 85.29% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 76870874 14.63% 99.92% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemRead 59319 0.01% 99.93% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemWrite 373516 0.07% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 332017365 66.69% 66.69% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1043826 0.21% 66.90% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 55377 0.01% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 73083 0.01% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 85601974 17.19% 84.12% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 78622691 15.79% 99.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 65392 0.01% 99.93% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 361004 0.07% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 525408547 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12905668 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1219098786 # The number of ROB reads -system.cpu1.rob.rob_writes 1150856845 # The number of ROB writes -system.cpu1.timesIdled 925679 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 20455657 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94076236903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 446004136 # Number of Instructions Simulated -system.cpu1.committedOps 525408547 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.555241 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.555241 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.642987 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.642987 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 659945611 # number of integer regfile reads -system.cpu1.int_regfile_writes 391450025 # number of integer regfile writes -system.cpu1.fp_regfile_reads 826837 # number of floating regfile reads -system.cpu1.fp_regfile_writes 461620 # number of floating regfile writes -system.cpu1.cc_regfile_reads 120567774 # number of cc regfile reads -system.cpu1.cc_regfile_writes 121287073 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1215585693 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14957440 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5242137 # number of replacements -system.cpu1.dcache.tags.tagsinuse 459.717362 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 151071021 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5242649 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.815780 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8517875621500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.717362 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897885 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.897885 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 497840712 # Class of committed instruction +system.cpu1.commit.bw_lim_events 13138718 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1100782906 # The number of ROB reads +system.cpu1.rob.rob_writes 1098088032 # The number of ROB writes +system.cpu1.timesIdled 993023 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 22654795 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94078628435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 416374803 # Number of Instructions Simulated +system.cpu1.committedOps 497840712 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.453542 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.453542 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.687975 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.687975 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 625781479 # number of integer regfile reads +system.cpu1.int_regfile_writes 379830432 # number of integer regfile writes +system.cpu1.fp_regfile_reads 798661 # number of floating regfile reads +system.cpu1.fp_regfile_writes 473896 # number of floating regfile writes +system.cpu1.cc_regfile_reads 94918566 # number of cc regfile reads +system.cpu1.cc_regfile_writes 95638413 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1053266822 # number of misc regfile reads +system.cpu1.misc_regfile_writes 6252018 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5530000 # number of replacements +system.cpu1.dcache.tags.tagsinuse 456.074004 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 153151228 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5530512 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.692052 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8516003368500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.074004 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890770 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.890770 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 335085452 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 335085452 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 78683388 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 78683388 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 67788952 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 67788952 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181257 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 181257 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 140156 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 140156 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1756750 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1756750 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1770273 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1770273 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 146612496 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 146612496 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 146793753 # number of overall hits -system.cpu1.dcache.overall_hits::total 146793753 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6126313 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6126313 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6911292 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6911292 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 643081 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 643081 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 451908 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 451908 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 241040 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 241040 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 183733 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 183733 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13489513 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13489513 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14132594 # number of overall misses -system.cpu1.dcache.overall_misses::total 14132594 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 94548549000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 94548549000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 128933568944 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 128933568944 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10455217570 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10455217570 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3390405500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3390405500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4379858500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4379858500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2605000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2605000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 233937335514 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 233937335514 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 233937335514 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 233937335514 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 84809701 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 84809701 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 74700244 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 74700244 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 824338 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 824338 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 592064 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 592064 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1997790 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1997790 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1954006 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1954006 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 160102009 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 160102009 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 160926347 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 160926347 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072236 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.072236 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.092520 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.092520 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780118 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780118 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.763276 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.763276 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120653 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120653 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094029 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094029 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.084256 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.084256 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087820 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.087820 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15433.189424 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15433.189424 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18655.494363 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18655.494363 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23135.721364 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23135.721364 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14065.738052 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14065.738052 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23838.170062 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23838.170062 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 341526918 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 341526918 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 79602961 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 79602961 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68799990 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68799990 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187687 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 187687 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 159948 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 159948 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1827869 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1827869 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1836377 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1836377 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 148562899 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 148562899 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 148750586 # number of overall hits +system.cpu1.dcache.overall_hits::total 148750586 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6412648 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6412648 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7514708 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7514708 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 707982 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 707982 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 465981 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 465981 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 246351 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 246351 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195484 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 14393337 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 14393337 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 15101319 # number of overall misses +system.cpu1.dcache.overall_misses::total 15101319 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101710324000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 101710324000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138164152559 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 138164152559 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10841403957 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10841403957 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3505750500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3505750500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4668207500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4668207500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2827500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2827500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 250715880516 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 250715880516 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 250715880516 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 250715880516 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 86015609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 86015609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 76314698 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 76314698 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 895669 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 895669 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625929 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 625929 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074220 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2074220 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2031861 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2031861 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 162956236 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 162956236 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 163851905 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 163851905 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074552 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.074552 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098470 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.098470 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790450 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790450 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.744463 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.744463 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118768 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118768 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096209 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096209 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088326 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.088326 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092164 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.092164 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15860.893035 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15860.893035 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18385.831167 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18385.831167 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23265.763962 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23265.763962 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14230.713494 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14230.713494 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23880.253627 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23880.253627 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17342.163169 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17342.163169 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16553.035877 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16553.035877 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 2644851 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 20463296 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 369952 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 688434 # 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number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8695562 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8695562 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8695562 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8695562 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3012677 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3012677 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1333025 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1333025 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 643006 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 643006 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 448249 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 448249 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115972 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115972 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 183726 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 183726 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4793951 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4793951 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5436957 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5436957 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8871 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8871 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 8695 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17566 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17566 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42819104500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42819104500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26001782801 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26001782801 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14897861000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14897861000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9889085570 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9889085570 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1553813500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1553813500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4196193500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4196193500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2544000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2544000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78709972871 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 78709972871 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93607833871 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 93607833871 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1354957000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1354957000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1354957000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1354957000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035523 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035523 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017845 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017845 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780027 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780027 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.757096 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.757096 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058050 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058050 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094025 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094025 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029943 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029943 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033785 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033785 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14212.975536 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14212.975536 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19505.847828 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19505.847828 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23169.085514 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23169.085514 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22061.589808 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22061.589808 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13398.178008 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13398.178008 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22839.410318 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22839.410318 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17418.884899 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17418.884899 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16602.250473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16602.250473 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 2802154 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 21903502 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 386416 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 756136 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.251651 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.967675 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 5530029 # number of writebacks +system.cpu1.dcache.writebacks::total 5530029 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3294839 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3294839 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6084278 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 6084278 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3511 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3511 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 126189 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 126189 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9382628 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9382628 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9382628 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9382628 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3117809 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3117809 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1430430 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1430430 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 707901 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 707901 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462470 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 462470 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120162 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120162 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195479 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 195479 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 5010709 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 5010709 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5718610 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5718610 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22964 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 44370 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44191154500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44191154500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27737660597 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27737660597 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 17972389000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 17972389000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10263027957 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10263027957 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1602495500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1602495500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4472798500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4472798500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2757500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2757500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82191843054 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 82191843054 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 100164232054 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 100164232054 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4057567500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4057567500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4057567500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4057567500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036247 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036247 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018744 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018744 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790360 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790360 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738854 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738854 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057931 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057931 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096207 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096207 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030749 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030749 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034901 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034901 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14173.785020 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14173.785020 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19391.134552 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19391.134552 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 25388.280282 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 25388.280282 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22191.770184 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22191.770184 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13336.125397 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.125397 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.222535 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.222535 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16418.601874 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16418.601874 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17216.953136 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17216.953136 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152740.051854 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 152740.051854 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 77135.204372 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 77135.204372 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5955489 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.186843 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 198342876 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5956001 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 33.301350 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8518419495000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.186843 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.978881 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.978881 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16403.236160 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16403.236160 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17515.485766 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17515.485766 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176692.540498 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176692.540498 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91448.444895 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91448.444895 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 6156366 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.025645 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 184011394 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 6156878 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 29.887127 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8516343949500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.025645 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.978566 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 415232377 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 415232377 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 198342876 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 198342876 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 198342876 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 198342876 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 198342876 # number of overall hits -system.cpu1.icache.overall_hits::total 198342876 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6295293 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6295293 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6295293 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6295293 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6295293 # number of overall misses -system.cpu1.icache.overall_misses::total 6295293 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 67919445914 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 67919445914 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 67919445914 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 67919445914 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 67919445914 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 67919445914 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 204638169 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 204638169 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 204638169 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 204638169 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 204638169 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 204638169 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030763 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030763 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030763 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030763 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030763 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030763 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10788.925299 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10788.925299 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10788.925299 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10788.925299 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10788.925299 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10788.925299 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 9829448 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 701 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 729519 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.473875 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 233.666667 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5955489 # number of writebacks -system.cpu1.icache.writebacks::total 5955489 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 339254 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 339254 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 339254 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 339254 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 339254 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 339254 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5956039 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5956039 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5956039 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5956039 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5956039 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5956039 # number of overall MSHR misses +system.cpu1.icache.tags.tag_accesses 387206970 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 387206970 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 184011394 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 184011394 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 184011394 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 184011394 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 184011394 # number of overall hits +system.cpu1.icache.overall_hits::total 184011394 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 6513585 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 6513585 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 6513585 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 6513585 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 6513585 # number of overall misses +system.cpu1.icache.overall_misses::total 6513585 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 71534475691 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 71534475691 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 71534475691 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 71534475691 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 71534475691 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 71534475691 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 190524979 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 190524979 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 190524979 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 190524979 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 190524979 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 190524979 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.034188 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.034188 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.034188 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.034188 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.034188 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.034188 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10982.350839 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10982.350839 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10982.350839 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10982.350839 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 10659560 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 1026 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 770474 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.835068 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 256.500000 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 6156366 # number of writebacks +system.cpu1.icache.writebacks::total 6156366 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 356573 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 356573 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 356573 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 356573 # 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average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10298.408308 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10298.408308 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101514.895522 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101514.895522 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7017688 # 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number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7017998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 7017998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032316 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.032316 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.032316 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10485.385028 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 104746.238806 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 104746.238806 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7532579 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7540263 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 6914 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 831383 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2042934 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 12933.505047 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10254699 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2058843 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.980807 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 905745 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2237289 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 12906.637296 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10683229 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2253034 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.741708 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12624.033726 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 36.418354 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 27.691890 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 245.361077 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.770510 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002223 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001690 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014976 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.789399 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 293 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15553 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 116 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 99 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 69 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.343747 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 34.232851 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 25.792432 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 248.268266 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.768942 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002089 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001574 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.015153 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.787759 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 360 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15324 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1807 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7301 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4524 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1724 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017883 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.949280 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 390440087 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 390440087 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 557579 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 186161 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 743740 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3343376 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3343376 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 7851276 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 7851276 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 37 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 859794 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 859794 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5412981 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 5412981 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2828036 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2828036 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191737 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 191737 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 557579 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 186161 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5412981 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3687830 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9844551 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 557579 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 186161 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5412981 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3687830 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9844551 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 21615 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9433 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 31048 # number of ReadReq misses -system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses -system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 224939 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 224939 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 183720 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 183720 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 255308 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 255308 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 543023 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 543023 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 939708 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 939708 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 256512 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 256512 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 21615 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9433 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 543023 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1195016 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1769087 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 21615 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9433 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 543023 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1195016 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1769087 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 686942500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 338389000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1025331500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 939480500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 939480500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 264112000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 264112000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2448496 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2448496 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12203061000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 12203061000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19608835500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19608835500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34743736987 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34743736987 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 165000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 165000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 686942500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 338389000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19608835500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 46946797987 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 67580964987 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 686942500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 338389000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19608835500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 46946797987 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 67580964987 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 579194 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 195594 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 774788 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3343377 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3343377 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 7851276 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 7851276 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 224976 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 60380764485 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 343913500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18064709000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41319243985 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 106536831056 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6514500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3873635500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3880150000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6514500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3873635500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3880150000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041108 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999836 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999836 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999541 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999541 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219123 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219123 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091172 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248348 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248348 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.572247 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.572247 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.241674 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.151013 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.241674 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.198740 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.198740 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094783 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.252842 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.252842 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.547432 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.547432 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152870 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.215189 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27185.110468 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48620.817537 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18795.871267 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18795.871267 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15325.547012 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15325.547012 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 347082.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 347082.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37100.914690 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37100.914690 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30110.548007 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30852.431234 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30852.431234 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23288.664331 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23288.664331 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32146.253817 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31429.014374 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32146.253817 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36556.111738 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144717.901026 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 144337.715373 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 73083.940567 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 73163.415187 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 23228623 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11943528 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 5072 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 598776 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 598706 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 70 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 867379 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10679013 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 8695 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 8695 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4499349 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7854270 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1254191 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 938082 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 428069 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332128 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 468300 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1145370 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1120388 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5956039 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4785637 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 521245 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 449809 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17867666 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16911297 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 409122 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1224107 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36412192 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 762336624 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 654015560 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1564752 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4633552 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1422550488 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5059056 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 80617704 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 17392868 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.053991 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.226018 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.218292 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29514.167703 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58167.842352 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18783.759118 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18783.759118 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15367.275604 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15367.275604 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247944.222222 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247944.222222 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 39183.826986 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 39183.826986 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30955.142166 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32014.896809 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32014.896809 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 24559.370931 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 24559.370931 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32565.094029 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40238.199952 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168682.960286 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168475.098780 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87303.031327 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87318.000765 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 24247915 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12479959 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 8015 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 603053 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 602834 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 219 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 936644 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 11117136 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 21406 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 21406 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4809330 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 8167824 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1368728 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1012133 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 404751 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355876 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 480511 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1238980 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1214897 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6157012 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4940216 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 522762 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 463422 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18470485 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17838362 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 429531 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1305673 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 38044051 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 788054768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 689328153 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1639912 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4932816 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1483955649 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5334462 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 88980784 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 18249337 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.053626 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.225332 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 16453876 94.60% 94.60% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 938922 5.40% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 70 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 17270909 94.64% 94.64% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 978209 5.36% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 219 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 17392868 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 23086793966 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 170580468 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 18249337 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 24116423481 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 160883108 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8939751182 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 9241921761 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7774836803 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8211674528 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 213941664 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 224968642 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 645834647 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 690043535 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40408 # Transaction distribution -system.iobus.trans_dist::ReadResp 40408 # Transaction distribution -system.iobus.trans_dist::WriteReq 136658 # Transaction distribution -system.iobus.trans_dist::WriteResp 136658 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47776 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40285 # Transaction distribution +system.iobus.trans_dist::ReadResp 40285 # Transaction distribution +system.iobus.trans_dist::WriteReq 136579 # Transaction distribution +system.iobus.trans_dist::WriteResp 136579 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47524 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3026,15 +3027,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122710 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231342 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122406 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47796 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47544 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3045,21 +3046,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155817 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339384 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339384 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338984 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338984 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497287 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37041003 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496606 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36861002 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 331500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -3069,81 +3070,81 @@ system.iobus.reqLayer13.occupancy 9500 # La system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24305002 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24160506 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36394500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36392501 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 570335330 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570209840 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92783000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92558000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148038000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147938000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115667 # number of replacements -system.iocache.tags.tagsinuse 11.289924 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115633 # number of replacements +system.iocache.tags.tagsinuse 11.369333 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115683 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115649 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9156457442000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.417343 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.872581 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463584 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.242036 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705620 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9154282048000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.419555 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.949778 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463722 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.246861 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.710583 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041396 # Number of tag accesses -system.iocache.tags.data_accesses 1041396 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040946 # Number of tag accesses +system.iocache.tags.data_accesses 1040946 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8943 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8980 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8893 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8930 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115671 # number of demand (read+write) misses -system.iocache.demand_misses::total 115711 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115621 # number of demand (read+write) misses +system.iocache.demand_misses::total 115661 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115671 # number of overall misses -system.iocache.overall_misses::total 115711 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1878808543 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1884008543 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 370000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 370000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13080956787 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13080956787 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5570000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14959765330 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14965335330 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5570000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14959765330 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14965335330 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 115621 # number of overall misses +system.iocache.overall_misses::total 115661 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5192500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1787370736 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1792563236 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12950575604 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12950575604 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5561500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14737946340 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14743507840 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5561500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14737946340 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14743507840 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8943 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8980 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8893 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8930 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115671 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115711 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115621 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115661 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115671 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115711 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115621 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115661 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3157,53 +3158,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 210087.056133 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 209800.505902 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123333.333333 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 123333.333333 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 122563.495868 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 122563.495868 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139250 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129330.301718 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129333.730847 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139250 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129330.301718 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129333.730847 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 43850 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140337.837838 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 200986.251659 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 200734.964838 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121341.874710 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 121341.874710 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127471.730661 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127471.730661 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 39227 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3467 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3536 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.647822 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.093609 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106710 # 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number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7738901569 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7738901569 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3570000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9170560112 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9174130112 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3570000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9170560112 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9174130112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115621 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115661 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3342500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1342720736 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1346063236 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7608008190 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7608008190 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3561500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8950728926 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8954290426 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3561500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8950728926 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8954290426 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3217,656 +3218,658 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 160087.056133 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 159800.505902 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73333.333333 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 73333.333333 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 72510.508667 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 72510.508667 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89250 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79281.411175 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79284.857205 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89250 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79281.411175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79284.857205 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1625787 # number of replacements -system.l2c.tags.tagsinuse 65181.204595 # Cycle average of tags in use -system.l2c.tags.total_refs 6817657 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1687923 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.039081 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3083223500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 9617.868100 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 445.484302 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 525.919749 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4087.647415 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 22210.879235 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 20823.279726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 29.752566 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 32.095436 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2691.005366 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3224.848807 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1492.423894 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.146757 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006798 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.008025 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.338911 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.317738 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000454 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000490 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.041061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.049207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022773 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994586 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 12119 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 287 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49730 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1349 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 918 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9840 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 283 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2201 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4435 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42789 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.184921 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004379 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.758820 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 77430161 # Number of tag accesses -system.l2c.tags.data_accesses 77430161 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2884653 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2884653 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 199415 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 166641 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 366056 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 54285 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 48308 # 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number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 304905 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2831340 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 116676 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 127973 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 244649 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 12524 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4903 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 523305 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 664272 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 287889 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 14056 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 496370 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.325360 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.278628 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001161 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001324 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.048224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.065110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.049724 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995222 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 11759 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49542 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 196 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 891 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10670 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2478 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2877 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 43809 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.179428 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.755951 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 84121444 # Number of tag accesses +system.l2c.tags.data_accesses 84121444 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 3161961 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 3161961 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 218473 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 178227 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 396700 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 60416 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 50161 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 110577 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 54320 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59150 # 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number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 121091 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 243714 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 13417 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5017 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 539007 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 722848 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 293105 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 15148 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6130 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 525725 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 685679 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 298432 # number of demand (read+write) hits +system.l2c.demand_hits::total 3104508 # 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average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105558.459363 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 125462.625090 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24731.337936 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19590.158569 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23935.917426 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100998.508678 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103295.357775 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 122048.235828 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100998.508678 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103295.357775 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 122048.235828 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162895.779233 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126731.706168 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124280.086625 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81343.515024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 63993.594967 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 75714.318477 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 4039865 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2364937 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3552 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.090026 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.113299 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.100631 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.016811 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.020542 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.018507 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.639570 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.473281 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.568568 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.229637 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.170004 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.272553 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790053 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.442701 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.695870 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.290348 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.290348 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20261.288979 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.617178 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20533.376845 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24157.792836 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24591.730038 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24376.738609 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97847.242341 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98082.342415 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 97930.801930 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99676.794304 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108345.828832 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126680.145941 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24678.176440 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19608.216995 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23803.616300 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156825.980054 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150687.984670 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 148855.242426 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75004.347099 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77986.330328 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 76554.284857 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 4427188 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2544778 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 59844 # Transaction distribution -system.membus.trans_dist::ReadResp 1018974 # Transaction distribution -system.membus.trans_dist::WriteReq 38386 # Transaction distribution -system.membus.trans_dist::WriteResp 38386 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1351242 # Transaction distribution -system.membus.trans_dist::CleanEvict 267627 # Transaction distribution -system.membus.trans_dist::UpgradeReq 336754 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 267840 # Transaction distribution -system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 152823 # Transaction distribution -system.membus.trans_dist::ReadExResp 138565 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 959130 # Transaction distribution -system.membus.trans_dist::InvalidateReq 652932 # Transaction distribution -system.membus.trans_dist::InvalidateResp 30629 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122710 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 40965 # Transaction distribution +system.membus.trans_dist::ReadResp 1170673 # Transaction distribution +system.membus.trans_dist::WriteReq 38689 # Transaction distribution +system.membus.trans_dist::WriteResp 38689 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1526901 # Transaction distribution +system.membus.trans_dist::CleanEvict 301973 # Transaction distribution +system.membus.trans_dist::UpgradeReq 291943 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 287508 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 162891 # Transaction distribution +system.membus.trans_dist::ReadExResp 148894 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1129708 # Transaction distribution +system.membus.trans_dist::InvalidateReq 674487 # Transaction distribution +system.membus.trans_dist::InvalidateResp 26345 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122406 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4892821 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5041417 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237968 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237968 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5279385 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155817 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27362 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5422541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5572385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238081 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238081 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5810466 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155536 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 149644096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 149852089 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7250176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7250176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 157102265 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 616817 # Total snoops (count) -system.membus.snoopTraffic 199808 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2467715 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013862 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.116919 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172160384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 172371200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7263808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7263808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 179635008 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 585668 # Total snoops (count) +system.membus.snoopTraffic 182912 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2626196 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011361 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.105982 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2433507 98.61% 98.61% # Request fanout histogram -system.membus.snoop_fanout::1 34208 1.39% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2596359 98.86% 98.86% # Request fanout histogram +system.membus.snoop_fanout::1 29837 1.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2467715 # Request fanout histogram -system.membus.reqLayer0.occupancy 98169995 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2626196 # Request fanout histogram +system.membus.reqLayer0.occupancy 97843991 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21686998 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22899493 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9247698101 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10387724889 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5871093052 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6773203746 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 81490219 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 76561844 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3909,82 +3912,83 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12086303 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6387551 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2235502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 239971 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 217052 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 22919 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 59846 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4613854 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38386 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38386 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4129201 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2768870 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 702098 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 370433 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1072531 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298786 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298786 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4554900 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 905153 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 886862 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9925339 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7679367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17604706 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 251196049 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 191962664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 443158713 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3147878 # Total snoops (count) -system.toL2Bus.snoopTraffic 132377296 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8556431 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.371457 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.488706 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12840687 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6804210 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2233432 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 286650 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 259465 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 27185 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 40967 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4895074 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38689 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38689 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4582152 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2976886 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 687999 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 398085 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1086084 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 311857 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 311857 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4854758 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 900244 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 885499 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10402586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8325072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18727658 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271068295 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 211681017 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 482749312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3295138 # Total snoops (count) +system.toL2Bus.snoopTraffic 141512016 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 9092383 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.348495 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.482728 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5401002 63.12% 63.12% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3132510 36.61% 99.73% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 22919 0.27% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5950920 65.45% 65.45% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3114278 34.25% 99.70% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 27185 0.30% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8556431 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9443624545 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9092383 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 10118543300 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 9237873 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 8937131 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4533014073 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4714839859 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3814018472 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4090244927 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13606 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 5530 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5169 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 13684 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index fa5414686..982f55812 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.558690 # Number of seconds simulated -sim_ticks 51558689626000 # Number of ticks simulated -final_tick 51558689626000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.277959 # Number of seconds simulated +sim_ticks 51277959410000 # Number of ticks simulated +final_tick 51277959410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210245 # Simulator instruction rate (inst/s) -host_op_rate 247121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9737217389 # Simulator tick rate (ticks/s) -host_mem_usage 695392 # Number of bytes of host memory used -host_seconds 5295.01 # Real time elapsed on the host -sim_insts 1113248331 # Number of instructions simulated -sim_ops 1308509399 # Number of ops (including micro ops) simulated +host_inst_rate 210382 # Simulator instruction rate (inst/s) +host_op_rate 250295 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13357159040 # Simulator tick rate (ticks/s) +host_mem_usage 689664 # Number of bytes of host memory used +host_seconds 3838.99 # Real time elapsed on the host +sim_insts 807652759 # Number of instructions simulated +sim_ops 960879271 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 688064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 572736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6466080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 114242184 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 427328 # Number of bytes read from this memory -system.physmem.bytes_read::total 122396392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6466080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6466080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 142998784 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 253184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 234496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5589856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47714440 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 412800 # Number of bytes read from this memory +system.physmem.bytes_read::total 54204776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5589856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5589856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74605824 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 143019364 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 10751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 8949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 116985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1785047 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6677 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1928409 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2234356 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74626404 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3956 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3664 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 88894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 745551 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6450 # Number of read requests responded to by this memory +system.physmem.num_reads::total 848515 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1165716 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2236929 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 13345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 11108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 125412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2215770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2373924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 125412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 125412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2773515 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2773914 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2773515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 13345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 11108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 125412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2216169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5147838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1928410 # Number of read requests accepted -system.physmem.writeReqs 2236929 # Number of write requests accepted -system.physmem.readBursts 1928410 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2236929 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 123382976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35200 # Total number of bytes read from write queue -system.physmem.bytesWritten 143016896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 122396456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 143019364 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 550 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2266 # Number of DRAM write bursts merged with an existing one +system.physmem.num_writes::total 1168289 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 109011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 930506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1057077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 109011 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 109011 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1454930 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1455331 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1454930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 109011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 930907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2512408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 848516 # Number of read requests accepted +system.physmem.writeReqs 1168289 # Number of write requests accepted +system.physmem.readBursts 848516 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1168289 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 54258624 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 46336 # Total number of bytes read from write queue +system.physmem.bytesWritten 74623296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 54204840 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 74626404 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 724 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2278 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 114164 # Per bank write bursts -system.physmem.perBankRdBursts::1 120325 # Per bank write bursts -system.physmem.perBankRdBursts::2 121021 # Per bank write bursts -system.physmem.perBankRdBursts::3 117289 # Per bank write bursts -system.physmem.perBankRdBursts::4 115474 # Per bank write bursts -system.physmem.perBankRdBursts::5 125294 # Per bank write bursts -system.physmem.perBankRdBursts::6 117554 # Per bank write bursts -system.physmem.perBankRdBursts::7 120469 # Per bank write bursts -system.physmem.perBankRdBursts::8 115697 # Per bank write bursts -system.physmem.perBankRdBursts::9 146662 # Per bank write bursts -system.physmem.perBankRdBursts::10 119160 # Per bank write bursts -system.physmem.perBankRdBursts::11 123181 # Per bank write bursts -system.physmem.perBankRdBursts::12 118002 # Per bank write bursts -system.physmem.perBankRdBursts::13 121360 # Per bank write bursts -system.physmem.perBankRdBursts::14 114093 # Per bank write bursts -system.physmem.perBankRdBursts::15 118114 # Per bank write bursts -system.physmem.perBankWrBursts::0 133629 # Per bank write bursts -system.physmem.perBankWrBursts::1 139072 # Per bank write bursts -system.physmem.perBankWrBursts::2 140295 # Per bank write bursts -system.physmem.perBankWrBursts::3 139312 # Per bank write bursts -system.physmem.perBankWrBursts::4 138711 # Per bank write bursts -system.physmem.perBankWrBursts::5 145043 # Per bank write bursts -system.physmem.perBankWrBursts::6 137653 # Per bank write bursts -system.physmem.perBankWrBursts::7 140751 # Per bank write bursts -system.physmem.perBankWrBursts::8 137271 # Per bank write bursts -system.physmem.perBankWrBursts::9 144471 # Per bank write bursts -system.physmem.perBankWrBursts::10 139139 # Per bank write bursts -system.physmem.perBankWrBursts::11 142751 # Per bank write bursts -system.physmem.perBankWrBursts::12 139024 # Per bank write bursts -system.physmem.perBankWrBursts::13 141466 # Per bank write bursts -system.physmem.perBankWrBursts::14 137078 # Per bank write bursts -system.physmem.perBankWrBursts::15 138973 # Per bank write bursts +system.physmem.perBankRdBursts::0 50870 # Per bank write bursts +system.physmem.perBankRdBursts::1 59107 # Per bank write bursts +system.physmem.perBankRdBursts::2 53673 # Per bank write bursts +system.physmem.perBankRdBursts::3 52283 # Per bank write bursts +system.physmem.perBankRdBursts::4 52009 # Per bank write bursts +system.physmem.perBankRdBursts::5 59846 # Per bank write bursts +system.physmem.perBankRdBursts::6 50421 # Per bank write bursts +system.physmem.perBankRdBursts::7 52784 # Per bank write bursts +system.physmem.perBankRdBursts::8 49319 # Per bank write bursts +system.physmem.perBankRdBursts::9 57871 # Per bank write bursts +system.physmem.perBankRdBursts::10 53663 # Per bank write bursts +system.physmem.perBankRdBursts::11 59850 # Per bank write bursts +system.physmem.perBankRdBursts::12 49313 # Per bank write bursts +system.physmem.perBankRdBursts::13 51526 # Per bank write bursts +system.physmem.perBankRdBursts::14 46865 # Per bank write bursts +system.physmem.perBankRdBursts::15 48391 # Per bank write bursts +system.physmem.perBankWrBursts::0 70028 # Per bank write bursts +system.physmem.perBankWrBursts::1 76221 # Per bank write bursts +system.physmem.perBankWrBursts::2 72051 # Per bank write bursts +system.physmem.perBankWrBursts::3 73117 # Per bank write bursts +system.physmem.perBankWrBursts::4 72572 # Per bank write bursts +system.physmem.perBankWrBursts::5 78772 # Per bank write bursts +system.physmem.perBankWrBursts::6 71408 # Per bank write bursts +system.physmem.perBankWrBursts::7 73272 # Per bank write bursts +system.physmem.perBankWrBursts::8 71515 # Per bank write bursts +system.physmem.perBankWrBursts::9 77080 # Per bank write bursts +system.physmem.perBankWrBursts::10 72838 # Per bank write bursts +system.physmem.perBankWrBursts::11 77780 # Per bank write bursts +system.physmem.perBankWrBursts::12 69170 # Per bank write bursts +system.physmem.perBankWrBursts::13 71642 # Per bank write bursts +system.physmem.perBankWrBursts::14 68698 # Per bank write bursts +system.physmem.perBankWrBursts::15 69825 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 512 # Number of times write queue was full causing retry -system.physmem.totGap 51558688241500 # Total gap between requests +system.physmem.numWrRetry 522 # Number of times write queue was full causing retry +system.physmem.totGap 51277958025500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) -system.physmem.readPktSize::4 21272 # Read request sizes (log2) +system.physmem.readPktSize::4 2072 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1907125 # Read request sizes (log2) +system.physmem.readPktSize::6 846431 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2234356 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1137157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 697006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 62243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1165716 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 541295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 247060 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 638 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,184 +160,185 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 36181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 84750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 118181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 127464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 131678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 133520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 138083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 140930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 136900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 140021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 142369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 134210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 132730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 134518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 146577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 128734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 131799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1159 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 946985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.313381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.848752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.664857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 373897 39.48% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 237629 25.09% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 90926 9.60% 74.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 53224 5.62% 79.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 39122 4.13% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 27360 2.89% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21677 2.29% 89.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17745 1.87% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 85405 9.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 946985 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 117910 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.350064 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 51.964300 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 117905 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 117910 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 117910 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.952074 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.420057 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.842093 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 113720 96.45% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 1383 1.17% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 426 0.36% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 819 0.69% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 466 0.40% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 257 0.22% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 350 0.30% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 159 0.13% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 44 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 53 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 45 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 26 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 14 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 12 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 23 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 25 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 22 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 13 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 7 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 7 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::624-639 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 18590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 25743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 45741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 55757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 63122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 66457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 68011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 72400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 75195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 71101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 74150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 75214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 67195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 65816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 65315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 67462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1155 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 505782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 254.816375 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.511846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 294.316020 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 218537 43.21% 43.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 130980 25.90% 69.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 46546 9.20% 78.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24886 4.92% 83.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16948 3.35% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10705 2.12% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8138 1.61% 90.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6857 1.36% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 42185 8.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 505782 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 52835 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.045538 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 23.735472 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 52822 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 8 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 3 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 52835 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 52835 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.068496 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.791739 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 25.919021 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 48708 92.19% 92.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 1351 2.56% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 388 0.73% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 806 1.53% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 454 0.86% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 263 0.50% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 370 0.70% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 158 0.30% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 43 0.08% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 52 0.10% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 56 0.11% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 28 0.05% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 16 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 21 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 12 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 27 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 19 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 15 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 8 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::592-607 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::624-639 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 4 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::656-671 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::736-751 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::752-767 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::880-895 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 117910 # Writes before turning the bus around for reads -system.physmem.totQLat 71195410655 # Total ticks spent queuing -system.physmem.totMemAccLat 107342766905 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9639295000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36929.76 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55679.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.77 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s +system.physmem.wrPerTurnAround::880-895 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::912-927 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::992-1007 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 52835 # Writes before turning the bus around for reads +system.physmem.totQLat 32888008041 # Total ticks spent queuing +system.physmem.totMemAccLat 48784089291 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4238955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 38792.54 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.99 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 57542.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.06 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing -system.physmem.readRowHits 1556076 # Number of row buffer hits during reads -system.physmem.writeRowHits 1659436 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.72 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.26 # Row buffer hit rate for writes -system.physmem.avgGap 12378029.31 # Average gap between requests -system.physmem.pageHitRate 77.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3355628640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1783558920 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6794352600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5817512520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 51361776960.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 51335807970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3128372160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 100703099850 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 75728818080 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12253311191655 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12553360719255 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.477109 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51437874182990 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 5229192000 # Time in different power states -system.physmem_0.memoryStateTime::REF 21823720000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51019823371500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 197210375905 # Time in different power states -system.physmem_0.memoryStateTime::ACT 93762531010 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 220840435585 # Time in different power states -system.physmem_1.actEnergy 3405851400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1810249155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6970560660 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5847303060 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 52613798640.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 52063882650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3186128160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 104825729160 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 76862967360 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12250174362465 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12557802494490 # Total energy per rank (pJ) -system.physmem_1.averagePower 243.563259 # Core power per rank (mW) -system.physmem_1.totalIdleTime 51436124881809 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 5313449750 # Time in different power states -system.physmem_1.memoryStateTime::REF 22355242000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51006079595250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 200164062707 # Time in different power states -system.physmem_1.memoryStateTime::ACT 94896006191 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 229881270102 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing +system.physmem.readRowHits 648292 # Number of row buffer hits during reads +system.physmem.writeRowHits 859704 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.73 # Row buffer hit rate for writes +system.physmem.avgGap 25425342.57 # Average gap between requests +system.physmem.pageHitRate 74.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1849802640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 983185830 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3077290020 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3066442020 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 32858039760.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 30159163980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1958344800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 66073114650 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 46519620000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12231781860420 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12418342348350 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.176999 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51206686329778 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3544531992 # Time in different power states +system.physmem_0.memoryStateTime::REF 13966174000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 50940644588000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 121144747142 # Time in different power states +system.physmem_0.memoryStateTime::ACT 53762327980 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 144897040886 # Time in different power states +system.physmem_1.actEnergy 1761495120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 936256860 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2975937720 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3020020560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 32012909760.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 29684228010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1902447840 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 63461801580 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 45299969760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12234156504570 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12415225828860 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.116222 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51207876412176 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3424177242 # Time in different power states +system.physmem_1.memoryStateTime::REF 13608086000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 50950737151500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 117968786503 # Time in different power states +system.physmem_1.memoryStateTime::ACT 53050734582 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 139170474173 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -354,30 +355,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 291746368 # Number of BP lookups -system.cpu.branchPred.condPredicted 199670043 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13704274 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 209695065 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131330914 # Number of BTB hits +system.cpu.branchPred.lookups 214792288 # Number of BP lookups +system.cpu.branchPred.condPredicted 137846282 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12464803 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 146135265 # Number of BTB lookups +system.cpu.branchPred.BTBHits 84448125 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.629473 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37689025 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 403296 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 8150983 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6071547 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2079436 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 799941 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 57.787643 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31594768 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 349324 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6874034 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4883721 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1990313 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 771971 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -407,93 +408,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 1432753 # Table walker walks requested -system.cpu.dtb.walker.walksLong 1432753 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 31582 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277767 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 672727 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 760026 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2835.541153 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 21869.031891 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 752912 99.06% 99.06% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 4648 0.61% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 979 0.13% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 465 0.06% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 329 0.04% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.00% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 227 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 31 0.00% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 15 0.00% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 373 0.05% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 760026 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 802864 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 26261.811465 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21447.525498 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20174.954942 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 783898 97.64% 97.64% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 15255 1.90% 99.54% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1830 0.23% 99.77% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 1111 0.14% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 417 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 138 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 67 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 44 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 88 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 802864 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1071344974520 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.740930 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.520683 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 1067157103520 99.61% 99.61% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 2648963000 0.25% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 765456500 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 299226500 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 205947000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 124770000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 49360500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 91134000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2962000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::18-19 28500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1071344974520 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 277768 89.79% 89.79% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 31582 10.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 309350 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1432753 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 970467 # Table walker walks requested +system.cpu.dtb.walker.walksLong 970467 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 18061 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 162102 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 433748 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 536719 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2148.778970 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14488.438649 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 533045 99.32% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 2702 0.50% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 468 0.09% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 229 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 124 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 18 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 94 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 8 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 22 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 536719 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 489559 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21856.142978 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 16984.908569 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 19510.602702 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 478829 97.81% 97.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 9216 1.88% 99.69% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 680 0.14% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 491 0.10% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 167 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 30 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 18 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 87 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 13 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 489559 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 687539152416 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.766147 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.508794 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 685391448916 99.69% 99.69% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1144327500 0.17% 99.85% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 477284500 0.07% 99.92% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 191925000 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 139963500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 102241500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 33074500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 56365000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2522000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 687539152416 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 162103 89.98% 89.98% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 18061 10.02% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 180164 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 970467 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1432753 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309350 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 970467 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 180164 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309350 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1742103 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 180164 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1150631 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 218702786 # DTB read hits -system.cpu.dtb.read_misses 1008685 # DTB read misses -system.cpu.dtb.write_hits 193509885 # DTB write hits -system.cpu.dtb.write_misses 424068 # DTB write misses -system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 174485449 # DTB read hits +system.cpu.dtb.read_misses 696020 # DTB read misses +system.cpu.dtb.write_hits 152010399 # DTB write hits +system.cpu.dtb.write_misses 274447 # DTB write misses +system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 88843 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 16314 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 41510 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1047 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 74778 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 103 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10363 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 85947 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 219711471 # DTB read accesses -system.cpu.dtb.write_accesses 193933953 # DTB write accesses +system.cpu.dtb.perms_faults 69607 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 175181469 # DTB read accesses +system.cpu.dtb.write_accesses 152284846 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 412212671 # DTB hits -system.cpu.dtb.misses 1432753 # DTB misses -system.cpu.dtb.accesses 413645424 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 326495848 # DTB hits +system.cpu.dtb.misses 970467 # DTB misses +system.cpu.dtb.accesses 327466315 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -523,1117 +518,1115 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 178667 # Table walker walks requested -system.cpu.itb.walker.walksLong 178667 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1505 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 129431 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 20285 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 158382 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1812.216666 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 18363.278107 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-65535 157121 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-131071 1064 0.67% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-196607 45 0.03% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-327679 12 0.01% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-393215 8 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-458751 4 0.00% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::524288-589823 38 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::589824-655359 58 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 158382 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 151221 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29741.047870 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23638.717531 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 30785.807578 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 145088 95.94% 95.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 5051 3.34% 99.28% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 405 0.27% 99.55% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 372 0.25% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 84 0.06% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 62 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 13 0.01% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 89 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 6 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::720896-786431 31 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 151221 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 912431133568 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.946195 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.225953 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 49158537652 5.39% 5.39% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 863207621416 94.61% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 64327000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 645500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 912431133568 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 129431 98.85% 98.85% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1505 1.15% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 130936 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 166329 # Table walker walks requested +system.cpu.itb.walker.walksLong 166329 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1543 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 121824 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 18039 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 148290 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1030.507789 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 10121.197556 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-65535 147791 99.66% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-131071 435 0.29% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-196607 25 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-262143 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-393215 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::458752-524287 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::524288-589823 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::589824-655359 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 148290 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 141406 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26889.721794 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 22183.567838 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 21940.142141 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 138369 97.85% 97.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2580 1.82% 99.68% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 191 0.14% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 150 0.11% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 40 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 49 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 141406 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 580161918016 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.951845 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.214419 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 27974300560 4.82% 4.82% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 552153156456 95.17% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 33290000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 609500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 49000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::5 512500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 580161918016 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 121824 98.75% 98.75% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1543 1.25% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123367 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178667 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 178667 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 166329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 166329 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130936 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 130936 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 309603 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 465155459 # ITB inst hits -system.cpu.itb.inst_misses 178667 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123367 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123367 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 289696 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 333977355 # ITB inst hits +system.cpu.itb.inst_misses 166329 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 62700 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 41510 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1047 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 54464 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 443616 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 373131 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 465334126 # ITB inst accesses -system.cpu.itb.hits 465155459 # DTB hits -system.cpu.itb.misses 178667 # DTB misses -system.cpu.itb.accesses 465334126 # DTB accesses -system.cpu.numPwrStateTransitions 34326 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 17163 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 2940291030.619589 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 58535247231.170448 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7840 45.68% 45.68% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9287 54.11% 99.79% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 334143684 # ITB inst accesses +system.cpu.itb.hits 333977355 # DTB hits +system.cpu.itb.misses 166329 # DTB misses +system.cpu.itb.accesses 334143684 # DTB accesses +system.cpu.numPwrStateTransitions 32546 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16273 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3107516335.044798 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60196725189.485252 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 6948 42.70% 42.70% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9289 57.08% 99.78% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::overflows 18 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 17163 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1094474667476 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50464214958524 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2188958665 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 16273 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 709346089816 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50568613320184 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1418701600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 793327228 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1301291266 # Number of instructions fetch has processed -system.cpu.fetch.Branches 291746368 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 175091486 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1303318637 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29494258 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4691335 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11697076 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1210879 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 1191 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 464693718 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6899661 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 52634 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2129020646 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.716284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.134063 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 626970761 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 964955706 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214792288 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 120926614 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 712354427 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26627776 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3832226 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 25955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9044924 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1035738 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 1059 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 333569052 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6336680 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48713 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1366578978 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.835386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.187527 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1402178691 65.86% 65.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 283295913 13.31% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 88951632 4.18% 83.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 354594410 16.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 828034594 60.59% 60.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 202016384 14.78% 75.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 69979562 5.12% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 266548438 19.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2129020646 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133281 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.594480 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 614901243 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 887926164 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542267168 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73189541 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10736530 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41417664 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4068147 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1415615504 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 33076716 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10736530 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 677683388 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 94369025 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 569420569 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 556850066 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219961068 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1391316215 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 8139294 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7433415 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 989914 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1107412 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 140152556 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 22881 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1341380585 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2214711658 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1650667847 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1431319 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1262462841 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78917741 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44085987 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39608884 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160777326 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 223759172 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 197950271 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12848262 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11112686 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1338031616 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 44396038 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1368016868 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4222413 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 73918251 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42115616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 367601 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2129020646 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.642557 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.913774 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1366578978 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.151401 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.680168 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 523831535 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 358407215 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 444986242 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 29823356 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9530630 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 82997397 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3840205 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1051662188 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29872784 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9530630 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 559062030 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 58275029 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 221284587 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 439543391 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 78883311 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1030946151 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 7084405 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5220432 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 401053 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 689601 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 52909282 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20659 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 944726342 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1460373617 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1214391439 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1466073 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 877604087 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 67122252 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11621737 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 7877357 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 58456344 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 178961087 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 155538156 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 10194150 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9195511 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1010975595 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 11936880 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1010573430 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3406540 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 62033200 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 34713553 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 312805 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1366578978 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.739491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.966076 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1277602195 60.01% 60.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 452152764 21.24% 81.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 292326493 13.73% 94.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96574735 4.54% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10335382 0.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29077 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 766524619 56.09% 56.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 278054062 20.35% 76.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 240507320 17.60% 94.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 74487645 5.45% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6984867 0.51% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20465 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2129020646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1366578978 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 73998347 33.81% 33.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90252 0.04% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26750 0.01% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 451 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 58933248 26.93% 60.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 85092406 38.88% 99.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 64953 0.03% 99.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 641116 0.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59327643 34.80% 34.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 97860 0.06% 34.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26629 0.02% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 606 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 45774518 26.85% 61.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64550245 37.86% 99.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 65013 0.04% 99.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 650262 0.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 41 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 945166591 69.09% 69.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2943445 0.22% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 129819 0.01% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 9 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 24 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 112220 0.01% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 223636421 16.35% 85.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 195247662 14.27% 99.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 119006 0.01% 99.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 661615 0.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 675222587 66.82% 66.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2579661 0.26% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 123552 0.01% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 381 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 24 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 118042 0.01% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 178525210 17.67% 84.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 153211297 15.16% 99.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 117761 0.01% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 674889 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1368016868 # Type of FU issued -system.cpu.iq.rate 0.624962 # Inst issue rate -system.cpu.iq.fu_busy_cnt 218847523 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.159974 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5085629992 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1455613237 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1345805572 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2494325 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 915085 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 886623 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1585264941 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1599409 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5699315 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1010573430 # Type of FU issued +system.cpu.iq.rate 0.712323 # Inst issue rate +system.cpu.iq.fu_busy_cnt 170492776 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.168709 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3559085350 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1084154908 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 991977756 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2539803 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 933979 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 905255 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1179439202 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1626993 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4435926 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17397321 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21752 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 184120 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8002822 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14385160 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15174 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 144472 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6174251 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3610863 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2045833 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2629445 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1524875 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10736530 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13380632 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5317474 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1382714005 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9530630 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7210038 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4323845 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1023153770 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 223759172 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 197950271 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39068255 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 183844 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4942045 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 184120 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4054774 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6111734 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10166508 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1354334153 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 218708027 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12279784 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 178961087 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 155538156 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7437223 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 69213 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4169498 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 144472 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3542728 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5585702 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 9128430 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 998939859 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 174475303 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10677060 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 286351 # number of nop insts executed -system.cpu.iew.exec_refs 412227919 # number of memory reference insts executed -system.cpu.iew.exec_branches 257147927 # Number of branches executed -system.cpu.iew.exec_stores 193519892 # Number of stores executed -system.cpu.iew.exec_rate 0.618712 # Inst execution rate -system.cpu.iew.wb_sent 1347736728 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1346692195 # cumulative count of insts written-back -system.cpu.iew.wb_producers 575598964 # num instructions producing a value -system.cpu.iew.wb_consumers 947631330 # num instructions consuming a value -system.cpu.iew.wb_rate 0.615220 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.607408 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 63004798 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 44028437 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9693675 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2114795220 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.618740 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.263829 # Number of insts commited each cycle +system.cpu.iew.exec_nop 241295 # number of nop insts executed +system.cpu.iew.exec_refs 326482764 # number of memory reference insts executed +system.cpu.iew.exec_branches 185483896 # Number of branches executed +system.cpu.iew.exec_stores 152007461 # Number of stores executed +system.cpu.iew.exec_rate 0.704123 # Inst execution rate +system.cpu.iew.wb_sent 993723823 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 992883011 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420701773 # num instructions producing a value +system.cpu.iew.wb_consumers 671731184 # num instructions consuming a value +system.cpu.iew.wb_rate 0.699853 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626295 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 52581924 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 11624075 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8681545 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1354317292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.709493 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.365584 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1434472892 67.83% 67.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 397205670 18.78% 86.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 150685224 7.13% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44578118 2.11% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36046556 1.70% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18010679 0.85% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 11270632 0.53% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5868076 0.28% 99.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16657373 0.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 893350952 65.96% 65.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 231145639 17.07% 83.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 123165028 9.09% 92.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 37514552 2.77% 94.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29252763 2.16% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14325561 1.06% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8938173 0.66% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4404967 0.33% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 12219657 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2114795220 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1113248331 # Number of instructions committed -system.cpu.commit.committedOps 1308509399 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1354317292 # Number of insts commited each cycle +system.cpu.commit.committedInsts 807652759 # Number of instructions committed +system.cpu.commit.committedOps 960879271 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 396309299 # Number of memory references committed -system.cpu.commit.loads 206361850 # Number of loads committed -system.cpu.commit.membars 9184659 # Number of memory barriers committed -system.cpu.commit.branches 248844974 # Number of branches committed -system.cpu.commit.fp_insts 874713 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1195788175 # Number of committed integer instructions. -system.cpu.commit.function_calls 31054705 # Number of function calls committed. +system.cpu.commit.refs 313939831 # Number of memory references committed +system.cpu.commit.loads 164575926 # Number of loads committed +system.cpu.commit.membars 7185354 # Number of memory barriers committed +system.cpu.commit.branches 178524482 # Number of branches committed +system.cpu.commit.fp_insts 893967 # Number of committed floating point instructions. +system.cpu.commit.int_insts 893684330 # Number of committed integer instructions. +system.cpu.commit.function_calls 25910780 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 909436322 69.50% 69.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2554044 0.20% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 103998 0.01% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 8 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 13 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 21 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 105694 0.01% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 206248879 15.76% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 189291443 14.47% 99.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 112971 0.01% 99.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 656006 0.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 644536442 67.08% 67.08% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2193608 0.23% 67.31% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98465 0.01% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 8 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 13 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 21 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 110883 0.01% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 164464107 17.12% 84.44% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 148692682 15.47% 99.92% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 111819 0.01% 99.93% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 671223 0.07% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1308509399 # Class of committed instruction -system.cpu.commit.bw_lim_events 16657373 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3460150362 # The number of ROB reads -system.cpu.rob.rob_writes 2757143126 # The number of ROB writes -system.cpu.timesIdled 9093879 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59938019 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100928420629 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1113248331 # Number of Instructions Simulated -system.cpu.committedOps 1308509399 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.966281 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.966281 # CPI: Total CPI of All Threads -system.cpu.ipc 0.508574 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.508574 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1608691208 # number of integer regfile reads -system.cpu.int_regfile_writes 947917634 # number of integer regfile writes -system.cpu.fp_regfile_reads 1422673 # number of floating regfile reads -system.cpu.fp_regfile_writes 763952 # number of floating regfile writes -system.cpu.cc_regfile_reads 314581614 # number of cc regfile reads -system.cpu.cc_regfile_writes 315450766 # number of cc regfile writes -system.cpu.misc_regfile_reads 3476012517 # number of misc regfile reads -system.cpu.misc_regfile_writes 44950556 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 13775006 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.982219 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 363107662 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13775518 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.358912 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1801582500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.982219 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 960879271 # Class of committed instruction +system.cpu.commit.bw_lim_events 12219657 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2347791153 # The number of ROB reads +system.cpu.rob.rob_writes 2039089805 # The number of ROB writes +system.cpu.timesIdled 8233460 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52122622 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101137217350 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 807652759 # Number of Instructions Simulated +system.cpu.committedOps 960879271 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.756574 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.756574 # CPI: Total CPI of All Threads +system.cpu.ipc 0.569290 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.569290 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1178021092 # number of integer regfile reads +system.cpu.int_regfile_writes 719548586 # number of integer regfile writes +system.cpu.fp_regfile_reads 1455011 # number of floating regfile reads +system.cpu.fp_regfile_writes 777624 # number of floating regfile writes +system.cpu.cc_regfile_reads 183031164 # number of cc regfile reads +system.cpu.cc_regfile_writes 183683629 # number of cc regfile writes +system.cpu.misc_regfile_reads 2245464732 # number of misc regfile reads +system.cpu.misc_regfile_writes 11742996 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 10097387 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.998168 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 291447803 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10097899 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 28.862222 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 194046500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.998168 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1608531103 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1608531103 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 187963659 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 187963659 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164128124 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164128124 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 464529 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 464529 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 334911 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 334911 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4841304 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4841304 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5331661 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5331661 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 352426694 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 352426694 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 352891223 # number of overall hits -system.cpu.dcache.overall_hits::total 352891223 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12866276 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12866276 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18869425 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18869425 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2066021 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2066021 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1270837 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1270837 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 552138 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 552138 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 33006538 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 33006538 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 35072559 # number of overall misses -system.cpu.dcache.overall_misses::total 35072559 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 225016613000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 225016613000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1113555465610 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1113555465610 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30066239407 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 30066239407 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9389478000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 9389478000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 268500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 268500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1368638318017 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1368638318017 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1368638318017 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1368638318017 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 200829935 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 200829935 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 182997549 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 182997549 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2530550 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2530550 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605748 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1605748 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5393442 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5393442 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5331669 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5331669 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385433232 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385433232 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 387963782 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 387963782 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064066 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.064066 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103113 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.103113 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816432 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.816432 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791430 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791430 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102372 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1275104379 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1275104379 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 151424979 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 151424979 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 131950159 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 131950159 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 388682 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 388682 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 326177 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 326177 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3459521 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3459521 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3868336 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3868336 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 283701315 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 283701315 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 284089997 # number of overall hits +system.cpu.dcache.overall_hits::total 284089997 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9913119 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9913119 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11970495 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11970495 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1253745 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1253745 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1236891 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1236891 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 459501 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 459501 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 9 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 23120505 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 23120505 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 24374250 # number of overall misses +system.cpu.dcache.overall_misses::total 24374250 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 163455721000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 163455721000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 418494791659 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 418494791659 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27820801905 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 27820801905 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6946845500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6946845500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 284500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 284500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 609771314564 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 609771314564 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 609771314564 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 609771314564 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 161338098 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 161338098 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 143920654 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 143920654 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1642427 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1642427 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1563068 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1563068 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3919022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3868345 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3868345 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 306821820 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 306821820 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 308464247 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 308464247 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061443 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061443 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083174 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.083174 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.763349 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.763349 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791323 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791323 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.117249 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.117249 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.085635 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.085635 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.090402 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.090402 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17488.868807 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17488.868807 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59013.746609 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59013.746609 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23658.611928 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23658.611928 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17005.672495 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17005.672495 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33562.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33562.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41465.673195 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41465.673195 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39023.052695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39023.052695 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29226576 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.075355 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.075355 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.079018 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.079018 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16488.828693 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16488.828693 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34960.525163 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34960.525163 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22492.525134 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22492.525134 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15118.238045 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15118.238045 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 31611.111111 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 31611.111111 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26373.615739 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26373.615739 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25017.028814 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25017.028814 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19489299 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2109542 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1643530 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.854465 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.858195 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 10412623 # number of writebacks -system.cpu.dcache.writebacks::total 10412623 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5753869 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5753869 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15770096 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15770096 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6914 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 6914 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 268040 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 268040 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21530879 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21530879 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21530879 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21530879 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7112407 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7112407 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3099329 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3099329 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2059217 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 2059217 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263923 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1263923 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 284098 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 284098 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 11475659 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 11475659 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 13534876 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 13534876 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 119879387000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 119879387000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164321917838 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 164321917838 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 34890815500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 34890815500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28496186907 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28496186907 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4243086000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4243086000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 260500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 260500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 312697491745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 312697491745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 347588307245 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 347588307245 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225622500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225622500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225622500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225622500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035415 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035415 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016936 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016936 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813743 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813743 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787124 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787124 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052675 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052675 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 7764980 # number of writebacks +system.cpu.dcache.writebacks::total 7764980 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4590646 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4590646 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9875948 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9875948 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6846 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 6846 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 225673 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 225673 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 14473440 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 14473440 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 14473440 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 14473440 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5322473 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5322473 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2094547 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2094547 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1246940 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1246940 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1230045 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1230045 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233828 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 233828 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 8647065 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8647065 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9894005 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9894005 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33590 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33590 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33609 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33609 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67199 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67199 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84299556500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84299556500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 70150658430 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 70150658430 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22795031000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22795031000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26312863405 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26312863405 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3251889000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3251889000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 275500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 275500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 180763078335 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 180763078335 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203558109335 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 203558109335 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6204454000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6204454000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6204454000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6204454000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032990 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032990 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014553 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014553 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.759206 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.759206 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786943 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786943 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059665 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059665 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029773 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029773 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034887 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16854.967242 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16854.967242 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53018.546220 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53018.546220 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16943.729340 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16943.729340 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22545.825107 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22545.825107 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14935.289935 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14935.289935 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32562.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32562.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27248.761204 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27248.761204 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25680.937693 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25680.937693 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184780.437493 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184780.437493 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92375.139105 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92375.139105 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16945634 # number of replacements -system.cpu.icache.tags.tagsinuse 511.953469 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 446936468 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16946146 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.373930 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13767479500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.953469 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028183 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028183 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032075 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032075 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15838.418814 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15838.418814 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33492.043115 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33492.043115 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18280.776140 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18280.776140 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21391.789248 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21391.789248 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13907.183913 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13907.183913 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 30611.111111 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 30611.111111 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20904.558753 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20904.558753 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20573.883815 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20573.883815 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184711.342662 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184711.342662 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92329.558476 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92329.558476 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 15304958 # number of replacements +system.cpu.icache.tags.tagsinuse 511.969276 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 317502771 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15305470 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20.744399 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 12156673500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.969276 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999940 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999940 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 481618789 # Number of tag accesses -system.cpu.icache.tags.data_accesses 481618789 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 446936468 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 446936468 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 446936468 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 446936468 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 446936468 # number of overall hits -system.cpu.icache.overall_hits::total 446936468 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17735952 # 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average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 20885 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1467 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1543 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.366053 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.535321 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16945634 # number of writebacks -system.cpu.icache.writebacks::total 16945634 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 789581 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 789581 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 789581 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 789581 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 789581 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 789581 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16946371 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16946371 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16946371 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16946371 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16946371 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16946371 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 213535123378 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 213535123378 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 213535123378 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 213535123378 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 213535123378 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 213535123378 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1752662500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1752662500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1752662500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 1752662500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036470 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.036470 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.036470 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12600.640183 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12600.640183 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12600.640183 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12600.640183 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12600.640183 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12600.640183 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82307.809712 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82307.809712 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2400192 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65402.662910 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 59310777 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2462586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.084754 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2677803000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9273.019739 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 380.440424 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.878818 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6709.693607 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48618.630322 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.141495 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005805 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006422 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.102382 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.741861 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 239 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 998 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5581 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55200 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003647 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948410 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 508162919 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 508162919 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1310607 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 311860 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1622467 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 10412623 # 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number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193058693887 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 193058693887 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 193058693887 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 193058693887 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 193058693887 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 193058693887 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 174071500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 174071500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 174071500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 174071500 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82639387661 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 147896500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5784421000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5932317500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 147896500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5784421000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 5932317500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007008 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093933 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093933 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.375000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.375000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436995 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436995 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005649 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.046998 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.046998 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.469451 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.469451 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142766 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.061147 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142766 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.061147 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115403.908629 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19072.531242 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19072.531242 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.136873 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.136873 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005674 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039477 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039477 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407427 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407427 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.084207 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.033301 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.084207 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.033301 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 96862.532808 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19077.308256 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19077.308256 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 54333.333333 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 54333.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94885.979578 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94885.979578 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99416.421686 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99416.421686 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101263.521197 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101263.521197 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.655013 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.655013 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99416.421686 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96469.885007 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96814.358355 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99416.421686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96469.885007 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96814.358355 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172276.222842 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.078493 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.052229 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82206.564512 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 62406736 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 31684635 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4771 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2157 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2157 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93768.097075 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93768.097075 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101217.967215 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101217.967215 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105286.332245 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105286.332245 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20912.486984 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20912.486984 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101217.967215 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 97907.874245 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 98240.114291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101217.967215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 97907.874245 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 98240.114291 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70628.701051 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172206.638881 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166245.866495 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70628.701051 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86078.974389 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85612.074813 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 51553426 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26149596 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7713 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1993 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1993 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 2262463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28648866 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 12540349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16945634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3634849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43449 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43457 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3072370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3072370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 16946371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 9441630 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1296845 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1263929 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50880736 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41548571 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 789343 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3060305 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 96278955 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2169414432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467392114 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2566504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10570864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3649943914 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 3001846 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 140762320 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 35497041 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.026133 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.159532 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1662998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23767979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8824066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 15304958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2522010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 29914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 29923 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2069369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2069369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15305703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6801111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1260813 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1230062 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45920340 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30488261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 721887 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1992767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 79123255 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959102240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1064742138 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2294120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6404600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3032543098 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1823037 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 72164080 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 28412224 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025596 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.157926 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 34569387 97.39% 97.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 927654 2.61% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 27684996 97.44% 97.44% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 727226 2.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 35497041 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 59266206483 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 28412224 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 49353009980 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1503389 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1469889 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25451406259 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22969214259 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19476952327 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13985386089 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 468902194 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 435462274 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1739672503 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1192643074 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40306 # Transaction distribution -system.iobus.trans_dist::ReadResp 40306 # Transaction distribution -system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 136571 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40205 # Transaction distribution +system.iobus.trans_dist::ReadResp 40205 # Transaction distribution +system.iobus.trans_dist::WriteReq 136485 # Transaction distribution +system.iobus.trans_dist::WriteResp 136485 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1646,13 +1639,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230940 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1665,21 +1658,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334192 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41898000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7491768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41589500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 340000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 341500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1691,77 +1684,77 @@ system.iobus.reqLayer15.occupancy 9500 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25176500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25178000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36502500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36502000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568938305 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568968268 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147700000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115466 # number of replacements -system.iocache.tags.tagsinuse 10.450358 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115451 # number of replacements +system.iocache.tags.tagsinuse 10.420620 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115467 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13091904723000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.528286 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.922072 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220518 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432629 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13090295539000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.547144 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.873475 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221697 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429592 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651289 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039722 # Number of tag accesses -system.iocache.tags.data_accesses 1039722 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039587 # Number of tag accesses +system.iocache.tags.data_accesses 1039587 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8858 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8806 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8843 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115485 # number of demand (read+write) misses -system.iocache.demand_misses::total 115525 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115470 # number of demand (read+write) misses +system.iocache.demand_misses::total 115510 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115485 # number of overall misses -system.iocache.overall_misses::total 115525 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1915316073 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1920401573 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115470 # number of overall misses +system.iocache.overall_misses::total 115510 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1876442585 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1881528585 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13385817732 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13385817732 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15301133805 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15306570305 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15301133805 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15306570305 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13387619683 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13387619683 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15264062268 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15269499268 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15264062268 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15269499268 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8806 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8843 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115485 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115525 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115470 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115510 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115485 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115525 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115470 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115510 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1775,53 +1768,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217131.399274 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 216798.551930 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 213086.825460 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 212770.392966 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125495.178617 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125495.178617 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 132494.556046 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 132495.739494 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 132494.556046 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 132495.739494 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 46527 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125512.072330 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125512.072330 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 132190.718524 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 132192.011670 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 132190.718524 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 132192.011670 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 45104 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3437 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3423 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.537096 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.176746 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8821 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8858 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8806 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8843 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115485 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115525 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115470 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115510 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115485 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115525 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1474266073 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1477501573 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115470 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115510 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1436142585 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1439378585 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8047307820 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8047307820 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9521573893 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9525010393 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9521573893 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9525010393 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8048941203 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8048941203 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9485083788 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9488520788 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9485083788 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9488520788 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1835,96 +1828,96 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167131.399274 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 166798.551930 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163086.825460 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 162770.392966 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75445.396947 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75445.396947 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 82448.576811 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82449.776178 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 82448.576811 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82449.776178 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 5129530 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2552281 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3338 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75460.710296 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75460.710296 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 82143.273474 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82144.583049 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 82143.273474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82144.583049 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 2825507 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1398744 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3574 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 54986 # Transaction distribution -system.membus.trans_dist::ReadResp 622896 # Transaction distribution -system.membus.trans_dist::WriteReq 33703 # Transaction distribution -system.membus.trans_dist::WriteResp 33703 # Transaction distribution -system.membus.trans_dist::WritebackDirty 2234356 # Transaction distribution -system.membus.trans_dist::CleanEvict 280040 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4640 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 35684 # Transaction distribution +system.membus.trans_dist::ReadResp 407371 # Transaction distribution +system.membus.trans_dist::WriteReq 33609 # Transaction distribution +system.membus.trans_dist::WriteResp 33609 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1165716 # Transaction distribution +system.membus.trans_dist::CleanEvict 197310 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4655 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 1342054 # Transaction distribution -system.membus.trans_dist::ReadExResp 1342054 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 567911 # Transaction distribution -system.membus.trans_dist::InvalidateReq 700014 # Transaction distribution -system.membus.trans_dist::InvalidateResp 32639 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 477795 # Transaction distribution +system.membus.trans_dist::ReadExResp 477795 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 371688 # Transaction distribution +system.membus.trans_dist::InvalidateReq 607818 # Transaction distribution +system.membus.trans_dist::InvalidateResp 30461 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6846190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6975852 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7213520 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6852 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3443320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3572590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237411 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237411 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3810001 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258164108 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 258334162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7251648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7251648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 265585810 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 35487 # Total snoops (count) -system.membus.snoopTraffic 181760 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2703311 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013318 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.114632 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 121594060 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 121763674 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7237120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7237120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 129000794 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 33521 # Total snoops (count) +system.membus.snoopTraffic 195328 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1531252 # Request fanout histogram +system.membus.snoop_fanout::mean 0.022242 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.147469 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2667309 98.67% 98.67% # Request fanout histogram -system.membus.snoop_fanout::1 36002 1.33% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1497194 97.78% 97.78% # Request fanout histogram +system.membus.snoop_fanout::1 34058 2.22% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2703311 # Request fanout histogram -system.membus.reqLayer0.occupancy 104009500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1531252 # Request fanout histogram +system.membus.reqLayer0.occupancy 103704000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5608500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5582500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 14476553313 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7711716413 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10180600996 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4552014688 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 79038203 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 76660254 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1934,11 +1927,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1967,30 +1960,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 17163 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16273 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index af7693171..6bd1757fc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.177074 # Number of seconds simulated -sim_ticks 47177073828000 # Number of ticks simulated -final_tick 47177073828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.256223 # Number of seconds simulated +sim_ticks 47256222864000 # Number of ticks simulated +final_tick 47256222864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1523218 # Simulator instruction rate (inst/s) -host_op_rate 1791835 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73539001789 # Simulator tick rate (ticks/s) -host_mem_usage 696552 # Number of bytes of host memory used -host_seconds 641.52 # Real time elapsed on the host -sim_insts 977181439 # Number of instructions simulated -sim_ops 1149505972 # Number of ops (including micro ops) simulated +host_inst_rate 1686655 # Simulator instruction rate (inst/s) +host_op_rate 2012712 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87867845670 # Simulator tick rate (ticks/s) +host_mem_usage 696856 # Number of bytes of host memory used +host_seconds 537.81 # Real time elapsed on the host +sim_insts 907100218 # Number of instructions simulated +sim_ops 1082456754 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 157952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 131712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4192628 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35968392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 222400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 221568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3097544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 39307632 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 413888 # Number of bytes read from this memory -system.physmem.bytes_read::total 83713716 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4192628 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3097544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7290172 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 102127744 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 160064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 126784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3921972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 37880648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 245824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 244416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3131208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 41316208 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428544 # Number of bytes read from this memory +system.physmem.bytes_read::total 87455668 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3921972 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3131208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7053180 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 106476736 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 102148328 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2058 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 105917 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 562019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3475 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3462 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 48506 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 614198 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6467 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1348570 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1595746 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 106497320 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 65688 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 591898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3841 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3819 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 49032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 645582 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6696 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1371038 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1663699 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1598320 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 88870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 762413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 65658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 833194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1774458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 88870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 65658 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 154528 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2164775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1666273 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 801601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 5202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 5172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 66260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 874302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1850670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 66260 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 149254 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2253179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2165211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2164775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 88870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 762849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 65658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 833194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3939669 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.physmem.bw_write::total 2253615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2253179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 802037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 5202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 5172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 66260 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 874302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4104285 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -100,9 +100,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -110,7 +110,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -140,47 +140,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 123270 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 123270 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 123270 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 123270 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 123270 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 94962 90.03% 90.03% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10516 9.97% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 105478 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123270 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 130714 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 130714 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 130714 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 130714 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 130714 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 3646000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 3646000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 3646000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 100196 89.16% 89.16% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 12181 10.84% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 112377 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 130714 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123270 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 105478 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 130714 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 112377 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 105478 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 228748 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 112377 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 243091 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 90958252 # DTB read hits -system.cpu0.dtb.read_misses 87293 # DTB read misses -system.cpu0.dtb.write_hits 84301704 # DTB write hits -system.cpu0.dtb.write_misses 35977 # DTB write misses +system.cpu0.dtb.read_hits 93175374 # DTB read hits +system.cpu0.dtb.read_misses 92435 # DTB read misses +system.cpu0.dtb.write_hits 86370526 # DTB write hits +system.cpu0.dtb.write_misses 38279 # DTB write misses system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35878 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36393 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5554 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5252 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10284 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91045545 # DTB read accesses -system.cpu0.dtb.write_accesses 84337681 # DTB write accesses +system.cpu0.dtb.perms_faults 10620 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 93267809 # DTB read accesses +system.cpu0.dtb.write_accesses 86408805 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 175259956 # DTB hits -system.cpu0.dtb.misses 123270 # DTB misses -system.cpu0.dtb.accesses 175383226 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 179545900 # DTB hits +system.cpu0.dtb.misses 130714 # DTB misses +system.cpu0.dtb.accesses 179676614 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -210,468 +210,466 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 60279 # Table walker walks requested -system.cpu0.itb.walker.walksLong 60279 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 60279 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 60279 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 60279 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54211 98.84% 98.84% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 635 1.16% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 54846 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 60670 # Table walker walks requested +system.cpu0.itb.walker.walksLong 60670 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 60670 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 60670 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 60670 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 3644500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3644500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 3644500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 54534 98.81% 98.81% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 657 1.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 55191 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60279 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60279 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60670 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60670 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54846 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54846 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 115125 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 489463139 # ITB inst hits -system.cpu0.itb.inst_misses 60279 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55191 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55191 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 115861 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 460432126 # ITB inst hits +system.cpu0.itb.inst_misses 60670 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24716 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25186 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 489523418 # ITB inst accesses -system.cpu0.itb.hits 489463139 # DTB hits -system.cpu0.itb.misses 60279 # DTB misses -system.cpu0.itb.accesses 489523418 # DTB accesses -system.cpu0.numPwrStateTransitions 26258 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13129 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3571424062.507959 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 90351330790.457672 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3131 23.85% 23.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9971 75.95% 99.79% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 460492796 # ITB inst accesses +system.cpu0.itb.hits 460432126 # DTB hits +system.cpu0.itb.misses 60670 # DTB misses +system.cpu0.itb.accesses 460492796 # DTB accesses +system.cpu0.numPwrStateTransitions 26581 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13288 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3535659625.946418 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 88810636016.861053 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3229 24.30% 24.30% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 10032 75.50% 99.80% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7510114609000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13129 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 287847311333 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46889226516667 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94354160786 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7390911651500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13288 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 274377754424 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46981845109576 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94512459022 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13129 # number of quiesce instructions executed -system.cpu0.committedInsts 489228722 # Number of instructions committed -system.cpu0.committedOps 575357792 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 527304848 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 518985 # Number of float alu accesses -system.cpu0.num_func_calls 28507888 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 75158499 # number of instructions that are conditional controls -system.cpu0.num_int_insts 527304848 # number of integer instructions -system.cpu0.num_fp_insts 518985 # number of float instructions -system.cpu0.num_int_register_reads 772493030 # number of times the integer registers were read -system.cpu0.num_int_register_writes 418386904 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 837696 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 439396 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 131494560 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 131170441 # number of times the CC registers were written -system.cpu0.num_mem_refs 175360180 # number of memory refs -system.cpu0.num_load_insts 91031152 # Number of load instructions -system.cpu0.num_store_insts 84329028 # Number of store instructions -system.cpu0.num_idle_cycles 93778466083.220322 # Number of idle cycles -system.cpu0.num_busy_cycles 575694702.779680 # Number of busy cycles -system.cpu0.not_idle_fraction 0.006101 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.993899 # Percentage of idle cycles -system.cpu0.Branches 109461640 # Number of branches fetched +system.cpu0.kern.inst.quiesce 13293 # number of quiesce instructions executed +system.cpu0.committedInsts 460154624 # Number of instructions committed +system.cpu0.committedOps 548413661 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 509180687 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 522850 # Number of float alu accesses +system.cpu0.num_func_calls 28957516 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 67014933 # number of instructions that are conditional controls +system.cpu0.num_int_insts 509180687 # number of integer instructions +system.cpu0.num_fp_insts 522850 # number of float instructions +system.cpu0.num_int_register_reads 679939222 # number of times the integer registers were read +system.cpu0.num_int_register_writes 397756518 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 842282 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 446532 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 104721942 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 104390194 # number of times the CC registers were written +system.cpu0.num_mem_refs 179652770 # number of memory refs +system.cpu0.num_load_insts 93252874 # Number of load instructions +system.cpu0.num_store_insts 86399896 # Number of store instructions +system.cpu0.num_idle_cycles 93963703435.962769 # Number of idle cycles +system.cpu0.num_busy_cycles 548755586.037238 # Number of busy cycles +system.cpu0.not_idle_fraction 0.005806 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.994194 # Percentage of idle cycles +system.cpu0.Branches 101918794 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 398983706 69.31% 69.31% # Class of executed instruction -system.cpu0.op_class::IntMult 1214289 0.21% 69.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 59472 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 8 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 13 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 21 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatMisc 72490 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::MemRead 90970869 15.80% 85.34% # Class of executed instruction -system.cpu0.op_class::MemWrite 83942858 14.58% 99.92% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 60283 0.01% 99.93% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 386170 0.07% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 367730477 67.01% 67.01% # Class of executed instruction +system.cpu0.op_class::IntMult 1235344 0.23% 67.24% # Class of executed instruction +system.cpu0.op_class::IntDiv 59786 0.01% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatAdd 8 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 13 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 21 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMisc 72659 0.01% 67.26% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::MemRead 93191543 16.98% 84.24% # Class of executed instruction +system.cpu0.op_class::MemWrite 86011078 15.67% 99.92% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 61331 0.01% 99.93% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 388818 0.07% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 575690180 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6169123 # number of replacements -system.cpu0.dcache.tags.tagsinuse 502.902441 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169021316 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6169635 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.395675 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.902441 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.982231 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.982231 # Average percentage of cache occupancy +system.cpu0.op_class::total 548751079 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6361267 # number of replacements +system.cpu0.dcache.tags.tagsinuse 499.577143 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 173125033 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6361779 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.213305 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 13850500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.577143 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975737 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.975737 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 356856913 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 356856913 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 84588460 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 84588460 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79569773 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 79569773 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213774 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 213774 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259782 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 259782 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2069774 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2069774 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2033350 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2033350 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164418015 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164418015 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 164631789 # number of overall hits -system.cpu0.dcache.overall_hits::total 164631789 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3250756 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3250756 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1461940 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1461940 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 763460 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 763460 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 814949 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 814949 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 115689 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 115689 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 151036 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 151036 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5527645 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5527645 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6291105 # number of overall misses -system.cpu0.dcache.overall_misses::total 6291105 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87839216 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 87839216 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81031713 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81031713 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 977234 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 977234 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1074731 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1074731 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2185463 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2185463 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2184386 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2184386 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169945660 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 169945660 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170922894 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 170922894 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037008 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037008 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018042 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018042 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781246 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781246 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.758282 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.758282 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052936 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052936 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.069143 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069143 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032526 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032526 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036807 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036807 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 365631383 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 365631383 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 86603750 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86603750 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 81517458 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 81517458 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 217950 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 217950 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259225 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 259225 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2136353 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2136353 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2100440 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2100440 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 168380433 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 168380433 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 168598383 # number of overall hits +system.cpu0.dcache.overall_hits::total 168598383 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3343142 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3343142 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1509525 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1509525 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 802963 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 802963 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 820079 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 820079 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119939 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 119939 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154648 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 154648 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5672746 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5672746 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6475709 # number of overall misses +system.cpu0.dcache.overall_misses::total 6475709 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89946892 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89946892 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 83026983 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 83026983 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1020913 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1020913 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1079304 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1079304 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2255088 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2255088 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 174053179 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 174053179 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 175074092 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 175074092 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037168 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037168 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018181 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018181 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.786515 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.786515 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759822 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759822 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053158 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053158 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.068577 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.068577 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032592 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032592 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036988 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036988 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6169123 # number of writebacks -system.cpu0.dcache.writebacks::total 6169123 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5445857 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.988996 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 484071611 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5446369 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.879694 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5759898000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.988996 # Average occupied blocks per requestor +system.cpu0.dcache.writebacks::writebacks 6361267 # number of writebacks +system.cpu0.dcache.writebacks::total 6361267 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 5436488 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.989232 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 455050312 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5437000 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 83.695110 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5738328000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989232 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 984482344 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 984482344 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 484071611 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 484071611 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 484071611 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 484071611 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 484071611 # number of overall hits -system.cpu0.icache.overall_hits::total 484071611 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5446374 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5446374 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5446374 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5446374 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5446374 # number of overall misses -system.cpu0.icache.overall_misses::total 5446374 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 489517985 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 489517985 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 489517985 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 489517985 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 489517985 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 489517985 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011126 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011126 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011126 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011126 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011126 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011126 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 926411639 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 926411639 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 455050312 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 455050312 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 455050312 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 455050312 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 455050312 # number of overall hits +system.cpu0.icache.overall_hits::total 455050312 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5437005 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5437005 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5437005 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5437005 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5437005 # number of overall misses +system.cpu0.icache.overall_misses::total 5437005 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 460487317 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 460487317 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 460487317 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 460487317 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 460487317 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 460487317 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011807 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011807 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011807 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011807 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011807 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011807 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5445857 # number of writebacks -system.cpu0.icache.writebacks::total 5445857 # number of writebacks -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 5436488 # number of writebacks +system.cpu0.icache.writebacks::total 5436488 # number of writebacks +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2533357 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15711.685213 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9303903 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2548994 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.650029 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15660.837363 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.957912 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.889938 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.955862 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001890 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001214 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.958965 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15585 # Occupied blocks per task id +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2619867 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15716.053325 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9431762 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2635628 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.578563 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 269403000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15665.638757 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.618352 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.796216 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.956155 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001869 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001208 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.959232 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15683 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 61 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2073 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5396 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5335 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2374 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.951233 # 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number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20714 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10073 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 488475 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1907459 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2426721 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 301783 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 162502 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 464285 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4385344 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4385344 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 7228256 # 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number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4129905 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 814949 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 814949 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 301783 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 162502 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5446374 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5456881 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11367540 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 301783 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 162502 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5446374 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5456881 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11367540 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.061987 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.066311 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2189 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5717 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5104 # 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number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 322156 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164538 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5437005 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5640907 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11564606 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.061506 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.064367 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.526132 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.526132 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089688 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089688 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.292814 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.292814 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.735636 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.735636 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.061987 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089688 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.349551 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.213478 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.061987 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089688 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.349551 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.213478 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.531347 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.531347 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.091453 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.091453 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.291997 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.291997 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.728766 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.728766 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.061506 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.091453 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350334 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.216588 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.061506 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.091453 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350334 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.216588 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 1537445 # number of writebacks -system.cpu0.l2cache.writebacks::total 1537445 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 23876126 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12158327 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1385 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 304592 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 304592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.l2cache.writebacks::writebacks 1595934 # number of writebacks +system.cpu0.l2cache.writebacks::total 1595934 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 24251358 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12353916 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1372 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 295344 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 295344 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 614484 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10190763 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32444 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32444 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 4385344 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7229636 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 134964 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 151036 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 286000 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1326976 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1326976 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5446374 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4129905 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 814949 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 814949 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16424855 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19414693 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 360152 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 717544 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 36917244 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 697275284 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 744257581 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1440608 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2870176 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1445843649 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4732413 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 102900484 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 28818191 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.019582 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.138557 # Request fanout histogram +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 597776 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10300825 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32321 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32321 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4541229 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7256526 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 134662 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154648 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 289310 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1374863 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1374863 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5437005 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4266044 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 820079 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 820079 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16319948 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19991301 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362448 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 758854 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37432551 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 695922452 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 768331945 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1449792 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3035416 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1468739605 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4809457 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 106507396 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 29250499 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.019295 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.137560 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 28253885 98.04% 98.04% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 564306 1.96% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 28686107 98.07% 98.07% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 564392 1.93% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 28818191 # Request fanout histogram -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.snoop_fanout::total 29250499 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -701,47 +699,47 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 145570 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 145570 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 145570 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 145570 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 145570 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walksPending::samples -274399872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -274399872 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -274399872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 112948 88.82% 88.82% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 14218 11.18% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 127166 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145570 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 149830 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 149830 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 149830 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 149830 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 149830 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -295973872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -295973872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -295973872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 115525 88.27% 88.27% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 15355 11.73% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 130880 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 149830 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145570 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 127166 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 149830 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 130880 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 127166 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 272736 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 130880 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 280710 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 92188600 # DTB read hits -system.cpu1.dtb.read_misses 112898 # DTB read misses -system.cpu1.dtb.write_hits 82869602 # DTB write hits -system.cpu1.dtb.write_misses 32672 # DTB write misses +system.cpu1.dtb.read_hits 93113840 # DTB read hits +system.cpu1.dtb.read_misses 115970 # DTB read misses +system.cpu1.dtb.write_hits 83725509 # DTB write hits +system.cpu1.dtb.write_misses 33860 # DTB write misses system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44985 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 45912 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4483 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4582 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11594 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 92301498 # DTB read accesses -system.cpu1.dtb.write_accesses 82902274 # DTB write accesses +system.cpu1.dtb.perms_faults 11647 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 93229810 # DTB read accesses +system.cpu1.dtb.write_accesses 83759369 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 175058202 # DTB hits -system.cpu1.dtb.misses 145570 # DTB misses -system.cpu1.dtb.accesses 175203772 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 176839349 # DTB hits +system.cpu1.dtb.misses 149830 # DTB misses +system.cpu1.dtb.accesses 176989179 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -771,471 +769,467 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 62174 # Table walker walks requested -system.cpu1.itb.walker.walksLong 62174 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 62174 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 62174 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 62174 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walksPending::samples -274400872 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -274400872 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -274400872 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 55194 99.03% 99.03% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 542 0.97% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55736 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 62588 # Table walker walks requested +system.cpu1.itb.walker.walksLong 62588 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 62588 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 62588 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 62588 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -295974872 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -295974872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -295974872 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 55491 99.07% 99.07% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 523 0.93% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 56014 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62174 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62174 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62588 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62588 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55736 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55736 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 117910 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 488205248 # ITB inst hits -system.cpu1.itb.inst_misses 62174 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56014 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56014 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 118602 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 447202663 # ITB inst hits +system.cpu1.itb.inst_misses 62588 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31602 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 32344 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 488267422 # ITB inst accesses -system.cpu1.itb.hits 488205248 # DTB hits -system.cpu1.itb.misses 62174 # DTB misses -system.cpu1.itb.accesses 488267422 # DTB accesses -system.cpu1.numPwrStateTransitions 12500 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 6250 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 7502374904.322560 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 140163345879.751923 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4511 72.18% 72.18% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1712 27.39% 99.57% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.11% 99.68% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.05% 99.76% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 447265251 # ITB inst accesses +system.cpu1.itb.hits 447202663 # DTB hits +system.cpu1.itb.misses 62588 # DTB misses +system.cpu1.itb.accesses 447265251 # DTB accesses +system.cpu1.numPwrStateTransitions 12622 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 6311 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 7445577920.705118 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 138960729730.016388 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4567 72.37% 72.37% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1718 27.22% 99.59% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.67% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 3 0.05% 99.71% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.75% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.03% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 13 0.21% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7033264907012 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 6250 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 287230675984 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46889843152016 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94354153907 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 6953792880276 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 6311 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 267180606430 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46989042257570 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94512452040 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6250 # number of quiesce instructions executed -system.cpu1.committedInsts 487952717 # Number of instructions committed -system.cpu1.committedOps 574148180 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 526945204 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 380393 # Number of float alu accesses -system.cpu1.num_func_calls 28766283 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 74749330 # number of instructions that are conditional controls -system.cpu1.num_int_insts 526945204 # number of integer instructions -system.cpu1.num_fp_insts 380393 # number of float instructions -system.cpu1.num_int_register_reads 777937433 # number of times the integer registers were read -system.cpu1.num_int_register_writes 419402413 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 618522 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 309432 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 129016491 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 128726040 # number of times the CC registers were written -system.cpu1.num_mem_refs 175180123 # number of memory refs -system.cpu1.num_load_insts 92288401 # Number of load instructions -system.cpu1.num_store_insts 82891722 # Number of store instructions -system.cpu1.num_idle_cycles 93779692516.971710 # Number of idle cycles -system.cpu1.num_busy_cycles 574461390.028282 # Number of busy cycles -system.cpu1.not_idle_fraction 0.006088 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.993912 # Percentage of idle cycles -system.cpu1.Branches 108727125 # Number of branches fetched +system.cpu1.kern.inst.quiesce 6311 # number of quiesce instructions executed +system.cpu1.committedInsts 446945594 # Number of instructions committed +system.cpu1.committedOps 534043093 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 497796457 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 375258 # Number of float alu accesses +system.cpu1.num_func_calls 29044812 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 64056743 # number of instructions that are conditional controls +system.cpu1.num_int_insts 497796457 # number of integer instructions +system.cpu1.num_fp_insts 375258 # number of float instructions +system.cpu1.num_int_register_reads 659899184 # number of times the integer registers were read +system.cpu1.num_int_register_writes 389220604 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 611056 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 302696 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 95980638 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 95700174 # number of times the CC registers were written +system.cpu1.num_mem_refs 176965712 # number of memory refs +system.cpu1.num_load_insts 93216701 # Number of load instructions +system.cpu1.num_store_insts 83749011 # Number of store instructions +system.cpu1.num_idle_cycles 93978090791.450775 # Number of idle cycles +system.cpu1.num_busy_cycles 534361248.549225 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005654 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994346 # Percentage of idle cycles +system.cpu1.Branches 98364194 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 398021787 69.29% 69.29% # Class of executed instruction -system.cpu1.op_class::IntMult 1155567 0.20% 69.49% # Class of executed instruction -system.cpu1.op_class::IntDiv 62024 0.01% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatMisc 37076 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::MemRead 92237466 16.06% 85.56% # Class of executed instruction -system.cpu1.op_class::MemWrite 82599340 14.38% 99.94% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 50935 0.01% 99.95% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 292382 0.05% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 356129610 66.65% 66.65% # Class of executed instruction +system.cpu1.op_class::IntMult 1162336 0.22% 66.86% # Class of executed instruction +system.cpu1.op_class::IntDiv 62196 0.01% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatMisc 36452 0.01% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::MemRead 93166406 17.44% 84.32% # Class of executed instruction +system.cpu1.op_class::MemWrite 83460500 15.62% 99.94% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 50295 0.01% 99.95% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 288511 0.05% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 574456577 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 6056013 # number of replacements -system.cpu1.dcache.tags.tagsinuse 439.385542 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 169014740 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 6056525 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.906223 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8470277781000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 439.385542 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.858175 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.858175 # Average percentage of cache occupancy +system.cpu1.op_class::total 534356306 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 6135169 # number of replacements +system.cpu1.dcache.tags.tagsinuse 439.724728 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 170720636 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 6135681 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.824236 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8470256211500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 439.724728 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.858837 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.858837 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 356467951 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 356467951 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 85651314 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 85651314 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 78663816 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 78663816 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 189367 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 189367 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 66166 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 66166 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2074874 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 2074874 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2069738 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2069738 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 164381296 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 164381296 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 164570663 # number of overall hits -system.cpu1.dcache.overall_hits::total 164570663 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3417226 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3417226 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1481686 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1481686 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 799274 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 799274 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 443256 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 443256 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150141 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 150141 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 154039 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 154039 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5342168 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5342168 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6141442 # number of overall misses -system.cpu1.dcache.overall_misses::total 6141442 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 89068540 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 89068540 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 80145502 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 80145502 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 988641 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 988641 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 509422 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 509422 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2225015 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2225015 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2223777 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2223777 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 169723464 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 169723464 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 170712105 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 170712105 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038366 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038366 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018487 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018487 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808457 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808457 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870116 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870116 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067479 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067479 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.069269 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.069269 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031476 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031476 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035975 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035975 # miss rate for overall accesses +system.cpu1.dcache.tags.tag_accesses 360116437 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 360116437 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 86463703 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 86463703 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 79472088 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 79472088 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 192310 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 192310 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 67346 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 67346 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2116228 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2116228 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2109994 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2109994 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 166003137 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 166003137 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 166195447 # number of overall hits +system.cpu1.dcache.overall_hits::total 166195447 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3476659 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3476659 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1488439 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1488439 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 809340 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 809340 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 440862 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 440862 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 151875 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 151875 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156847 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 156847 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5405960 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5405960 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6215300 # number of overall misses +system.cpu1.dcache.overall_misses::total 6215300 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 89940362 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 89940362 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 80960527 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 80960527 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 1001650 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 1001650 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 508208 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 508208 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2268103 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2268103 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2266841 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2266841 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 171409097 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 171409097 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 172410747 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 172410747 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038655 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038655 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018385 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018385 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808007 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808007 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.867483 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.867483 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066961 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066961 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.069192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.069192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031538 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031538 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036049 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.036049 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 6056013 # number of writebacks -system.cpu1.dcache.writebacks::total 6056013 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 4848965 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.412961 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 483411507 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4849477 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 99.683225 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8470205818500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.412961 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969557 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969557 # Average percentage of cache occupancy +system.cpu1.dcache.writebacks::writebacks 6135169 # number of writebacks +system.cpu1.dcache.writebacks::total 6135169 # number of writebacks +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 4821762 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.439302 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 442436403 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4822274 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 91.748499 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8470184249000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439302 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 146 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 981371445 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 981371445 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 483411507 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 483411507 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 483411507 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 483411507 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 483411507 # number of overall hits -system.cpu1.icache.overall_hits::total 483411507 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4849477 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4849477 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4849477 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4849477 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4849477 # number of overall misses -system.cpu1.icache.overall_misses::total 4849477 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 488260984 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 488260984 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 488260984 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 488260984 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 488260984 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 488260984 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009932 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009932 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009932 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009932 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009932 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009932 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 899339628 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 899339628 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 442436403 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 442436403 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 442436403 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 442436403 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 442436403 # number of overall hits +system.cpu1.icache.overall_hits::total 442436403 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4822274 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4822274 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4822274 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4822274 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4822274 # number of overall misses +system.cpu1.icache.overall_misses::total 4822274 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 447258677 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 447258677 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 447258677 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 447258677 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 447258677 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 447258677 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010782 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.010782 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010782 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.010782 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010782 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.010782 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 4848965 # number of writebacks -system.cpu1.icache.writebacks::total 4848965 # number of writebacks -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.writebacks::writebacks 4821762 # number of writebacks +system.cpu1.icache.writebacks::total 4821762 # number of writebacks +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2230269 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13059.321303 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 8938644 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2245943 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 3.979907 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2257136 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13044.860493 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 8980176 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2273016 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 3.950776 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 13021.698131 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 21.453000 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.170172 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.794781 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001309 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000987 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.797078 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15589 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2501 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7586 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3485 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1787 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.951477 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 374536552 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 374536552 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 340661 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155597 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 496258 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 4122422 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 4122422 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6782171 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6782171 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 622232 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 622232 # 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number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155597 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4374488 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3759887 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8630633 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22356 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11279 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 33635 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145163 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 145163 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 154039 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 154039 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 714291 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 714291 # 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number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22356 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11279 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 474989 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1943277 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2451901 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 363017 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 166876 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 529893 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4122422 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 4122422 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 6782171 # 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number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4849477 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5703164 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 11082534 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.061584 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.067589 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.063475 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 13005.388479 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 22.571640 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.900374 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.793786 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001378 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001032 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.796195 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15820 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 29 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 398 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7364 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3549 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1830 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.965576 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 376404615 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 376404615 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 350077 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155851 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 505928 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 4161473 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 4161473 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 6795092 # 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miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097946 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.340737 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.221240 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.061584 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.067589 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097946 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.340737 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.221240 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538644 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538644 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097638 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097638 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.280424 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.280424 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620963 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620963 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.068824 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097638 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.340535 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.222030 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.068824 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097638 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.340535 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.222030 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 1226637 # number of writebacks -system.cpu1.l2cache.writebacks::total 1226637 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 22478068 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11482434 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 385 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 282472 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 282472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.writebacks::writebacks 1247214 # number of writebacks +system.cpu1.l2cache.writebacks::total 1247214 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 22589206 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11541877 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 366 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 281509 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 281509 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 614190 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9830308 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6354 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6354 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4122422 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6782556 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 145163 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 154039 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 299202 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1336523 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1336523 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4849477 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4366641 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 443256 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 443256 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14548179 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18972689 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371656 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 843740 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34736264 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 620700808 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 752625722 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1486624 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3374960 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1378188114 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4390439 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 84812544 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 27053766 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.020745 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.142530 # Request fanout histogram +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 627108 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9887256 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6357 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6357 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4161473 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6795458 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 141879 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156847 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 298726 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1346560 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1346560 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4822274 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4437874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 440862 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 440862 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14466570 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 19208649 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 374184 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 867050 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34916453 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 617218824 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 762892902 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1496736 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3468200 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1385076662 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4471176 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 86426880 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 27252775 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.020850 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.142882 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 26492533 97.93% 97.93% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 561233 2.07% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 26684555 97.92% 97.92% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 568220 2.08% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 27053766 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40293 # Transaction distribution -system.iobus.trans_dist::ReadResp 40293 # Transaction distribution -system.iobus.trans_dist::WriteReq 136632 # Transaction distribution -system.iobus.trans_dist::WriteResp 136632 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47630 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.snoop_fanout::total 27252775 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40208 # Transaction distribution +system.iobus.trans_dist::ReadResp 40208 # Transaction distribution +system.iobus.trans_dist::WriteReq 136550 # Transaction distribution +system.iobus.trans_dist::WriteResp 136550 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47302 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1248,13 +1242,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122564 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231206 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122236 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47650 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353516 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47322 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1267,56 +1261,56 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155671 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338840 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155343 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496597 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115584 # number of replacements -system.iocache.tags.tagsinuse 11.285245 # Cycle average of tags in use +system.iobus.pkt_size::total 7496245 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115580 # number of replacements +system.iocache.tags.tagsinuse 11.294790 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115600 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115596 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9107772860509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.859437 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.425808 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.241215 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.464113 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705328 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9107754177509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.848737 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.446053 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240546 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465378 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705924 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040784 # Number of tag accesses -system.iocache.tags.data_accesses 1040784 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040757 # Number of tag accesses +system.iocache.tags.data_accesses 1040757 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115603 # number of demand (read+write) misses -system.iocache.demand_misses::total 115643 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115600 # number of demand (read+write) misses +system.iocache.demand_misses::total 115640 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115603 # number of overall misses -system.iocache.overall_misses::total 115643 # number of overall misses +system.iocache.overall_misses::realview.ide 115600 # number of overall misses +system.iocache.overall_misses::total 115640 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8875 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115603 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115643 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115600 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115640 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115603 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115643 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115600 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115640 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1336,282 +1330,281 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1923250 # number of replacements -system.l2c.tags.tagsinuse 65186.498545 # Cycle average of tags in use -system.l2c.tags.total_refs 5749330 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1985687 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.895386 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 477350500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 10983.634083 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 57.375221 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 60.020702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3162.214163 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 16603.028209 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 344.016385 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 410.384147 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2922.724883 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 30643.100751 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.167597 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000916 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.048252 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.253342 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005249 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006262 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.044597 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.467577 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994667 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 241 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62196 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3250 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4725 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53923 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003677 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.949036 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 71541788 # Number of tag accesses -system.l2c.tags.data_accesses 71541788 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2764082 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2764082 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 56104 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 51044 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 107148 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 8413 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7881 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16294 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 200040 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 182839 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 382879 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12914 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5340 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 425659 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 696237 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12397 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4498 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 426584 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 681796 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2265425 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 112817 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 103406 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 216223 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 12914 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5340 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 425659 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 896277 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 12397 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4498 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 426584 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 864635 # number of demand (read+write) hits -system.l2c.demand_hits::total 2648304 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 12914 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5340 # number of overall hits -system.l2c.overall_hits::cpu0.inst 425659 # number of overall hits -system.l2c.overall_hits::cpu0.data 896277 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 12397 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4498 # number of overall hits -system.l2c.overall_hits::cpu1.inst 426584 # number of overall hits -system.l2c.overall_hits::cpu1.data 864635 # number of overall hits -system.l2c.overall_hits::total 2648304 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 19306 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 23056 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 42362 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 403 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 802 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1205 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 372703 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 418393 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 791096 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2468 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2058 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 62816 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 191372 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3475 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3462 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 48405 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 197388 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 511444 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 440136 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 128597 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 568733 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2468 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2058 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 62816 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 564075 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3475 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3462 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 48405 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 615781 # number of demand (read+write) misses -system.l2c.demand_misses::total 1302540 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2468 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2058 # number of overall misses -system.l2c.overall_misses::cpu0.inst 62816 # number of overall misses -system.l2c.overall_misses::cpu0.data 564075 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3475 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3462 # number of overall misses -system.l2c.overall_misses::cpu1.inst 48405 # number of overall misses -system.l2c.overall_misses::cpu1.data 615781 # number of overall misses -system.l2c.overall_misses::total 1302540 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 2764082 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2764082 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 75410 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 74100 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 149510 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 8816 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8683 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17499 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 572743 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 601232 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1173975 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15382 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7398 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 488475 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 887609 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15872 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7960 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 474989 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 879184 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 2776869 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 552953 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 232003 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 784956 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 15382 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7398 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 488475 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1460352 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 15872 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7960 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 474989 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1480416 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3950844 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 15382 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7398 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 488475 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1460352 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 15872 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7960 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 474989 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1480416 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3950844 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.256014 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.311147 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.283339 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.045712 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.092364 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.068861 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.650733 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.695893 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.673861 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.278183 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.128596 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.215604 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.434925 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.101908 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.224513 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.184180 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.795974 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.554290 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.724541 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.278183 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.128596 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.386260 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.434925 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.101908 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.415951 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.329687 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.278183 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.128596 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.386260 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.434925 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.101908 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.415951 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.329687 # miss rate for overall accesses +system.iocache.writebacks::writebacks 106693 # number of writebacks +system.iocache.writebacks::total 106693 # number of writebacks +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 2000796 # number of replacements +system.l2c.tags.tagsinuse 65236.747854 # Cycle average of tags in use +system.l2c.tags.total_refs 5872089 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 2062236 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.847438 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 458916500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10773.265369 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 57.425728 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 60.472796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3088.117960 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 16913.790714 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 343.005231 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 383.707168 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2970.710524 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 30646.252365 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.164387 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000876 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000923 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.047121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.258084 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005234 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.005855 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.045329 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.467625 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995434 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 236 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 61204 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 232 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3527 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4478 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52898 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.933899 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 73224508 # Number of tag accesses +system.l2c.tags.data_accesses 73224508 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2843148 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2843148 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 57335 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 51488 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 108823 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 8370 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 7752 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16122 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 205747 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 172848 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 378595 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13551 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5506 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 436242 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 735903 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12336 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4370 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 421904 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 692405 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2322217 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 112000 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 99469 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 211469 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 13551 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5506 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 436242 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 941650 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 12336 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4370 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 421904 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 865253 # number of demand (read+write) hits +system.l2c.demand_hits::total 2700812 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 13551 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5506 # number of overall hits +system.l2c.overall_hits::cpu0.inst 436242 # number of overall hits +system.l2c.overall_hits::cpu0.data 941650 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 12336 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4370 # number of overall hits +system.l2c.overall_hits::cpu1.inst 421904 # number of overall hits +system.l2c.overall_hits::cpu1.data 865253 # number of overall hits +system.l2c.overall_hits::total 2700812 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 20153 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 22374 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 42527 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 465 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 952 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1417 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 404904 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 443379 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 848283 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2501 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1981 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 60987 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 188974 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3841 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3819 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 48931 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 203657 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 514691 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 441546 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 132806 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 574352 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2501 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1981 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 60987 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 593878 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3841 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3819 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 48931 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 647036 # number of demand (read+write) misses +system.l2c.demand_misses::total 1362974 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2501 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1981 # number of overall misses +system.l2c.overall_misses::cpu0.inst 60987 # number of overall misses +system.l2c.overall_misses::cpu0.data 593878 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3841 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3819 # number of overall misses +system.l2c.overall_misses::cpu1.inst 48931 # number of overall misses +system.l2c.overall_misses::cpu1.data 647036 # number of overall misses +system.l2c.overall_misses::total 1362974 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 2843148 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2843148 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 77488 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 73862 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 151350 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 8835 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8704 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 17539 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 610651 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 616227 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1226878 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16052 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7487 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 924877 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 16177 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 8189 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 470835 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 896062 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 2836908 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 553546 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 232275 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 785821 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 16052 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7487 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1535528 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 16177 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 8189 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 470835 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1512289 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4063786 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 16052 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7487 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1535528 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 16177 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 8189 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 470835 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1512289 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4063786 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.260079 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.302916 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.280984 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.052632 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.109375 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.080791 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.663069 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.719506 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.691416 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.264592 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.122654 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.204323 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.466357 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.103924 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.227280 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.181427 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.797668 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.571762 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.730894 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.264592 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.122654 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.386758 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.466357 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.103924 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.427852 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.335395 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.264592 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.122654 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.386758 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.466357 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.103924 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.427852 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.335395 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1489052 # number of writebacks -system.l2c.writebacks::total 1489052 # number of writebacks -system.membus.snoop_filter.tot_requests 4378272 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2451994 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3422 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.writebacks::writebacks 1557006 # number of writebacks +system.l2c.writebacks::total 1557006 # number of writebacks +system.membus.snoop_filter.tot_requests 4511574 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2519656 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3180 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 82126 # Transaction distribution -system.membus.trans_dist::ReadResp 602482 # Transaction distribution -system.membus.trans_dist::WriteReq 38798 # Transaction distribution -system.membus.trans_dist::WriteResp 38798 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1595746 # Transaction distribution -system.membus.trans_dist::CleanEvict 267406 # Transaction distribution -system.membus.trans_dist::UpgradeReq 230305 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 288781 # Transaction distribution -system.membus.trans_dist::UpgradeResp 46602 # Transaction distribution -system.membus.trans_dist::ReadExReq 791817 # Transaction distribution -system.membus.trans_dist::ReadExResp 788064 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 520356 # Transaction distribution -system.membus.trans_dist::InvalidateReq 683860 # Transaction distribution -system.membus.trans_dist::InvalidateResp 675461 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122564 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 43614 # Transaction distribution +system.membus.trans_dist::ReadResp 567214 # Transaction distribution +system.membus.trans_dist::WriteReq 38678 # Transaction distribution +system.membus.trans_dist::WriteResp 38678 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1663699 # Transaction distribution +system.membus.trans_dist::CleanEvict 266504 # Transaction distribution +system.membus.trans_dist::UpgradeReq 223308 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 295373 # Transaction distribution +system.membus.trans_dist::UpgradeResp 46773 # Transaction distribution +system.membus.trans_dist::ReadExReq 849453 # Transaction distribution +system.membus.trans_dist::ReadExResp 845457 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 523600 # Transaction distribution +system.membus.trans_dist::InvalidateReq 689636 # Transaction distribution +system.membus.trans_dist::InvalidateResp 681080 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122236 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27546 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6153530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6303732 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346870 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346870 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6650602 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155671 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27410 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6276469 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6426207 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6773067 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155343 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 178661596 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 178872563 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7398784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 186271347 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 186738012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 186948379 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7398528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 194346907 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4499195 # Request fanout histogram -system.membus.snoop_fanout::mean 0.007389 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.085643 # Request fanout histogram +system.membus.snoop_fanout::samples 4593865 # Request fanout histogram +system.membus.snoop_fanout::mean 0.007098 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.083952 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4465949 99.26% 99.26% # Request fanout histogram -system.membus.snoop_fanout::1 33246 0.74% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4561256 99.29% 99.29% # Request fanout histogram +system.membus.snoop_fanout::1 32609 0.71% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4499195 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 4593865 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1654,68 +1647,68 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 11103133 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5636149 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1803428 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 289976 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 265298 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 24678 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 82128 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3548294 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38798 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38798 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 2764082 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1999311 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 334418 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 305075 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 639493 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1358165 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1358165 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3466166 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 875913 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 875913 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9373855 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8310864 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17684719 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252267457 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 233795714 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 486063171 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1971827 # Total snoops (count) -system.toL2Bus.snoopTraffic 95347072 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 13179862 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.305132 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.464512 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 11315905 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5737208 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1831359 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 298423 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 272858 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 25565 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 43616 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3567484 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38678 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38678 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 2843148 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2033600 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 329302 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 311495 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 640797 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1403084 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1403084 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3523868 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 871405 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 871405 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9542040 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8377604 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17919644 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 260882877 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 236654062 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 497536939 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2048171 # Total snoops (count) +system.toL2Bus.snoopTraffic 99695936 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 13430913 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.303362 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.463832 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9182942 69.67% 69.67% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3972242 30.14% 99.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 24678 0.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9382052 69.85% 69.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4023296 29.96% 99.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 25565 0.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13179862 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 13430913 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 203bf8cf0..81cebbb77 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.548252 # Number of seconds simulated -sim_ticks 51548252400500 # Number of ticks simulated -final_tick 51548252400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.071102 # Number of seconds simulated +sim_ticks 51071102402000 # Number of ticks simulated +final_tick 51071102402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1717705 # Simulator instruction rate (inst/s) -host_op_rate 1880520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48787200192 # Simulator tick rate (ticks/s) -host_mem_usage 679528 # Number of bytes of host memory used -host_seconds 1056.59 # Real time elapsed on the host -sim_insts 1814916572 # Number of instructions simulated -sim_ops 1986945286 # Number of ops (including micro ops) simulated +host_inst_rate 1747137 # Simulator instruction rate (inst/s) +host_op_rate 2084338 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95484785421 # Simulator tick rate (ticks/s) +host_mem_usage 679432 # Number of bytes of host memory used +host_seconds 534.86 # Real time elapsed on the host +sim_insts 934475925 # Number of instructions simulated +sim_ops 1114831373 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 388608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 367808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5292340 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 73326152 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 442368 # Number of bytes read from this memory -system.physmem.bytes_read::total 79817276 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5292340 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5292340 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 101858624 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 487168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 439168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5588020 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 87025992 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439360 # Number of bytes read from this memory +system.physmem.bytes_read::total 93979708 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5588020 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5588020 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 115462912 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 101879204 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6072 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 123100 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1145734 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6912 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1287565 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1591541 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 115483492 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 7612 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 91720 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1359794 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6865 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1472853 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1804108 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1594114 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 102668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1422476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1548399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1975986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1976385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1975986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1422875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3524784 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.physmem.num_writes::total 1806681 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 9539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 8599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 109416 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1704016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1840174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 109416 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 109416 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2260827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2261230 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2260827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 9539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 8599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 109416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1704419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4101404 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -109,47 +109,47 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 267664 # Table walker walks requested -system.cpu.dtb.walker.walksLong 267664 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 267664 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 267664 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 267664 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 206672 89.75% 89.75% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 23595 10.25% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 230267 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 267664 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 297729 # Table walker walks requested +system.cpu.dtb.walker.walksLong 297729 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 297729 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 297729 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 297729 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walksPending::samples 3646000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 3646000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 3646000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 228847 88.79% 88.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 28897 11.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 257744 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 297729 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 267664 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 230267 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 297729 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 257744 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 230267 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 497931 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 257744 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 555473 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 421603994 # DTB read hits -system.cpu.dtb.read_misses 196270 # DTB read misses -system.cpu.dtb.write_hits 167651282 # DTB write hits -system.cpu.dtb.write_misses 71394 # DTB write misses +system.cpu.dtb.read_hits 192113611 # DTB read hits +system.cpu.dtb.read_misses 218086 # DTB read misses +system.cpu.dtb.write_hits 176013555 # DTB write hits +system.cpu.dtb.write_misses 79643 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 49773 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 81418 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 85167 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9097 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 10256 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 21656 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 421800264 # DTB read accesses -system.cpu.dtb.write_accesses 167722676 # DTB write accesses +system.cpu.dtb.perms_faults 22356 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 192331697 # DTB read accesses +system.cpu.dtb.write_accesses 176093198 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 589255276 # DTB hits -system.cpu.dtb.misses 267664 # DTB misses -system.cpu.dtb.accesses 589522940 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 368127166 # DTB hits +system.cpu.dtb.misses 297729 # DTB misses +system.cpu.dtb.accesses 368424895 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -179,470 +179,469 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 126885 # Table walker walks requested -system.cpu.itb.walker.walksLong 126885 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walkWaitTime::samples 126885 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 126885 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 126885 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 113624 99.02% 99.02% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 114746 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 128928 # Table walker walks requested +system.cpu.itb.walker.walksLong 128928 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 128928 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 128928 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 128928 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksPending::samples 3644500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 3644500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 3644500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 115252 99.04% 99.04% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1122 0.96% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 116374 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126885 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 126885 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 128928 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 128928 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114746 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 114746 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 241631 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 1815394284 # ITB inst hits -system.cpu.itb.inst_misses 126885 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 116374 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 116374 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 245302 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 935011975 # ITB inst hits +system.cpu.itb.inst_misses 128928 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 49773 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57333 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 59711 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 1815521169 # ITB inst accesses -system.cpu.itb.hits 1815394284 # DTB hits -system.cpu.itb.misses 126885 # DTB misses -system.cpu.itb.accesses 1815521169 # DTB accesses -system.cpu.numPwrStateTransitions 33574 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16787 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3011524161.053136 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59680214632.955681 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7463 44.46% 44.46% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9289 55.33% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 935140903 # ITB inst accesses +system.cpu.itb.hits 935011975 # DTB hits +system.cpu.itb.misses 128928 # DTB misses +system.cpu.itb.accesses 935140903 # DTB accesses +system.cpu.numPwrStateTransitions 33906 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16953 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 2979611399.652038 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59761128093.250465 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7631 45.01% 45.01% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9287 54.78% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16787 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 993796308901 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50554456091599 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 103096521589 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988782908468 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16953 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 557750343699 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50513352058301 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 102142221758 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16787 # number of quiesce instructions executed -system.cpu.committedInsts 1814916572 # Number of instructions committed -system.cpu.committedOps 1986945286 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1711962456 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 884728 # Number of float alu accesses -system.cpu.num_func_calls 56754008 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 449117161 # number of instructions that are conditional controls -system.cpu.num_int_insts 1711962456 # number of integer instructions -system.cpu.num_fp_insts 884728 # number of float instructions -system.cpu.num_int_register_reads 2333816547 # number of times the integer registers were read -system.cpu.num_int_register_writes 1316284167 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1424283 # number of times the floating registers were read -system.cpu.num_fp_register_writes 753044 # number of times the floating registers were written -system.cpu.num_cc_register_reads 621173289 # number of times the CC registers were read -system.cpu.num_cc_register_writes 620585461 # number of times the CC registers were written -system.cpu.num_mem_refs 589476099 # number of memory refs -system.cpu.num_load_insts 421772480 # Number of load instructions -system.cpu.num_store_insts 167703619 # Number of store instructions -system.cpu.num_idle_cycles 101108928647.540985 # Number of idle cycles -system.cpu.num_busy_cycles 1987592941.459016 # Number of busy cycles -system.cpu.not_idle_fraction 0.019279 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.980721 # Percentage of idle cycles -system.cpu.Branches 576475057 # Number of branches fetched +system.cpu.kern.inst.quiesce 16953 # number of quiesce instructions executed +system.cpu.committedInsts 934475925 # Number of instructions committed +system.cpu.committedOps 1114831373 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1036744712 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 878021 # Number of float alu accesses +system.cpu.num_func_calls 59056085 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 135851428 # number of instructions that are conditional controls +system.cpu.num_int_insts 1036744712 # number of integer instructions +system.cpu.num_fp_insts 878021 # number of float instructions +system.cpu.num_int_register_reads 1380118426 # number of times the integer registers were read +system.cpu.num_int_register_writes 809399347 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1413239 # number of times the floating registers were read +system.cpu.num_fp_register_writes 747664 # number of times the floating registers were written +system.cpu.num_cc_register_reads 207723168 # number of times the CC registers were read +system.cpu.num_cc_register_writes 207152857 # number of times the CC registers were written +system.cpu.num_mem_refs 368379179 # number of memory refs +system.cpu.num_load_insts 192305014 # Number of load instructions +system.cpu.num_store_insts 176074165 # Number of store instructions +system.cpu.num_idle_cycles 101026720885.444443 # Number of idle cycles +system.cpu.num_busy_cycles 1115500872.555553 # Number of busy cycles +system.cpu.not_idle_fraction 0.010921 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.989079 # Percentage of idle cycles +system.cpu.Branches 206489174 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1395540402 70.21% 70.21% # Class of executed instruction -system.cpu.op_class::IntMult 2356131 0.12% 70.33% # Class of executed instruction -system.cpu.op_class::IntDiv 100370 0.01% 70.34% # Class of executed instruction -system.cpu.op_class::FloatAdd 8 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCmp 13 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCvt 21 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMisc 107824 0.01% 70.34% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 421659035 21.21% 91.56% # Class of executed instruction -system.cpu.op_class::MemWrite 167040202 8.40% 99.96% # Class of executed instruction -system.cpu.op_class::FloatMemRead 113445 0.01% 99.97% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 663417 0.03% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 744480688 66.74% 66.74% # Class of executed instruction +system.cpu.op_class::IntMult 2418794 0.22% 66.96% # Class of executed instruction +system.cpu.op_class::IntDiv 103036 0.01% 66.97% # Class of executed instruction +system.cpu.op_class::FloatAdd 8 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatCvt 21 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatMisc 106782 0.01% 66.98% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::MemRead 192192210 17.23% 84.21% # Class of executed instruction +system.cpu.op_class::MemWrite 175415772 15.73% 99.93% # Class of executed instruction +system.cpu.op_class::FloatMemRead 112804 0.01% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 658393 0.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1987580869 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11603445 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999721 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 577795083 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11603957 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 49.792936 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999721 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.op_class::total 1115488522 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 12292096 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999911 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 356005277 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 12292608 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 28.960923 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 13850500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999911 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 1.000000 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 1.000000 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2369200172 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2369200172 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 409181313 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 409181313 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158964390 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158964390 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 425694 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 425694 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336647 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336647 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4299455 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4299455 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4553147 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4553147 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 568482350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 568482350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 568908044 # number of overall hits -system.cpu.dcache.overall_hits::total 568908044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5993326 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5993326 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2556217 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2556217 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1586747 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1586747 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1246619 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1246619 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 255495 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 255495 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1485484203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1485484203 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 178905891 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 178905891 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166844782 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166844782 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 437201 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 437201 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 338801 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 338801 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4589501 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4589501 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4852460 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4852460 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 346089474 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 346089474 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 346526675 # number of overall hits +system.cpu.dcache.overall_hits::total 346526675 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6353340 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6353340 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2735988 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2735988 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1721890 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1721890 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1253245 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1253245 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 264796 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 264796 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 9796162 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9796162 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11382909 # number of overall misses -system.cpu.dcache.overall_misses::total 11382909 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 415174639 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 415174639 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 161520607 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 161520607 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2012441 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2012441 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583266 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1583266 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4554950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4554950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4553148 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4553148 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 578278512 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 578278512 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 580290953 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 580290953 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.014436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015826 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015826 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788469 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788469 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787372 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787372 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056092 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056092 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 10342573 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10342573 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12064463 # number of overall misses +system.cpu.dcache.overall_misses::total 12064463 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 185259231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 185259231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 169580770 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 169580770 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2159091 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2159091 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1592046 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1592046 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4854297 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4854297 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4852461 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4852461 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 356432047 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 356432047 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 358591138 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 358591138 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034294 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.034294 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.016134 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.016134 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.797507 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.797507 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787191 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.787191 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.054549 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.054549 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016940 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019616 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019616 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.029017 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.033644 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.033644 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8939334 # number of writebacks -system.cpu.dcache.writebacks::total 8939334 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 14289332 # number of replacements -system.cpu.icache.tags.tagsinuse 511.984730 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1801219181 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14289844 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 126.048904 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.984730 # Average occupied blocks per requestor +system.cpu.dcache.writebacks::writebacks 9441403 # number of writebacks +system.cpu.dcache.writebacks::total 9441403 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 14554443 # number of replacements +system.cpu.icache.tags.tagsinuse 511.984790 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 920573389 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14554955 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63.248110 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6040365000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.984790 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1829798879 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1829798879 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1801219181 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1801219181 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1801219181 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1801219181 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 935128349 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 935128349 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 935128349 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 935128349 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015565 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015565 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015565 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015565 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015565 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015565 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 14289332 # number of writebacks -system.cpu.icache.writebacks::total 14289332 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1684196 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65394.978455 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 49472483 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1746767 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 28.322314 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9677.706964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 426.448625 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 480.005287 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6101.422178 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48709.395401 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.147670 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006507 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007324 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.093100 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.743246 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 329 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62242 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 328 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1404 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5082 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55348 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005020 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 422888423 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 422888423 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 482010 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237204 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 719214 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8939334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8939334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 14287756 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14287756 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 30651 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 30651 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1695121 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1695121 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14209837 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 14209837 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7515311 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7515311 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 704740 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 704740 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 482010 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 237204 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14209837 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9210432 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24139483 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 482010 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 237204 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14209837 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9210432 # number of overall hits -system.cpu.l2cache.overall_hits::total 24139483 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6072 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5747 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 11819 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3785 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3785 # number of UpgradeReq misses +system.cpu.icache.writebacks::writebacks 14554443 # number of writebacks +system.cpu.icache.writebacks::total 14554443 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1939529 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65410.509732 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 51207751 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2002275 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.574784 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 373950000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9607.000136 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 373.212421 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 441.072045 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6073.861347 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48915.363784 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.146591 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005695 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006730 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092680 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.746389 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998085 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 323 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62423 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 323 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1416 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5058 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55500 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004929 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952499 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 439130926 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 439130926 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 564464 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 243894 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 808358 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 9441403 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 9441403 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 14552867 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 14552867 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 32762 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 32762 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1717134 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1717134 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14467928 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14467928 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7961263 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7961263 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 682418 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 682418 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 564464 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 243894 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14467928 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9678397 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24954683 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 564464 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 243894 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14467928 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9678397 # number of overall hits +system.cpu.l2cache.overall_hits::total 24954683 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7612 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6862 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 14474 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3878 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3878 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826660 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826660 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 80012 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 80012 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320257 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 320257 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 541879 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 541879 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6072 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5747 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 80012 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1146917 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1238748 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6072 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5747 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 80012 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1146917 # number of overall misses -system.cpu.l2cache.overall_misses::total 1238748 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 488082 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 242951 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 731033 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8939334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8939334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 14287756 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 14287756 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34436 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 34436 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 982214 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 982214 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 87032 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 87032 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 378763 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 378763 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 570827 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 570827 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 7612 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 6862 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 87032 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1360977 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1462483 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 7612 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 6862 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 87032 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1360977 # number of overall misses +system.cpu.l2cache.overall_misses::total 1462483 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 572076 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 250756 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 822832 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 9441403 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 9441403 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 14552867 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14552867 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 36640 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 36640 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2521781 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2521781 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14289849 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 14289849 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7835568 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7835568 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246619 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1246619 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 488082 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 242951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14289849 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10357349 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25378231 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 488082 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 242951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14289849 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10357349 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25378231 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012441 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.023655 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016168 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.109914 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.109914 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2699348 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2699348 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14554960 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 14554960 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 8340026 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 8340026 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1253245 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1253245 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 572076 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 250756 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14554960 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 11039374 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 26417166 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 572076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 250756 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14554960 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 11039374 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 26417166 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013306 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.027365 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.017590 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.105841 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.105841 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.327808 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.327808 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005599 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005599 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.040872 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.040872 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.434679 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.434679 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012441 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.023655 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005599 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.110735 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.048811 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012441 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.023655 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005599 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.110735 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.048811 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.363871 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.363871 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045415 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045415 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.455479 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.455479 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013306 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.027365 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005980 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123284 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.055361 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013306 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.027365 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005980 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123284 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.055361 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1484910 # number of writebacks -system.cpu.l2cache.writebacks::total 1484910 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 52410934 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26517119 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2740 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2740 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.writebacks::writebacks 1697477 # number of writebacks +system.cpu.l2cache.writebacks::total 1697477 # number of writebacks +system.cpu.toL2Bus.snoop_filter.tot_requests 54350593 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 27503016 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1759 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2697 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1234221 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23359638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8939334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14289332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2664111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 34436 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1286731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 24181717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9441403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14554443 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2850693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 36640 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 34437 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2521781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2521781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14289849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7835568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1246619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1246619 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42955280 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35014647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758514 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1556522 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80284963 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829240084 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1235177526 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3034056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6226088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3073677754 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1724598 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 95094976 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 54812635 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010876 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103719 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 36641 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2699348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2699348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14554960 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 8340026 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1253245 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1253245 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43673813 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37084586 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 770772 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1726308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 83255479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1863020692 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1310959042 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3083088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6905232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3183968054 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1977015 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 108689536 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 57027218 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010978 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104200 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54216500 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 596135 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 56401167 98.90% 98.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 626051 1.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 54812635 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40253 # Transaction distribution -system.iobus.trans_dist::ReadResp 40253 # Transaction distribution -system.iobus.trans_dist::WriteReq 136515 # Transaction distribution -system.iobus.trans_dist::WriteResp 136515 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 57027218 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40168 # Transaction distribution +system.iobus.trans_dist::ReadResp 40168 # Transaction distribution +system.iobus.trans_dist::WriteReq 136429 # Transaction distribution +system.iobus.trans_dist::WriteResp 136429 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47254 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -655,13 +654,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122136 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230978 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230978 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353194 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47274 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -674,56 +673,56 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155266 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334344 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334344 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492032 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115470 # number of replacements -system.iocache.tags.tagsinuse 10.454534 # Cycle average of tags in use +system.iobus.pkt_size::total 7491696 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115471 # number of replacements +system.iocache.tags.tagsinuse 10.402763 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.524459 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.930076 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220279 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433130 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653408 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13082091783509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.557357 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.845405 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222335 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.427838 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.650173 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039749 # Number of tag accesses -system.iocache.tags.data_accesses 1039749 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039758 # Number of tag accesses +system.iocache.tags.data_accesses 1039758 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8825 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8862 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses -system.iocache.demand_misses::total 115528 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115489 # number of demand (read+write) misses +system.iocache.demand_misses::total 115529 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115488 # number of overall misses -system.iocache.overall_misses::total 115528 # number of overall misses +system.iocache.overall_misses::realview.ide 115489 # number of overall misses +system.iocache.overall_misses::total 115529 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8825 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8862 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115489 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115529 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115489 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115529 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -745,71 +744,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.membus.snoop_filter.tot_requests 3698370 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1836830 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_requests 4206457 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2089632 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 76703 # Transaction distribution -system.membus.trans_dist::ReadResp 497652 # Transaction distribution -system.membus.trans_dist::WriteReq 33618 # Transaction distribution -system.membus.trans_dist::WriteResp 33618 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1591541 # Transaction distribution -system.membus.trans_dist::CleanEvict 206888 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4346 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38191 # Transaction distribution +system.membus.trans_dist::ReadResp 527322 # Transaction distribution +system.membus.trans_dist::WriteReq 33519 # Transaction distribution +system.membus.trans_dist::WriteResp 33519 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1804108 # Transaction distribution +system.membus.trans_dist::CleanEvict 249631 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4439 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4347 # Transaction distribution -system.membus.trans_dist::ReadExReq 826102 # Transaction distribution -system.membus.trans_dist::ReadExResp 826102 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420949 # Transaction distribution -system.membus.trans_dist::InvalidateReq 648543 # Transaction distribution -system.membus.trans_dist::InvalidateResp 648543 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4440 # Transaction distribution +system.membus.trans_dist::ReadExReq 981656 # Transaction distribution +system.membus.trans_dist::ReadExResp 981656 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 489131 # Transaction distribution +system.membus.trans_dist::InvalidateReq 677491 # Transaction distribution +system.membus.trans_dist::InvalidateResp 677491 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122136 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6726 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5343163 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5472427 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5818953 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6648 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6027224 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6156066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6502595 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155266 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13452 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 174471520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 174640714 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7391488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 182032202 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 202241248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 202409942 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7391552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 209801494 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3808691 # Request fanout histogram -system.membus.snoop_fanout::mean 0.010569 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.102262 # Request fanout histogram +system.membus.snoop_fanout::samples 4278167 # Request fanout histogram +system.membus.snoop_fanout::mean 0.008735 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.093051 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3768436 98.94% 98.94% # Request fanout histogram -system.membus.snoop_fanout::1 40255 1.06% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4240798 99.13% 99.13% # Request fanout histogram +system.membus.snoop_fanout::1 37369 0.87% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3808691 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 4278167 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -819,11 +818,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -852,28 +851,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 529d7a06f..c24bc3993 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.405081 # Number of seconds simulated -sim_ticks 47405080882500 # Number of ticks simulated -final_tick 47405080882500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.401371 # Number of seconds simulated +sim_ticks 47401370587500 # Number of ticks simulated +final_tick 47401370587500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1071981 # Simulator instruction rate (inst/s) -host_op_rate 1260946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57861452624 # Simulator tick rate (ticks/s) -host_mem_usage 765552 # Number of bytes of host memory used -host_seconds 819.29 # Real time elapsed on the host -sim_insts 878258906 # Number of instructions simulated -sim_ops 1033075205 # Number of ops (including micro ops) simulated +host_inst_rate 1122973 # Simulator instruction rate (inst/s) +host_op_rate 1337206 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65940331964 # Simulator tick rate (ticks/s) +host_mem_usage 757896 # Number of bytes of host memory used +host_seconds 718.85 # Real time elapsed on the host +sim_insts 807251718 # Number of instructions simulated +sim_ops 961253990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 98688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3570996 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13936584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15336640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 134720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 134720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2530168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9676304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 10811456 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 435904 # Number of bytes read from this memory -system.physmem.bytes_read::total 56765124 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3570996 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2530168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6101164 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74743808 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 62784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 59776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2908084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 11497800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 12850688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 108160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 115584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2943416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9887760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11019584 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 443392 # Number of bytes read from this memory +system.physmem.bytes_read::total 51897028 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2908084 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2943416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5851500 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70859904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74764392 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1542 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 96204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 217772 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 239635 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39622 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 151205 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 168929 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6811 # Number of read requests responded to by this memory -system.physmem.num_reads::total 927476 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1167872 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 70880488 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 934 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 49846 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 179666 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 200792 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1690 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1806 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 46079 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 154509 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 172181 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6928 # Number of read requests responded to by this memory +system.physmem.num_reads::total 815412 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1107186 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1170446 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 75329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 293989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 323523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 204120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 228065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1197448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 75329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 128703 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1576705 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1109760 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 61350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 242563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 271104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 62096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 208597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 232474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1094842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 61350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 62096 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 123446 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1494891 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1577139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1576705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 75329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 294423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 323523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 204120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 228065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2774587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 927476 # Number of read requests accepted -system.physmem.writeReqs 1170446 # Number of write requests accepted -system.physmem.readBursts 927476 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1170446 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59335744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue -system.physmem.bytesWritten 74761408 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56765124 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 74764392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1495326 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1494891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 61350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 242997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 271104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 62096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 208597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 232474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2590168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 815412 # Number of read requests accepted +system.physmem.writeReqs 1109760 # Number of write requests accepted +system.physmem.readBursts 815412 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1109760 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 52162176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24192 # Total number of bytes read from write queue +system.physmem.bytesWritten 70877120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 51897028 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70880488 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 378 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2280 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 53525 # Per bank write bursts -system.physmem.perBankRdBursts::1 58700 # Per bank write bursts -system.physmem.perBankRdBursts::2 53136 # Per bank write bursts -system.physmem.perBankRdBursts::3 59915 # Per bank write bursts -system.physmem.perBankRdBursts::4 57558 # Per bank write bursts -system.physmem.perBankRdBursts::5 67025 # Per bank write bursts -system.physmem.perBankRdBursts::6 57593 # Per bank write bursts -system.physmem.perBankRdBursts::7 57551 # Per bank write bursts -system.physmem.perBankRdBursts::8 45941 # Per bank write bursts -system.physmem.perBankRdBursts::9 94599 # Per bank write bursts -system.physmem.perBankRdBursts::10 49635 # Per bank write bursts -system.physmem.perBankRdBursts::11 57294 # Per bank write bursts -system.physmem.perBankRdBursts::12 48522 # Per bank write bursts -system.physmem.perBankRdBursts::13 56965 # Per bank write bursts -system.physmem.perBankRdBursts::14 52794 # Per bank write bursts -system.physmem.perBankRdBursts::15 56368 # Per bank write bursts -system.physmem.perBankWrBursts::0 71875 # Per bank write bursts -system.physmem.perBankWrBursts::1 75753 # Per bank write bursts -system.physmem.perBankWrBursts::2 71549 # Per bank write bursts -system.physmem.perBankWrBursts::3 77042 # Per bank write bursts -system.physmem.perBankWrBursts::4 73392 # Per bank write bursts -system.physmem.perBankWrBursts::5 80022 # Per bank write bursts -system.physmem.perBankWrBursts::6 71461 # Per bank write bursts -system.physmem.perBankWrBursts::7 73088 # Per bank write bursts -system.physmem.perBankWrBursts::8 65465 # Per bank write bursts -system.physmem.perBankWrBursts::9 74249 # Per bank write bursts -system.physmem.perBankWrBursts::10 70475 # Per bank write bursts -system.physmem.perBankWrBursts::11 74236 # Per bank write bursts -system.physmem.perBankWrBursts::12 69250 # Per bank write bursts -system.physmem.perBankWrBursts::13 75271 # Per bank write bursts -system.physmem.perBankWrBursts::14 70641 # Per bank write bursts -system.physmem.perBankWrBursts::15 74378 # Per bank write bursts +system.physmem.perBankRdBursts::0 50443 # Per bank write bursts +system.physmem.perBankRdBursts::1 58279 # Per bank write bursts +system.physmem.perBankRdBursts::2 46176 # Per bank write bursts +system.physmem.perBankRdBursts::3 52637 # Per bank write bursts +system.physmem.perBankRdBursts::4 47826 # Per bank write bursts +system.physmem.perBankRdBursts::5 55648 # Per bank write bursts +system.physmem.perBankRdBursts::6 52176 # Per bank write bursts +system.physmem.perBankRdBursts::7 51274 # Per bank write bursts +system.physmem.perBankRdBursts::8 44248 # Per bank write bursts +system.physmem.perBankRdBursts::9 55412 # Per bank write bursts +system.physmem.perBankRdBursts::10 43487 # Per bank write bursts +system.physmem.perBankRdBursts::11 55151 # Per bank write bursts +system.physmem.perBankRdBursts::12 50800 # Per bank write bursts +system.physmem.perBankRdBursts::13 57431 # Per bank write bursts +system.physmem.perBankRdBursts::14 46539 # Per bank write bursts +system.physmem.perBankRdBursts::15 47507 # Per bank write bursts +system.physmem.perBankWrBursts::0 68734 # Per bank write bursts +system.physmem.perBankWrBursts::1 74075 # Per bank write bursts +system.physmem.perBankWrBursts::2 65910 # Per bank write bursts +system.physmem.perBankWrBursts::3 69531 # Per bank write bursts +system.physmem.perBankWrBursts::4 66080 # Per bank write bursts +system.physmem.perBankWrBursts::5 73115 # Per bank write bursts +system.physmem.perBankWrBursts::6 69817 # Per bank write bursts +system.physmem.perBankWrBursts::7 69743 # Per bank write bursts +system.physmem.perBankWrBursts::8 63555 # Per bank write bursts +system.physmem.perBankWrBursts::9 71485 # Per bank write bursts +system.physmem.perBankWrBursts::10 64662 # Per bank write bursts +system.physmem.perBankWrBursts::11 72406 # Per bank write bursts +system.physmem.perBankWrBursts::12 68380 # Per bank write bursts +system.physmem.perBankWrBursts::13 74722 # Per bank write bursts +system.physmem.perBankWrBursts::14 65945 # Per bank write bursts +system.physmem.perBankWrBursts::15 69295 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 399 # Number of times write queue was full causing retry -system.physmem.totGap 47405077592000 # Total gap between requests +system.physmem.numWrRetry 463 # Number of times write queue was full causing retry +system.physmem.totGap 47401367297000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 43195 # Read request sizes (log2) +system.physmem.readPktSize::2 4795 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 884251 # Read request sizes (log2) +system.physmem.readPktSize::6 810587 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1167872 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 648346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 87693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 22073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 104 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1107186 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 559891 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 78604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 23379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 20454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 14604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,167 +189,189 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 36931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 63693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 65505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 70215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 70242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 73447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 75382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 72205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 70493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 71352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 68341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 921 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 928498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 144.423393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.327252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 191.341879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 616929 66.44% 66.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189662 20.43% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44616 4.81% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20270 2.18% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14755 1.59% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9179 0.99% 96.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6168 0.66% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5453 0.59% 97.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21466 2.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 928498 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60682 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.278254 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 130.725132 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60680 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60682 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60682 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.250305 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.439777 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.504538 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 53685 88.47% 88.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 4623 7.62% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 1219 2.01% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 192 0.32% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 86 0.14% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 66 0.11% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 562 0.93% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 118 0.19% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 38 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 2 0.00% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 5 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 14 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 28 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 15 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60682 # Writes before turning the bus around for reads -system.physmem.totQLat 46391884854 # Total ticks spent queuing -system.physmem.totMemAccLat 63775403604 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4635605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 50038.65 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 27848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 46446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 51674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 63717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 66102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 66334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 69492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 71245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 67739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 66506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 67172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 70520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 64778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1057 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 862223 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 142.699715 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 97.984234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 187.236614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 572247 66.37% 66.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 178435 20.69% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 41649 4.83% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 18745 2.17% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13461 1.56% 95.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8413 0.98% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6049 0.70% 97.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5161 0.60% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18063 2.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 862223 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 57012 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.295727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 26.624569 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 57003 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 57012 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 57012 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.424946 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.563445 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.850614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 45452 79.72% 79.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4610 8.09% 87.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2793 4.90% 92.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1774 3.11% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1007 1.77% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 224 0.39% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 148 0.26% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 47 0.08% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 57 0.10% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 22 0.04% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 26 0.05% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 34 0.06% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 476 0.83% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 79 0.14% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 57 0.10% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 65 0.11% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 45 0.08% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 12 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 4 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 7 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 9 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 57012 # Writes before turning the bus around for reads +system.physmem.totQLat 43191913053 # Total ticks spent queuing +system.physmem.totMemAccLat 58473800553 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4075170000 # Total ticks spent in databus transfers +system.physmem.avgQLat 52994.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 68788.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 71744.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.50 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.50 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing -system.physmem.readRowHits 687053 # Number of row buffer hits during reads -system.physmem.writeRowHits 479716 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.07 # Row buffer hit rate for writes -system.physmem.avgGap 22596205.96 # Average gap between requests -system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3406258380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1810469265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3320121420 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3101630040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 41354208480.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 46841067270 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2207636640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 80277254730 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 57514863840 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11279816434935 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11519667255870 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.004907 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47296565897576 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3842888750 # Time in different power states -system.physmem_0.memoryStateTime::REF 17568968000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 46970746731500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 149777866049 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87097852174 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 176046576027 # Time in different power states -system.physmem_1.actEnergy 3223224480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1713180645 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3299522520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2996097300 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 40281047040.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47571960030 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2174762400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 74931048030 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 56612801280 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11282749861635 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11515570196190 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.918480 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47295055254584 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3757232201 # Time in different power states -system.physmem_1.memoryStateTime::REF 17114078000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 46983304269750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 147428799179 # Time in different power states -system.physmem_1.memoryStateTime::ACT 89154269965 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 164322233405 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 599171 # Number of row buffer hits during reads +system.physmem.writeRowHits 461094 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.63 # Row buffer hit rate for writes +system.physmem.avgGap 24621886.93 # Average gap between requests +system.physmem.pageHitRate 55.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3125163720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1661060115 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2959237260 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2907566100 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 39767208000.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 44841459390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2203203840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 73351636740 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 56747456160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11284217805975 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11511799212150 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.857940 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47297258186903 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3926700752 # Time in different power states +system.physmem_0.memoryStateTime::REF 16898782000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 46988619115750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 147779602583 # Time in different power states +system.physmem_0.memoryStateTime::ACT 83286870095 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 160859516320 # Time in different power states +system.physmem_1.actEnergy 3031115640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1611076170 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2860105500 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2873349000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 40284120240.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 45341107710 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2193321120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 73446933900 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 57703512480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11283525763155 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11512888807215 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.880926 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47296183842356 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3879016799 # Time in different power states +system.physmem_1.memoryStateTime::REF 17119770000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 46984848194500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 150269925291 # Time in different power states +system.physmem_1.memoryStateTime::ACT 84186543595 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 161067137315 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -376,9 +398,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -386,7 +408,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -416,72 +438,70 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 105104 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 105104 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9446 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80223 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 105078 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.247435 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 80.207956 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 105077 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 92556 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 92556 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8240 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 69143 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 92545 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.280944 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 85.466687 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 92544 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 105078 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 89695 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23784.720441 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21979.926785 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16790.109220 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 88715 98.91% 98.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 727 0.81% 99.72% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 132 0.15% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 44 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 40 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 92545 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 77394 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23265.414632 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21722.582011 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14143.873172 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 76797 99.23% 99.23% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 427 0.55% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 102 0.13% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 27 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 20 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 89695 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -4516142684 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.024301 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 109748704 -2.43% -2.43% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -4625891388 102.43% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -4516142684 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 80223 89.47% 89.47% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9446 10.53% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 89669 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105104 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 77394 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 6740631600 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.619851 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.485423 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2562444572 38.01% 38.01% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 4178187028 61.99% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6740631600 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 69143 89.35% 89.35% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8240 10.65% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 77383 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 92556 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105104 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89669 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 92556 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77383 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89669 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 194773 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77383 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 169939 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 85250979 # DTB read hits -system.cpu0.dtb.read_misses 79026 # DTB read misses -system.cpu0.dtb.write_hits 77401552 # DTB write hits -system.cpu0.dtb.write_misses 26078 # DTB write misses +system.cpu0.dtb.read_hits 77415423 # DTB read hits +system.cpu0.dtb.read_misses 69730 # DTB read misses +system.cpu0.dtb.write_hits 70114940 # DTB write hits +system.cpu0.dtb.write_misses 22826 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35795 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 34306 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4355 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3960 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8965 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 85330005 # DTB read accesses -system.cpu0.dtb.write_accesses 77427630 # DTB write accesses +system.cpu0.dtb.perms_faults 8638 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 77485153 # DTB read accesses +system.cpu0.dtb.write_accesses 70137766 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 162652531 # DTB hits -system.cpu0.dtb.misses 105104 # DTB misses -system.cpu0.dtb.accesses 162757635 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 147530363 # DTB hits +system.cpu0.dtb.misses 92556 # DTB misses +system.cpu0.dtb.accesses 147622919 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,759 +531,760 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 55600 # Table walker walks requested -system.cpu0.itb.walker.walksLong 55600 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 619 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49488 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 55600 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 55600 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 55600 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 50107 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25482.068374 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23271.243255 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 20741.366870 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 49151 98.09% 98.09% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 657 1.31% 99.40% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 169 0.34% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.11% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 41 0.08% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 10 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 50107 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 49488 98.76% 98.76% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 619 1.24% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 50107 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 51144 # Table walker walks requested +system.cpu0.itb.walker.walksLong 51144 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 535 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 45125 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 51144 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 51144 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 51144 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 45660 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 24927.069645 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23080.556454 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 20288.256560 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 45087 98.75% 98.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 348 0.76% 99.51% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 137 0.30% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 34 0.07% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 16 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 45660 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 618561500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 618561500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 618561500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 45125 98.83% 98.83% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 535 1.17% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 45660 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55600 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 51144 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 51144 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50107 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50107 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 105707 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 455710659 # ITB inst hits -system.cpu0.itb.inst_misses 55600 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 45660 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 45660 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 96804 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 385005651 # ITB inst hits +system.cpu0.itb.inst_misses 51144 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25367 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24319 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 455766259 # ITB inst accesses -system.cpu0.itb.hits 455710659 # DTB hits -system.cpu0.itb.misses 55600 # DTB misses -system.cpu0.itb.accesses 455766259 # DTB accesses -system.cpu0.numPwrStateTransitions 25961 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 12981 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3608162218.077806 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 66802602989.523827 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3144 24.22% 24.22% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9807 75.55% 99.77% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1988778266744 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 12981 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 567527129632 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46837553752868 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94809604801 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 385056795 # ITB inst accesses +system.cpu0.itb.hits 385005651 # DTB hits +system.cpu0.itb.misses 51144 # DTB misses +system.cpu0.itb.accesses 385056795 # DTB accesses +system.cpu0.numPwrStateTransitions 8306 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 4153 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 11295325194.838190 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 176339050181.920959 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 2776 66.84% 66.84% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1353 32.58% 99.42% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.14% 99.57% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.59% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.64% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 12 0.29% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 6953821743500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 4153 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 491885053337 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46909485534163 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94802741175 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 12981 # number of quiesce instructions executed -system.cpu0.committedInsts 455440444 # Number of instructions committed -system.cpu0.committedOps 534258155 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 490602455 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 409464 # Number of float alu accesses -system.cpu0.num_func_calls 27345084 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 69133268 # number of instructions that are conditional controls -system.cpu0.num_int_insts 490602455 # number of integer instructions -system.cpu0.num_fp_insts 409464 # number of float instructions -system.cpu0.num_int_register_reads 709813202 # number of times the integer registers were read -system.cpu0.num_int_register_writes 389013737 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 678261 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 309808 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 119533818 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 119119815 # number of times the CC registers were written -system.cpu0.num_mem_refs 162644052 # number of memory refs -system.cpu0.num_load_insts 85246888 # Number of load instructions -system.cpu0.num_store_insts 77397164 # Number of store instructions -system.cpu0.num_idle_cycles 93674557209.632675 # Number of idle cycles -system.cpu0.num_busy_cycles 1135047591.367321 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011972 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988028 # Percentage of idle cycles -system.cpu0.Branches 101837898 # Number of branches fetched +system.cpu0.kern.inst.quiesce 4153 # number of quiesce instructions executed +system.cpu0.committedInsts 384730653 # Number of instructions committed +system.cpu0.committedOps 456411878 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 424236423 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 341428 # Number of float alu accesses +system.cpu0.num_func_calls 24795410 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 55287954 # number of instructions that are conditional controls +system.cpu0.num_int_insts 424236423 # number of integer instructions +system.cpu0.num_fp_insts 341428 # number of float instructions +system.cpu0.num_int_register_reads 565685630 # number of times the integer registers were read +system.cpu0.num_int_register_writes 332181203 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 574384 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 236428 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 85999446 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 85681176 # number of times the CC registers were written +system.cpu0.num_mem_refs 147523428 # number of memory refs +system.cpu0.num_load_insts 77412307 # Number of load instructions +system.cpu0.num_store_insts 70111121 # Number of store instructions +system.cpu0.num_idle_cycles 93818971068.324020 # Number of idle cycles +system.cpu0.num_busy_cycles 983770106.675979 # Number of busy cycles +system.cpu0.not_idle_fraction 0.010377 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.989623 # Percentage of idle cycles +system.cpu0.Branches 84896632 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 370653040 69.34% 69.34% # Class of executed instruction -system.cpu0.op_class::IntMult 1173518 0.22% 69.56% # Class of executed instruction -system.cpu0.op_class::IntDiv 58988 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatMisc 41897 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::MemRead 85199674 15.94% 85.51% # Class of executed instruction -system.cpu0.op_class::MemWrite 77076811 14.42% 99.93% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 47214 0.01% 99.94% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 320353 0.06% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 307975543 67.44% 67.44% # Class of executed instruction +system.cpu0.op_class::IntMult 1108929 0.24% 67.68% # Class of executed instruction +system.cpu0.op_class::IntDiv 55110 0.01% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatMisc 28590 0.01% 67.70% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::MemRead 77373487 16.94% 84.64% # Class of executed instruction +system.cpu0.op_class::MemWrite 69837103 15.29% 99.93% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 38820 0.01% 99.94% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 274018 0.06% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 534571495 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5548235 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.308001 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 156839853 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5548600 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.266563 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.308001 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992789 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.992789 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 330814481 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 330814481 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 79405965 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79405965 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72971377 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72971377 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204972 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 204972 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263219 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 263219 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813440 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1813440 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787735 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1787735 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 152640561 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 152640561 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 152845533 # number of overall hits -system.cpu0.dcache.overall_hits::total 152845533 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3006341 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3006341 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1360477 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1360477 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 626311 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 626311 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 794287 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 794287 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164142 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 164142 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 188530 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 188530 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5161105 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5161105 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5787416 # number of overall misses -system.cpu0.dcache.overall_misses::total 5787416 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47850868000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 47850868000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29377875000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29377875000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25259415500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 25259415500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2486803500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2486803500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4498365000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4498365000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2057500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2057500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 102488158500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 102488158500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 102488158500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 102488158500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 82412306 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 82412306 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74331854 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74331854 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 831283 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 831283 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1057506 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1057506 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1977582 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1977582 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1976265 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1976265 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 157801666 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 157801666 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 158632949 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 158632949 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036479 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036479 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018303 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018303 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.753427 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.753427 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.751095 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.751095 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083001 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083001 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095397 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095397 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032706 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032706 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036483 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036483 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15916.646847 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15916.646847 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21593.804967 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21593.804967 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31801.370915 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31801.370915 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15150.318017 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15150.318017 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23860.207924 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23860.207924 # average StoreCondReq miss latency +system.cpu0.op_class::total 456691600 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5013046 # number of replacements +system.cpu0.dcache.tags.tagsinuse 470.143979 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 142293396 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5013556 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.381731 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 637122000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.143979 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.918250 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.918250 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 300094424 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 300094424 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 72133805 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 72133805 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 66092358 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 66092358 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186275 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 186275 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 227046 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 227046 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1654353 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1654353 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1603859 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1603859 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 138453209 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 138453209 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 138639484 # number of overall hits +system.cpu0.dcache.overall_hits::total 138639484 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2704079 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2704079 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1255388 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1255388 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 579222 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 579222 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 722220 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 722220 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 141818 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 141818 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191065 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 191065 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4681687 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4681687 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5260909 # number of overall misses +system.cpu0.dcache.overall_misses::total 5260909 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41586194000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41586194000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27254591500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 27254591500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 23833661500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 23833661500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2088985000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2088985000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4536311000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4536311000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2828500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2828500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 92674447000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 92674447000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 92674447000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 92674447000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 74837884 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 74837884 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 67347746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 67347746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 765497 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 765497 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 949266 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 949266 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1796171 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1796171 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1794924 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1794924 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 143134896 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 143134896 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 143900393 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 143900393 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036132 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036132 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018640 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018640 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756661 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.756661 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760819 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760819 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078956 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078956 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.106447 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.106447 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032708 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032708 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036559 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036559 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15379.060301 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15379.060301 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21710.094011 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21710.094011 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33000.555925 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33000.555925 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.041321 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.041321 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23742.239552 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23742.239552 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19857.793728 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19857.793728 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17708.794132 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17708.794132 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19795.096725 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19795.096725 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17615.671930 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17615.671930 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5548235 # number of writebacks -system.cpu0.dcache.writebacks::total 5548235 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26826 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 26826 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21220 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21220 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43038 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43038 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 48046 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 48046 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 48046 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 48046 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2979515 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2979515 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1339257 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1339257 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 624730 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 624730 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 794287 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 794287 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121104 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121104 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188530 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 188530 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5113059 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5113059 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5737789 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5737789 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29828 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59187 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43367868500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43367868500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27478579500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27478579500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14655261000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14655261000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24465128500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24465128500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1605767000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1605767000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4309885000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4309885000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2007500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2007500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95311576500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 95311576500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109966837500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 109966837500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5687970000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5687970000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5687970000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5687970000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036154 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036154 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018017 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018017 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.751525 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751525 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.751095 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.751095 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061238 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061238 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095397 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095397 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032402 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032402 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036170 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.036170 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14555.344914 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14555.344914 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20517.779261 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20517.779261 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23458.551694 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23458.551694 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30801.370915 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30801.370915 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13259.405139 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13259.405139 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22860.473134 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22860.473134 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5013046 # number of writebacks +system.cpu0.dcache.writebacks::total 5013046 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26558 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 26558 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21241 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21241 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 37285 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 37285 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 47799 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 47799 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 47799 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 47799 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2677521 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2677521 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1234147 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1234147 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 577585 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 577585 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 722220 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 722220 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104533 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104533 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191065 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 191065 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4633888 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4633888 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5211473 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5211473 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15891 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16800 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32691 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37485691500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37485691500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25473400500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25473400500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13565827500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13565827500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 23111441500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 23111441500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1404174500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1404174500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4345314000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4345314000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2760500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 86070533500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 86070533500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 99636361000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 99636361000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2929733500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2929733500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2929733500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2929733500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035778 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035778 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754523 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754523 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760819 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760819 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058198 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058198 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.106447 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.106447 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032374 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032374 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036216 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036216 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14000.148458 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14000.148458 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20640.491368 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20640.491368 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23487.153406 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23487.153406 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32000.555925 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32000.555925 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13432.834607 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13432.834607 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22742.595452 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22742.595452 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18640.812965 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18640.812965 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19165.367967 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19165.367967 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190692.302535 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190692.302535 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96101.677733 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96101.677733 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 4928137 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.903899 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 450782010 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4928649 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 91.461577 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30794452000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903899 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18574.150584 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18574.150584 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19118.656280 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19118.656280 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184364.325719 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184364.325719 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89618.962406 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89618.962406 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 4327935 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.943806 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 380677204 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4328447 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 87.947757 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 27073430000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.943806 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999890 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999890 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 916349967 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 916349967 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 450782010 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 450782010 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 450782010 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 450782010 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 450782010 # number of overall hits -system.cpu0.icache.overall_hits::total 450782010 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4928649 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4928649 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4928649 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4928649 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4928649 # number of overall misses -system.cpu0.icache.overall_misses::total 4928649 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54016215500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 54016215500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 54016215500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 54016215500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 54016215500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 54016215500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 455710659 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 455710659 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 455710659 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 455710659 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 455710659 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 455710659 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010815 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010815 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010815 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010815 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010815 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010815 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10959.639345 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10959.639345 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10959.639345 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10959.639345 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 774339749 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 774339749 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 380677204 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 380677204 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 380677204 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 380677204 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 380677204 # number of overall hits +system.cpu0.icache.overall_hits::total 380677204 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4328447 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4328447 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4328447 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4328447 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4328447 # number of overall misses +system.cpu0.icache.overall_misses::total 4328447 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47943054500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 47943054500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 47943054500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 47943054500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 47943054500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 47943054500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 385005651 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 385005651 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 385005651 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 385005651 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 385005651 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 385005651 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011243 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011243 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011243 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011243 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011243 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011243 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11076.271582 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11076.271582 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11076.271582 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11076.271582 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 4928137 # number of writebacks -system.cpu0.icache.writebacks::total 4928137 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4928649 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 4928649 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 4928649 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 4928649 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 4928649 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 4928649 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51551891000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 51551891000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51551891000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 51551891000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51551891000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 51551891000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010815 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010815 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010815 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10459.639345 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7424522 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7424525 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.writebacks::writebacks 4327935 # number of writebacks +system.cpu0.icache.writebacks::total 4327935 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4328447 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4328447 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4328447 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4328447 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4328447 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4328447 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 4725 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 4725 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45778831000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 45778831000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45778831000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 45778831000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45778831000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 45778831000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 463686000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 463686000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 463686000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 463686000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011243 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011243 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011243 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10576.271582 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10576.271582 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10576.271582 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98134.603175 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98134.603175 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98134.603175 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98134.603175 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7077148 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7077156 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 998915 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2238289 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15477.322343 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 8961437 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2253120 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.977346 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5406108500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15186.002225 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.160912 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 26.574333 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 232.584873 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.926880 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 27 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1242 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8440 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4747 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020935 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.880676 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 361005368 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 361005368 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # 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number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 36538035500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32033056811 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 82442961811 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 428248500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2802283500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3230532000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 428248500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2802283500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 3230532000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065151 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1272,123 +1293,123 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.211294 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.211294 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089860 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242397 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242397 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.733585 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.733585 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157982 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216629 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216629 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095048 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.247135 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247135 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772848 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772848 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.163977 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229343 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27858.040300 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51278.255674 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18620.800908 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18620.800908 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15355.240121 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15355.240121 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 407999.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 407999.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48519.631094 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48519.631094 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32868.658964 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33401.924446 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33401.924446 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31581.382996 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31581.382996 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35398.573573 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40339.599745 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182679.110232 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126684.975258 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92063.333164 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90332.013840 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 21698067 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128745 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1153 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 593692 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 593692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.238348 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24446.257569 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 47452.584254 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18678.492868 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18678.492868 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15238.588598 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15238.588598 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 374833 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 374833 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 47642.203354 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 47642.203354 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32334.063746 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31186.561088 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31186.561088 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31554.703260 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31554.703260 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33868.428867 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38107.031341 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176344.062677 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156700.232829 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85720.335872 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86340.923669 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 19414965 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 9975279 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 976 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 578988 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 578988 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 544237 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9287091 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 29360 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 29359 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5208748 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 6782514 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1060718 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 892976 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 428421 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 483695 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1159777 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1132425 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4928649 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4659477 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 859685 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 795582 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14871685 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17955801 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 314812 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 561073 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 33703371 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 631006804 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671861433 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190128 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2046696 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1306105061 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5091046 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 103758092 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 16426970 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.050205 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.218367 # Request fanout histogram +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 442233 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 8226522 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 16801 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 16800 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4707887 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 6010120 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 978928 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 831060 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 419258 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 359151 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 478987 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1069161 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1041370 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4328447 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4301809 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 793195 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 723551 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12994279 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16301256 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 289006 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 490041 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 30074582 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 554027348 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 608753046 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1089928 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1769528 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1165639850 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4847803 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 95443532 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 14917131 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.053800 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.225623 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15602261 94.98% 94.98% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 824709 5.02% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 14114583 94.62% 94.62% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 802548 5.38% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 16426970 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 21511948503 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 14917131 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 19175088002 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 179528613 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 194853286 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7436098500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 6497395500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7925019139 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7177011173 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 166046000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 152765499 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 305236000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 268850499 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1418,72 +1439,72 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 105151 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 105151 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9241 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80639 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 105142 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.076088 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 24.671859 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 105141 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 108097 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 108097 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9121 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84193 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 108080 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.074019 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 24.334214 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 108079 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 105142 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 89889 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24662.817475 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 22388.286381 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 19750.546055 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 88485 98.44% 98.44% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.20% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.18% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.07% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::total 108080 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 93331 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24327.977842 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22238.306429 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 18706.694176 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 92079 98.66% 98.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 920 0.99% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 176 0.19% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 54 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.05% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::327680-393215 24 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 23 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 89889 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 550636548 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.425840 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.494470 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 316153352 57.42% 57.42% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 234483196 42.58% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 550636548 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 80640 89.72% 89.72% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9241 10.28% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 89881 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105151 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 93331 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 5379088140 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.979144 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.142902 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 112185648 2.09% 2.09% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 5266902492 97.91% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 5379088140 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 84194 90.23% 90.23% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9121 9.77% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 93315 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108097 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105151 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89881 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108097 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 93315 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89881 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 195032 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 93315 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 201412 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 80227147 # DTB read hits -system.cpu1.dtb.read_misses 76874 # DTB read misses -system.cpu1.dtb.write_hits 72873093 # DTB write hits -system.cpu1.dtb.write_misses 28277 # DTB write misses +system.cpu1.dtb.read_hits 86913541 # DTB read hits +system.cpu1.dtb.read_misses 78813 # DTB read misses +system.cpu1.dtb.write_hits 79382446 # DTB write hits +system.cpu1.dtb.write_misses 29284 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 38283 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 38404 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3894 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4493 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10612 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 80304021 # DTB read accesses -system.cpu1.dtb.write_accesses 72901370 # DTB write accesses +system.cpu1.dtb.perms_faults 10593 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 86992354 # DTB read accesses +system.cpu1.dtb.write_accesses 79411730 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 153100240 # DTB hits -system.cpu1.dtb.misses 105151 # DTB misses -system.cpu1.dtb.accesses 153205391 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 166295987 # DTB hits +system.cpu1.dtb.misses 108097 # DTB misses +system.cpu1.dtb.accesses 166404084 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1513,763 +1534,767 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 60537 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60537 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54626 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60537 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60537 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60537 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 55171 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27009.443367 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24147.107472 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 24376.496047 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 53734 97.40% 97.40% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 967 1.75% 99.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 279 0.51% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 75 0.14% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 69 0.13% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 18 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 67294 # Table walker walks requested +system.cpu1.itb.walker.walksLong 67294 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61475 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 67294 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 67294 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 67294 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 62101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26137.727251 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23789.803797 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 22700.198457 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 60815 97.93% 97.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 864 1.39% 99.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 247 0.40% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 72 0.12% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 48 0.08% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 23 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 55171 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -589503148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -589503148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -589503148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54626 99.01% 99.01% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 545 0.99% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55171 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 62101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -17274852 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -17274852 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -17274852 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61475 98.99% 98.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 626 1.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 62101 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60537 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60537 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67294 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 67294 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55171 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55171 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 115708 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 423099313 # ITB inst hits -system.cpu1.itb.inst_misses 60537 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 129395 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 422829218 # ITB inst hits +system.cpu1.itb.inst_misses 67294 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26774 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 27014 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 423159850 # ITB inst accesses -system.cpu1.itb.hits 423099313 # DTB hits -system.cpu1.itb.misses 60537 # DTB misses -system.cpu1.itb.accesses 423159850 # DTB accesses -system.cpu1.numPwrStateTransitions 11486 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 5743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 8166193258.773638 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 240112362617.634613 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4041 70.36% 70.36% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1686 29.36% 99.72% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 8 0.14% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.91% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 4 0.07% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 422896512 # ITB inst accesses +system.cpu1.itb.hits 422829218 # DTB hits +system.cpu1.itb.misses 67294 # DTB misses +system.cpu1.itb.accesses 422896512 # DTB accesses +system.cpu1.numPwrStateTransitions 29136 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 14568 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3216976278.654242 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 84611127659.505341 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4387 30.11% 30.11% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10152 69.69% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813607762500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 5743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 506632997363 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46898447885137 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94810161765 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 7390879628476 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 14568 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 536460160065 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46864910427435 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94802741175 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5743 # number of quiesce instructions executed -system.cpu1.committedInsts 422818462 # Number of instructions committed -system.cpu1.committedOps 498817050 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 458669371 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 488965 # Number of float alu accesses -system.cpu1.num_func_calls 25225246 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 64273848 # number of instructions that are conditional controls -system.cpu1.num_int_insts 458669371 # number of integer instructions -system.cpu1.num_fp_insts 488965 # number of float instructions -system.cpu1.num_int_register_reads 669788044 # number of times the integer registers were read -system.cpu1.num_int_register_writes 364108323 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 780829 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 430972 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 109344834 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 109137409 # number of times the CC registers were written -system.cpu1.num_mem_refs 153090665 # number of memory refs -system.cpu1.num_load_insts 80223644 # Number of load instructions -system.cpu1.num_store_insts 72867021 # Number of store instructions -system.cpu1.num_idle_cycles 93796895770.272018 # Number of idle cycles -system.cpu1.num_busy_cycles 1013265994.727979 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010687 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989313 # Percentage of idle cycles -system.cpu1.Branches 94103649 # Number of branches fetched +system.cpu1.kern.inst.quiesce 14568 # number of quiesce instructions executed +system.cpu1.committedInsts 422521065 # Number of instructions committed +system.cpu1.committedOps 504842112 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 470472983 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 594254 # Number of float alu accesses +system.cpu1.num_func_calls 27792823 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 60626161 # number of instructions that are conditional controls +system.cpu1.num_int_insts 470472983 # number of integer instructions +system.cpu1.num_fp_insts 594254 # number of float instructions +system.cpu1.num_int_register_reads 624330931 # number of times the integer registers were read +system.cpu1.num_int_register_writes 367229936 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 937660 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 547764 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 91358730 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 91073731 # number of times the CC registers were written +system.cpu1.num_mem_refs 166284311 # number of memory refs +system.cpu1.num_load_insts 86908703 # Number of load instructions +system.cpu1.num_store_insts 79375608 # Number of store instructions +system.cpu1.num_idle_cycles 93729820854.868027 # Number of idle cycles +system.cpu1.num_busy_cycles 1072920320.131977 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011317 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988683 # Percentage of idle cycles +system.cpu1.Branches 93458434 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 344832107 69.09% 69.09% # Class of executed instruction -system.cpu1.op_class::IntMult 1045045 0.21% 69.30% # Class of executed instruction -system.cpu1.op_class::IntDiv 60210 0.01% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatAdd 8 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatCmp 13 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatCvt 21 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatMisc 69940 0.01% 69.33% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::MemRead 80163191 16.06% 85.39% # Class of executed instruction -system.cpu1.op_class::MemWrite 72508491 14.53% 99.92% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 60453 0.01% 99.93% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 358530 0.07% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 337624684 66.84% 66.84% # Class of executed instruction +system.cpu1.op_class::IntMult 1094737 0.22% 67.05% # Class of executed instruction +system.cpu1.op_class::IntDiv 62780 0.01% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatAdd 8 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatCmp 13 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatCvt 21 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatMisc 83819 0.02% 67.08% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::MemRead 86829386 17.19% 84.27% # Class of executed instruction +system.cpu1.op_class::MemWrite 78944532 15.63% 99.90% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 79317 0.02% 99.91% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 431076 0.09% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 499098010 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5131141 # number of replacements -system.cpu1.dcache.tags.tagsinuse 448.476526 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 147794571 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5131653 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.800578 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8379654946000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.476526 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875931 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.875931 # Average percentage of cache occupancy +system.cpu1.op_class::total 505150374 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5478037 # number of replacements +system.cpu1.dcache.tags.tagsinuse 455.042894 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 160612984 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5478549 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.316701 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8375929793000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.042894 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888756 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.888756 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 420 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 311357915 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 311357915 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 74677091 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 74677091 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 69169144 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 69169144 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167775 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 167775 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 60851 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 60851 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1670690 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1670690 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1646008 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1646008 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 143907086 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 143907086 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 144074861 # number of overall hits -system.cpu1.dcache.overall_hits::total 144074861 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2897407 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2897407 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1336766 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1336766 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634591 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 634591 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446061 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 446061 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170887 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 170887 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194464 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 194464 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4680234 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4680234 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5314825 # number of overall misses -system.cpu1.dcache.overall_misses::total 5314825 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43647010000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 43647010000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25591315500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 25591315500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9621405000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 9621405000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2591957500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2591957500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4654513500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4654513500 # number of StoreCondReq miss cycles +system.cpu1.dcache.tags.tag_accesses 338044480 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 338044480 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 80989814 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 80989814 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 75375313 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 75375313 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188638 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 188638 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 105231 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 105231 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1782566 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1782566 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1758380 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1758380 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 156470358 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 156470358 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 156658996 # number of overall hits +system.cpu1.dcache.overall_hits::total 156658996 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3115552 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3115552 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1383415 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1383415 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634948 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 634948 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 525445 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 525445 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 179669 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 179669 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202611 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 202611 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5024412 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5024412 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5659360 # number of overall misses +system.cpu1.dcache.overall_misses::total 5659360 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46416085500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 46416085500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 26188875500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 26188875500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10762345500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10762345500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2779147000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2779147000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4838630000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4838630000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2246000 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 78859730500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 78859730500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 78859730500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 78859730500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 77574498 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 77574498 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 70505910 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 70505910 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 802366 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 802366 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 506912 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 506912 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1841577 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1841577 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1840472 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1840472 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 148587320 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 148587320 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 149389686 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 149389686 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037350 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037350 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018960 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018960 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790900 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790900 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.879957 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.879957 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092794 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092794 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105660 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105660 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031498 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031498 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035577 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035577 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15064.162543 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15064.162543 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19144.199882 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19144.199882 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 21569.706834 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 21569.706834 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15167.669279 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15167.669279 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23935.090814 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23935.090814 # average StoreCondReq miss latency +system.cpu1.dcache.demand_miss_latency::cpu1.data 83367306500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 83367306500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 83367306500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 83367306500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 84105366 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 84105366 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 76758728 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 76758728 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823586 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 823586 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 630676 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 630676 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1962235 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1962235 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1960991 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1960991 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 161494770 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 161494770 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 162318356 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 162318356 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037043 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037043 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018023 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018023 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.770955 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.770955 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.833146 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.833146 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091563 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091563 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103321 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103321 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031112 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031112 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034866 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034866 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14898.189952 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14898.189952 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18930.599639 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18930.599639 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20482.344489 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 20482.344489 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15468.149764 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15468.149764 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23881.378602 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23881.378602 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16849.527289 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16849.527289 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14837.690893 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14837.690893 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16592.450321 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16592.450321 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14730.871777 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14730.871777 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5131141 # number of writebacks -system.cpu1.dcache.writebacks::total 5131141 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17932 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 17932 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 468 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 468 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44381 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44381 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 18400 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 18400 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 18400 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 18400 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879475 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2879475 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1336298 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1336298 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634591 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 634591 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446061 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 446061 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126506 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126506 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194464 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 194464 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4661834 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4661834 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5296425 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5296425 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8724 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17779 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39613799000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39613799000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24222435000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24222435000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14015397000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14015397000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9175344000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9175344000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1695802000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1695802000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4460100500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4460100500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2195000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2195000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73011578000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 73011578000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87026975000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 87026975000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1272776000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1272776000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1272776000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1272776000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037119 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037119 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018953 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018953 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790900 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790900 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879957 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879957 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068694 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068694 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105660 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105660 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031374 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031374 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035454 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035454 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13757.299160 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13757.299160 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18126.521928 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18126.521928 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22085.716627 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22085.716627 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 20569.706834 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 20569.706834 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13404.913601 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13404.913601 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22935.353073 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22935.353073 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5478037 # number of writebacks +system.cpu1.dcache.writebacks::total 5478037 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17265 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 17265 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 318 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 318 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 49763 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 49763 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 17583 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 17583 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 17583 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 17583 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3098287 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3098287 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1383097 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1383097 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634948 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 634948 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 525445 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 525445 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 129906 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 129906 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202611 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 202611 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 5006829 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 5006829 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5641777 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5641777 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22372 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22372 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21343 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 43715 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 43715 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42239304500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42239304500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24787763000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24787763000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13852353000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13852353000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10236900500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10236900500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1787997500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1787997500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4636074000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4636074000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2191000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2191000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 77263968000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 77263968000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91116321000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 91116321000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3993280500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3993280500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3993280500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3993280500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036838 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036838 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018019 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018019 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.770955 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.770955 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.833146 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.833146 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066203 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066203 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103321 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103321 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031003 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031003 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034757 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034757 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13633.115493 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13633.115493 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17921.926662 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17921.926662 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21816.515683 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21816.515683 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19482.344489 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 19482.344489 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13763.779194 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13763.779194 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.650058 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.650058 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15661.556804 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15661.556804 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16431.267317 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16431.267317 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145893.626777 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 145893.626777 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 71588.728275 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 71588.728275 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5003710 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.211749 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 418095086 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5004222 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 83.548469 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8379626352000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.211749 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15431.716961 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15431.716961 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16150.287578 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16150.287578 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178494.569104 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178494.569104 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91348.061306 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91348.061306 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5778503 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.250731 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 417050198 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5779015 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 72.166312 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8375901500000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.250731 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969240 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969240 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 129 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 851202853 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 851202853 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 418095086 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 418095086 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 418095086 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 418095086 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 418095086 # number of overall hits -system.cpu1.icache.overall_hits::total 418095086 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5004227 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5004227 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5004227 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5004227 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5004227 # number of overall misses -system.cpu1.icache.overall_misses::total 5004227 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54129933000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 54129933000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 54129933000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 54129933000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 54129933000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 54129933000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 423099313 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 423099313 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 423099313 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 423099313 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 423099313 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 423099313 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011828 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011828 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011828 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011828 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011828 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011828 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10816.842042 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10816.842042 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10816.842042 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10816.842042 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 851437456 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 851437456 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 417050198 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 417050198 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 417050198 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 417050198 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 417050198 # number of overall hits +system.cpu1.icache.overall_hits::total 417050198 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5779020 # 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number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 422829218 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 422829218 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 422829218 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 422829218 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 422829218 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013668 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013668 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013668 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013668 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013668 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013668 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10579.331703 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10579.331703 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10579.331703 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10579.331703 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5003710 # number of writebacks -system.cpu1.icache.writebacks::total 5003710 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5004227 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5004227 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5004227 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5004227 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5004227 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5004227 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 5778503 # number of writebacks +system.cpu1.icache.writebacks::total 5778503 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5779020 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5779020 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5779020 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5779020 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5779020 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5779020 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51627819500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 51627819500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51627819500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 51627819500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51627819500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 51627819500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10917500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10917500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10917500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10917500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011828 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011828 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 58248659500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58248659500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 58248659500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10594500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10594500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10594500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10594500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013668 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013668 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013668 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10079.331703 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96313.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96313.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7190671 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7190679 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 895743 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 1888854 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13151.739114 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 8987368 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1904692 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.718541 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 898577 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 1924030 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 12969.443296 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10103718 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1939825 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.208572 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12880.289345 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.911148 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 9.232940 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 244.305681 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.786150 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001093 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000564 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014911 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.802718 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 70 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 12701.469256 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 37.295961 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 26.822764 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 203.855315 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.775236 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002276 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001637 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.012442 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.791592 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 331 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15403 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 142 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 95 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 88 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 46 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1447 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5487 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7313 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1113 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 349452832 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 349452832 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 234483 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153773 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 388256 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3241183 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3241183 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6893065 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6893065 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 876408 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 876408 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4540376 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4540376 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2756982 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2756982 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 197607 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 197607 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 234483 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153773 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4540376 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3633390 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8562022 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 234483 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153773 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4540376 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3633390 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8562022 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18869 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10447 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 29316 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206667 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 206667 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194457 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 194457 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 253441 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 253441 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 463851 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 463851 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 883590 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 883590 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 248454 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 248454 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18869 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10447 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 463851 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1137031 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1630198 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18869 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10447 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 463851 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1137031 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1630198 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 633582000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 432596500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1066178500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 941410000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 941410000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 356938000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 356938000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2118500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2118500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11335810999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 11335810999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16839909000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16839909000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31901147000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31901147000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 63500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 63500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 633582000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 432596500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16839909000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 43236957999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 61143045499 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 633582000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 432596500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16839909000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 43236957999 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 61143045499 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 253352 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164220 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 417572 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3241183 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3241183 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 6893065 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 6893065 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206667 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 206667 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194457 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 194457 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1129849 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1129849 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5004227 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 5004227 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3640572 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3640572 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 446061 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 446061 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 253352 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164220 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5004227 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4770421 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10192220 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 253352 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164220 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5004227 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4770421 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10192220 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063616 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.070206 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1498 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5779 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5762 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2244 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020203 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940125 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 387081443 # 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mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220271 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220271 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092692 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.242623 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242623 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.556993 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.556993 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159467 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.212930 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.212930 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081336 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.233029 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.233029 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.496975 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.496975 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.228341 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.146333 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.228341 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227064 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30368.484786 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40166.172481 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.834003 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18917.834003 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15429.639967 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15429.639967 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 258928.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 258928.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37379.997023 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37379.997023 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30304.565475 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30068.403177 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30068.403177 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23066.823504 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23066.823504 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31260.779843 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33911.913163 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 137839.064649 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 137265.168667 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 67636.424996 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 67784.700095 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 21003363 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10784914 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 562670 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 562670 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 495353 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9225555 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 9055 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 9055 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342808 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6893668 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1123725 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 834597 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 381961 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350555 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 459411 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1160534 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1136567 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5004227 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4505940 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 508009 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 447155 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15012384 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16553521 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 345144 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 558947 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32469996 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640508408 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 639647146 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1313760 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2026816 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1283496130 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4569933 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 76953880 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 15475638 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.052337 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.222706 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.207230 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28841.495543 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41029.714216 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18762.622482 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18762.622482 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15376.182720 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15376.182720 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296249.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296249.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37930.849916 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37930.849916 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31558.655646 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30343.424178 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30343.424178 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23603.719178 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23603.719178 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31816.424545 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34523.878539 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170469.761309 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170070.233965 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87241.210111 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87245.156874 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 23256823 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11916693 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 817 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 568685 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 568681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 538115 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10263353 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 21343 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 21343 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4626226 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7781279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1111211 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 833315 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 380175 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 364314 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 469217 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1205096 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1180975 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5779020 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4693276 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 584455 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 526474 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17336763 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17662942 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 385121 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576423 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 35961249 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 739681912 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 678880625 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472080 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2095208 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1422129825 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4566671 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 79930832 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 16661362 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.048994 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.215856 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14665687 94.77% 94.77% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 809951 5.23% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 15845064 95.10% 95.10% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 816294 4.90% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 15475638 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20769928998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 16661362 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 23051952997 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 168229153 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 163764383 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7506450500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8668640000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7592764051 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8058549119 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 180924000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 201111499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 305595000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 314522000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40383 # Transaction distribution -system.iobus.trans_dist::ReadResp 40383 # Transaction distribution -system.iobus.trans_dist::WriteReq 136636 # Transaction distribution -system.iobus.trans_dist::WriteResp 136636 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47758 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40263 # Transaction distribution +system.iobus.trans_dist::ReadResp 40263 # Transaction distribution +system.iobus.trans_dist::WriteReq 136535 # Transaction distribution +system.iobus.trans_dist::WriteResp 136535 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47338 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2412,13 +2437,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122692 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47778 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353596 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47358 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2431,27 +2456,27 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155799 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155379 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496965 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36934001 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496457 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36598000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 319001 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -2459,75 +2484,75 @@ system.iobus.reqLayer16.occupancy 13000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25636500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25735000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37418000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37421000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 570101370 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570201068 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92787000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92468000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147962000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147940000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115614 # number of replacements -system.iocache.tags.tagsinuse 11.296592 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115618 # number of replacements +system.iocache.tags.tagsinuse 11.260426 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115634 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9136749782000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.841541 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.455051 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240096 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465941 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706037 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9133276021000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.412431 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.847995 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463277 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.240500 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.703777 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041054 # Number of tag accesses -system.iocache.tags.data_accesses 1041054 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040955 # Number of tag accesses +system.iocache.tags.data_accesses 1040955 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8942 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8894 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8931 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115633 # number of demand (read+write) misses -system.iocache.demand_misses::total 115673 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115622 # number of demand (read+write) misses +system.iocache.demand_misses::total 115662 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115633 # number of overall misses -system.iocache.overall_misses::total 115673 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1975225504 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1980423504 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115622 # number of overall misses +system.iocache.overall_misses::total 115662 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 2022255480 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 2027450480 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13261468866 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13261468866 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15236694370 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15242261370 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15236694370 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15242261370 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13353085588 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13353085588 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15375341068 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15380905068 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15375341068 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15380905068 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8942 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8894 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8931 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115633 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115673 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115622 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115662 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115633 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115673 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115622 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115662 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2541,53 +2566,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 221810.837058 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 221474.335048 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 227373.002024 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 227012.706304 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124254.824095 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 124254.824095 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131770.260735 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131770.260735 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 49344 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125113.237276 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125113.237276 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 132979.373026 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 132981.489755 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 132979.373026 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 132981.489755 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51037 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3519 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 14.022165 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 14.437624 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8905 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8942 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8894 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8931 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115633 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115673 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115622 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115662 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115633 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115673 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1529975504 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1533323504 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115622 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115662 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # 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number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2601,654 +2626,663 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171810.837058 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 171474.335048 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # 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Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49775 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 111 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 261 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 10351 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1155 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 44374 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.163620 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003891 # 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number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2105 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 39604 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 101630 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 753120 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 431914 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 78834 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 510748 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1546 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1542 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 53195 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 218373 # 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average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1289685 # number of replacements +system.l2c.tags.tagsinuse 65148.785380 # Cycle average of tags in use +system.l2c.tags.total_refs 5723107 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1350729 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.237051 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6059472500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 12155.679811 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 124.426191 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 138.926128 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3396.773965 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 12605.328956 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8503.765275 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 300.348884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 348.970492 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3831.795073 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 12139.257493 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11603.513111 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.185481 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001899 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002120 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.051831 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.192342 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.129757 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.005325 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.058469 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.185230 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.177056 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994092 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 12163 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 299 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48582 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 174 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 318 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 11671 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 297 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4557 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 42755 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.185593 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004562 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.741302 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 65194650 # Number of tag accesses +system.l2c.tags.data_accesses 65194650 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2495189 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2495189 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 165997 # 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average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164673.511533 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119859.378583 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109827.621226 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82989.195296 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 58807.082185 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74728.175792 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3514896 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2065226 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.115631 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.125404 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.120410 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.014025 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016453 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015328 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.622634 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.458584 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541433 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.190955 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164321 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.225381 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790941 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.417452 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.681347 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.246584 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.246584 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20138.407667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20719.933407 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20434.567817 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23987.480438 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24755.760369 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24429.993364 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98342.382231 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 103851.457660 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 100651.968310 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101484.703015 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107283.829493 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 115635.619321 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19728.771869 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19079.766042 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19612.091469 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158335.221383 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152481.962450 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 145677.383121 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76966.290508 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 78032.198659 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77279.539421 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3361893 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1995718 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 81785 # Transaction distribution -system.membus.trans_dist::ReadResp 843578 # Transaction distribution -system.membus.trans_dist::WriteReq 38414 # Transaction distribution -system.membus.trans_dist::WriteResp 38414 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1167872 # Transaction distribution -system.membus.trans_dist::CleanEvict 225685 # Transaction distribution -system.membus.trans_dist::UpgradeReq 305919 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 282864 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 43096 # Transaction distribution +system.membus.trans_dist::ReadResp 738496 # Transaction distribution +system.membus.trans_dist::WriteReq 38143 # Transaction distribution +system.membus.trans_dist::WriteResp 38143 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1107186 # Transaction distribution +system.membus.trans_dist::CleanEvict 202416 # Transaction distribution +system.membus.trans_dist::UpgradeReq 304555 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 296744 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 142258 # Transaction distribution -system.membus.trans_dist::ReadExResp 125306 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 761793 # Transaction distribution -system.membus.trans_dist::InvalidateReq 628104 # Transaction distribution -system.membus.trans_dist::InvalidateResp 29933 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122692 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 135023 # Transaction distribution +system.membus.trans_dist::ReadExResp 117908 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 695400 # Transaction distribution +system.membus.trans_dist::InvalidateReq 620101 # Transaction distribution +system.membus.trans_dist::InvalidateResp 29545 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122272 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4252247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4401047 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4639145 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155799 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25316 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3948606 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4096286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4334494 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155379 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124265196 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 124473231 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7264320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131737551 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 601899 # Total snoops (count) -system.membus.snoopTraffic 182272 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2241138 # Request fanout histogram -system.membus.snoop_fanout::mean 0.014818 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.120825 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 115505708 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 115711923 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7271808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 122983731 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 615067 # Total snoops (count) +system.membus.snoopTraffic 174144 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2133066 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015313 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.122793 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2207928 98.52% 98.52% # Request fanout histogram -system.membus.snoop_fanout::1 33210 1.48% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2100403 98.47% 98.47% # Request fanout histogram +system.membus.snoop_fanout::1 32663 1.53% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2241138 # Request fanout histogram -system.membus.reqLayer0.occupancy 100391998 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2133066 # Request fanout histogram +system.membus.reqLayer0.occupancy 100156000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21648500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21088500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7995026443 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7525887071 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4845345366 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4366874131 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 80706575 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 80052408 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3291,78 +3325,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 10666038 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5633070 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2010769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 207058 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 187933 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 19125 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 81787 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4013883 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38414 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38414 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3649317 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2329332 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 637884 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 382893 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1020777 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 286710 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 286710 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3932744 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 861229 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 844497 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8425616 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7143072 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15568688 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 207061181 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177741330 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 384802511 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2851175 # Total snoops (count) -system.toL2Bus.snoopTraffic 119274320 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7603509 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.379635 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.490452 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10343091 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5462203 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1986792 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 195863 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 175744 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 20119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 43098 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3851068 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38143 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38143 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3495681 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2217175 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 626966 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 393553 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1020519 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 123 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 273712 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 273712 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3808446 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 849023 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 832010 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7676666 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7311446 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 14988112 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 187677530 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 181320537 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 368998067 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2787811 # Total snoops (count) +system.toL2Bus.snoopTraffic 116317008 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7322753 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.391714 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.493730 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4736073 62.29% 62.29% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2848311 37.46% 99.75% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 19125 0.25% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4474450 61.10% 61.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2828184 38.62% 99.73% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 20119 0.27% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7603509 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8403909954 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7322753 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8114772770 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 9629111 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 9310827 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3830991948 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3511032286 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3536553815 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3606444627 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 9261f2548..69f18b388 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821872 # Number of seconds simulated -sim_ticks 51821872017500 # Number of ticks simulated -final_tick 51821872017500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.818011 # Number of seconds simulated +sim_ticks 51818010617500 # Number of ticks simulated +final_tick 51818010617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1130306 # Simulator instruction rate (inst/s) -host_op_rate 1328204 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68135685678 # Simulator tick rate (ticks/s) -host_mem_usage 679252 # Number of bytes of host memory used -host_seconds 760.57 # Real time elapsed on the host -sim_insts 859675526 # Number of instructions simulated -sim_ops 1010190283 # Number of ops (including micro ops) simulated +host_inst_rate 1170120 # Simulator instruction rate (inst/s) +host_op_rate 1392764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73119251351 # Simulator tick rate (ticks/s) +host_mem_usage 679172 # Number of bytes of host memory used +host_seconds 708.68 # Real time elapsed on the host +sim_insts 829238196 # Number of instructions simulated +sim_ops 987021276 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 215360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 217216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5027508 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 42852104 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 396352 # Number of bytes read from this memory -system.physmem.bytes_read::total 48708540 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5027508 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5027508 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69916032 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 290880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 276800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5155828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 53423624 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 392768 # Number of bytes read from this memory +system.physmem.bytes_read::total 59539900 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5155828 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5155828 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 81086784 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69936612 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3365 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 118962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 669577 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6193 # Number of read requests responded to by this memory -system.physmem.num_reads::total 801491 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1092438 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 81107364 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4545 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 84967 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 834757 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6137 # Number of read requests responded to by this memory +system.physmem.num_reads::total 934731 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1266981 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1095011 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 97015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 826912 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 939922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 97015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 97015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1349161 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1269554 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 99499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1030986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1149019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 99499 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 99499 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1564838 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1349558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1349161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 97015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 827309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2289480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 801491 # Number of read requests accepted -system.physmem.writeReqs 1095011 # Number of write requests accepted -system.physmem.readBursts 801491 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1095011 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 51258176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37248 # Total number of bytes read from write queue -system.physmem.bytesWritten 69934720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 48708540 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 69936612 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 582 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1565235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1564838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 99499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1031383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2714254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 934731 # Number of read requests accepted +system.physmem.writeReqs 1269554 # Number of write requests accepted +system.physmem.readBursts 934731 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1269554 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59774080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 48704 # Total number of bytes read from write queue +system.physmem.bytesWritten 81104832 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 59539900 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 81107364 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 761 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2263 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 50792 # Per bank write bursts -system.physmem.perBankRdBursts::1 52585 # Per bank write bursts -system.physmem.perBankRdBursts::2 45494 # Per bank write bursts -system.physmem.perBankRdBursts::3 47583 # Per bank write bursts -system.physmem.perBankRdBursts::4 47505 # Per bank write bursts -system.physmem.perBankRdBursts::5 55338 # Per bank write bursts -system.physmem.perBankRdBursts::6 45272 # Per bank write bursts -system.physmem.perBankRdBursts::7 44194 # Per bank write bursts -system.physmem.perBankRdBursts::8 47329 # Per bank write bursts -system.physmem.perBankRdBursts::9 89850 # Per bank write bursts -system.physmem.perBankRdBursts::10 47381 # Per bank write bursts -system.physmem.perBankRdBursts::11 49509 # Per bank write bursts -system.physmem.perBankRdBursts::12 42888 # Per bank write bursts -system.physmem.perBankRdBursts::13 45239 # Per bank write bursts -system.physmem.perBankRdBursts::14 44185 # Per bank write bursts -system.physmem.perBankRdBursts::15 45765 # Per bank write bursts -system.physmem.perBankWrBursts::0 68303 # Per bank write bursts -system.physmem.perBankWrBursts::1 72266 # Per bank write bursts -system.physmem.perBankWrBursts::2 69005 # Per bank write bursts -system.physmem.perBankWrBursts::3 70230 # Per bank write bursts -system.physmem.perBankWrBursts::4 67390 # Per bank write bursts -system.physmem.perBankWrBursts::5 74059 # Per bank write bursts -system.physmem.perBankWrBursts::6 66126 # Per bank write bursts -system.physmem.perBankWrBursts::7 65521 # Per bank write bursts -system.physmem.perBankWrBursts::8 69259 # Per bank write bursts -system.physmem.perBankWrBursts::9 70740 # Per bank write bursts -system.physmem.perBankWrBursts::10 68902 # Per bank write bursts -system.physmem.perBankWrBursts::11 68447 # Per bank write bursts -system.physmem.perBankWrBursts::12 64485 # Per bank write bursts -system.physmem.perBankWrBursts::13 66687 # Per bank write bursts -system.physmem.perBankWrBursts::14 65337 # Per bank write bursts -system.physmem.perBankWrBursts::15 65973 # Per bank write bursts +system.physmem.perBankRdBursts::0 59992 # Per bank write bursts +system.physmem.perBankRdBursts::1 60310 # Per bank write bursts +system.physmem.perBankRdBursts::2 57698 # Per bank write bursts +system.physmem.perBankRdBursts::3 58037 # Per bank write bursts +system.physmem.perBankRdBursts::4 57948 # Per bank write bursts +system.physmem.perBankRdBursts::5 67620 # Per bank write bursts +system.physmem.perBankRdBursts::6 56261 # Per bank write bursts +system.physmem.perBankRdBursts::7 53370 # Per bank write bursts +system.physmem.perBankRdBursts::8 54837 # Per bank write bursts +system.physmem.perBankRdBursts::9 66514 # Per bank write bursts +system.physmem.perBankRdBursts::10 61956 # Per bank write bursts +system.physmem.perBankRdBursts::11 59662 # Per bank write bursts +system.physmem.perBankRdBursts::12 55006 # Per bank write bursts +system.physmem.perBankRdBursts::13 54479 # Per bank write bursts +system.physmem.perBankRdBursts::14 55622 # Per bank write bursts +system.physmem.perBankRdBursts::15 54658 # Per bank write bursts +system.physmem.perBankWrBursts::0 77492 # Per bank write bursts +system.physmem.perBankWrBursts::1 79625 # Per bank write bursts +system.physmem.perBankWrBursts::2 80003 # Per bank write bursts +system.physmem.perBankWrBursts::3 79967 # Per bank write bursts +system.physmem.perBankWrBursts::4 79681 # Per bank write bursts +system.physmem.perBankWrBursts::5 86821 # Per bank write bursts +system.physmem.perBankWrBursts::6 77332 # Per bank write bursts +system.physmem.perBankWrBursts::7 76109 # Per bank write bursts +system.physmem.perBankWrBursts::8 76222 # Per bank write bursts +system.physmem.perBankWrBursts::9 83393 # Per bank write bursts +system.physmem.perBankWrBursts::10 81152 # Per bank write bursts +system.physmem.perBankWrBursts::11 79739 # Per bank write bursts +system.physmem.perBankWrBursts::12 76657 # Per bank write bursts +system.physmem.perBankWrBursts::13 78391 # Per bank write bursts +system.physmem.perBankWrBursts::14 77174 # Per bank write bursts +system.physmem.perBankWrBursts::15 77505 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 520 # Number of times write queue was full causing retry -system.physmem.totGap 51821869155500 # Total gap between requests +system.physmem.numWrRetry 469 # Number of times write queue was full causing retry +system.physmem.totGap 51818007690500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 43101 # Read request sizes (log2) +system.physmem.readPktSize::2 4701 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 758375 # Read request sizes (log2) +system.physmem.readPktSize::6 930015 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1092438 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 767476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 27687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1266981 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 899250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 547 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,185 +160,189 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 65097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 64813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 63194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 67249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 66047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 58755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 68102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 72474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 75844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 72834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 71244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 73203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 75560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 73943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 77939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 76725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 71213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 72289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 71241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 69956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 69529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1159 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 1043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1058 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 494423 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.119212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 147.459226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.994040 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 219027 44.30% 44.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 131709 26.64% 70.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 43564 8.81% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22937 4.64% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15466 3.13% 87.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9602 1.94% 89.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7396 1.50% 90.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5862 1.19% 92.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 38860 7.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 494423 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 57152 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.013543 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 134.391751 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 57148 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 57152 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 57152 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.119716 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.362666 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.513001 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 44632 78.09% 78.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9484 16.59% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 590 1.03% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 287 0.50% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 876 1.53% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 130 0.23% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 106 0.19% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 28 0.05% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 52 0.09% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 20 0.03% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 16 0.03% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 48 0.08% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 542 0.95% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 77 0.13% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 52 0.09% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 79 0.14% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 35 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 16 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 9 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 18 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 11 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::40 900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1035 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 576881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.207370 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.656879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.643014 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 255111 44.22% 44.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 152646 26.46% 70.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51224 8.88% 79.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27873 4.83% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18823 3.26% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12144 2.11% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9162 1.59% 91.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7710 1.34% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 42188 7.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 576881 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 67805 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.773807 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 23.890121 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 67793 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 67805 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 67805 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.689816 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.049494 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.758455 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 55088 81.24% 81.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9632 14.21% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 629 0.93% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 315 0.46% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 880 1.30% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 141 0.21% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 113 0.17% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 35 0.05% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 64 0.09% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.02% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 17 0.03% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 38 0.06% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 506 0.75% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 74 0.11% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 50 0.07% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 77 0.11% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 34 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 13 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 4 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 19 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 9 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::196-199 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 57152 # Writes before turning the bus around for reads -system.physmem.totQLat 29342800943 # Total ticks spent queuing -system.physmem.totMemAccLat 44359844693 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4004545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36636.87 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 67805 # Writes before turning the bus around for reads +system.physmem.totQLat 32840058772 # Total ticks spent queuing +system.physmem.totMemAccLat 50351996272 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4669850000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35161.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55386.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53911.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing -system.physmem.readRowHits 600164 # Number of row buffer hits during reads -system.physmem.writeRowHits 799051 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.94 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.12 # Row buffer hit rate for writes -system.physmem.avgGap 27324974.69 # Average gap between requests -system.physmem.pageHitRate 73.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1814238300 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 964290525 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2775767820 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2886138000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 48823313760.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 38608999590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3011693280 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 94024683450 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 72592857120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12330153384360 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12595677850665 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.057176 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51728729641480 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 5702683750 # Time in different power states -system.physmem_0.memoryStateTime::REF 20763204000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51334071775500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 189043780464 # Time in different power states -system.physmem_0.memoryStateTime::ACT 66096536270 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 206194037516 # Time in different power states -system.physmem_1.actEnergy 1715949060 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 912044760 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2942722440 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2817912600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 46334636400.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 38117726280 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2754271680 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 87558235230 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 69416939040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12335402832360 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12587993852010 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.908898 # Core power per rank (mW) -system.physmem_1.totalIdleTime 51731061753764 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 5083631742 # Time in different power states -system.physmem_1.memoryStateTime::REF 19704542000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51358275119250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 180773350699 # Time in different power states -system.physmem_1.memoryStateTime::ACT 66022048244 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 192013325565 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing +system.physmem.readRowHits 700734 # Number of row buffer hits during reads +system.physmem.writeRowHits 923617 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.88 # Row buffer hit rate for writes +system.physmem.avgGap 23507852.97 # Average gap between requests +system.physmem.pageHitRate 73.79 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2121758100 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1127741175 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3364625040 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3325296600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 53356283760.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 43527513060 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3305473920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 105977484840 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 78284868000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12316974110865 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12611384893410 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.378407 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51713320513020 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 6156853750 # Time in different power states +system.physmem_0.memoryStateTime::REF 22684760000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51277629948750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 203866794298 # Time in different power states +system.physmem_0.memoryStateTime::ACT 75265891230 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 232406369472 # Time in different power states +system.physmem_1.actEnergy 1997179380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1061522220 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3303920760 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3289816260 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 51035403120.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 42719469090 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3040212960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 99255699990 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 75177553440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12322732679115 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12603635909925 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.228865 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51716360660558 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5564281492 # Time in different power states +system.physmem_1.memoryStateTime::REF 21699622000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51302919507000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 195774926499 # Time in different power states +system.physmem_1.memoryStateTime::ACT 74386011700 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 217666268809 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -355,9 +359,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -365,7 +369,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -395,75 +399,75 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 196189 # Table walker walks requested -system.cpu.dtb.walker.walksLong 196189 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 13637 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 152377 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 216211 # Table walker walks requested +system.cpu.dtb.walker.walksLong 216211 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16346 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 167307 # Level at which table walker walks with long descriptors terminate system.cpu.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 196170 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.152929 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 48.843369 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 196168 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::samples 216192 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.138766 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 46.526694 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 216190 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 196170 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 166033 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23680.132865 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 19678.566540 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 19257.699461 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 164361 98.99% 98.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 1402 0.84% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 64 0.04% 99.88% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 64 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 59 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 17 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 48 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::total 216192 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 183672 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24269.346988 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20148.872722 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20272.280127 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 181570 98.86% 98.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 1738 0.95% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 90 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 74 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 86 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 33 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 8 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 59 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 166033 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -7075428332 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.933158 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.249747 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -472932796 6.68% 6.68% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 -6602495536 93.32% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -7075428332 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 152378 91.79% 91.79% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 13637 8.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 166015 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 196189 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 183672 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 2036554556 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.701695 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.457514 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 607514500 29.83% 29.83% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 1429040056 70.17% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 2036554556 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 167308 91.10% 91.10% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16346 8.90% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 183654 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 216211 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 196189 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 166015 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 216211 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183654 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 166015 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 362204 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183654 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 399865 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 161617169 # DTB read hits -system.cpu.dtb.read_misses 145721 # DTB read misses -system.cpu.dtb.write_hits 146821389 # DTB write hits -system.cpu.dtb.write_misses 50468 # DTB write misses +system.cpu.dtb.read_hits 169128390 # DTB read hits +system.cpu.dtb.read_misses 159496 # DTB read misses +system.cpu.dtb.write_hits 153929844 # DTB write hits +system.cpu.dtb.write_misses 56715 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72934 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 43399 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 75955 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 7326 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8791 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19275 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 161762890 # DTB read accesses -system.cpu.dtb.write_accesses 146871857 # DTB write accesses +system.cpu.dtb.perms_faults 20041 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 169287886 # DTB read accesses +system.cpu.dtb.write_accesses 153986559 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 308438558 # DTB hits -system.cpu.dtb.misses 196189 # DTB misses -system.cpu.dtb.accesses 308634747 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 323058234 # DTB hits +system.cpu.dtb.misses 216211 # DTB misses +system.cpu.dtb.accesses 323274445 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -493,833 +497,831 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 120716 # Table walker walks requested -system.cpu.itb.walker.walksLong 120716 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1119 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 108836 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 120716 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 120716 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 120716 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 109955 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27513.978446 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23291.832317 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24606.943327 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 107988 98.21% 98.21% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 1629 1.48% 99.69% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 80 0.07% 99.77% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 85 0.08% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 60 0.05% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 77 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 123370 # Table walker walks requested +system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1116 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 111000 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 112116 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27477.773021 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23151.580183 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24996.246984 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 109776 97.91% 97.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1925 1.72% 99.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 106 0.09% 99.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 116 0.10% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 77 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 36 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 73 0.07% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 109955 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -556629296 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -556629296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -556629296 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 108836 98.98% 98.98% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1119 1.02% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 109955 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 112116 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 523074000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 523074000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 523074000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 111000 99.00% 99.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1116 1.00% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 112116 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 120716 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 120716 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109955 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 109955 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 230671 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 860205714 # ITB inst hits -system.cpu.itb.inst_misses 120716 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112116 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 112116 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 235486 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 829831290 # ITB inst hits +system.cpu.itb.inst_misses 123370 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52133 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 43399 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 54054 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 860326430 # ITB inst accesses -system.cpu.itb.hits 860205714 # DTB hits -system.cpu.itb.misses 120716 # DTB misses -system.cpu.itb.accesses 860326430 # DTB accesses -system.cpu.numPwrStateTransitions 32324 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16162 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3111484469.414615 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60405660268.224297 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 6871 42.51% 42.51% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9256 57.27% 99.78% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 829954660 # ITB inst accesses +system.cpu.itb.hits 829831290 # DTB hits +system.cpu.itb.misses 123370 # DTB misses +system.cpu.itb.accesses 829954660 # DTB accesses +system.cpu.numPwrStateTransitions 32736 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16368 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3071765118.618646 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59759289847.266548 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7078 43.24% 43.24% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9254 56.54% 99.78% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 6 0.04% 99.82% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16162 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1534060022821 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50287811994679 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 103643744035 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988775098960 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16368 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1539359155950 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50278651461550 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 103636021235 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16162 # number of quiesce instructions executed -system.cpu.committedInsts 859675526 # Number of instructions committed -system.cpu.committedOps 1010190283 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 928076114 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 896946 # Number of float alu accesses -system.cpu.num_func_calls 51280324 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 130830869 # number of instructions that are conditional controls -system.cpu.num_int_insts 928076114 # number of integer instructions -system.cpu.num_fp_insts 896946 # number of float instructions -system.cpu.num_int_register_reads 1348653813 # number of times the integer registers were read -system.cpu.num_int_register_writes 735932841 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1446833 # number of times the floating registers were read -system.cpu.num_fp_register_writes 759084 # number of times the floating registers were written -system.cpu.num_cc_register_reads 224374440 # number of times the CC registers were read -system.cpu.num_cc_register_writes 223774216 # number of times the CC registers were written -system.cpu.num_mem_refs 308419372 # number of memory refs -system.cpu.num_load_insts 161608555 # Number of load instructions -system.cpu.num_store_insts 146810817 # Number of store instructions -system.cpu.num_idle_cycles 100575623989.356064 # Number of idle cycles -system.cpu.num_busy_cycles 3068120045.643941 # Number of busy cycles -system.cpu.not_idle_fraction 0.029603 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970397 # Percentage of idle cycles -system.cpu.Branches 191908708 # Number of branches fetched +system.cpu.kern.inst.quiesce 16368 # number of quiesce instructions executed +system.cpu.committedInsts 829238196 # Number of instructions committed +system.cpu.committedOps 987021276 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 918155469 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 894809 # Number of float alu accesses +system.cpu.num_func_calls 53301366 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 119804511 # number of instructions that are conditional controls +system.cpu.num_int_insts 918155469 # number of integer instructions +system.cpu.num_fp_insts 894809 # number of float instructions +system.cpu.num_int_register_reads 1221916718 # number of times the integer registers were read +system.cpu.num_int_register_writes 717363924 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1441242 # number of times the floating registers were read +system.cpu.num_fp_register_writes 760964 # number of times the floating registers were written +system.cpu.num_cc_register_reads 183477837 # number of times the CC registers were read +system.cpu.num_cc_register_writes 182884399 # number of times the CC registers were written +system.cpu.num_mem_refs 323042928 # number of memory refs +system.cpu.num_load_insts 169122320 # Number of load instructions +system.cpu.num_store_insts 153920608 # Number of store instructions +system.cpu.num_idle_cycles 100557302923.098053 # Number of idle cycles +system.cpu.num_busy_cycles 3078718311.901940 # Number of busy cycles +system.cpu.not_idle_fraction 0.029707 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970293 # Percentage of idle cycles +system.cpu.Branches 183328759 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 699966855 69.25% 69.25% # Class of executed instruction -system.cpu.op_class::IntMult 2168337 0.21% 69.47% # Class of executed instruction -system.cpu.op_class::IntDiv 97451 0.01% 69.48% # Class of executed instruction -system.cpu.op_class::FloatAdd 8 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatCmp 13 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 21 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatMisc 111537 0.01% 69.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::MemRead 161496118 15.98% 85.46% # Class of executed instruction -system.cpu.op_class::MemWrite 146137887 14.46% 99.92% # Class of executed instruction -system.cpu.op_class::FloatMemRead 112437 0.01% 99.93% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 672930 0.07% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 662135321 67.04% 67.04% # Class of executed instruction +system.cpu.op_class::IntMult 2232133 0.23% 67.27% # Class of executed instruction +system.cpu.op_class::IntDiv 98376 0.01% 67.28% # Class of executed instruction +system.cpu.op_class::FloatAdd 8 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatCvt 21 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatMisc 110293 0.01% 67.29% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::MemRead 169008582 17.11% 84.40% # Class of executed instruction +system.cpu.op_class::MemWrite 153249872 15.52% 99.92% # Class of executed instruction +system.cpu.op_class::FloatMemRead 113738 0.01% 99.93% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 670736 0.07% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1010763595 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9712819 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.962733 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 298526964 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9713331 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.733737 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3801165500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.962733 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999927 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy +system.cpu.op_class::total 987619094 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 10318810 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994503 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 312537175 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10319322 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.286600 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 585910500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994503 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1243130616 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1243130616 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 151166129 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 151166129 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 139372457 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 139372457 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 383388 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 383388 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 333792 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 333792 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3475542 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3475542 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3766859 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3766859 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 290872378 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 290872378 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 291255766 # number of overall hits -system.cpu.dcache.overall_hits::total 291255766 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5061632 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5061632 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2072136 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2072136 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1203806 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1203806 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1225587 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1225587 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 292986 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 292986 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8359355 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8359355 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9563161 # number of overall misses -system.cpu.dcache.overall_misses::total 9563161 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 86410296000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 86410296000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64078644000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64078644000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 24971401500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 24971401500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4471115500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4471115500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 167500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 175460341500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 175460341500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 175460341500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 175460341500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 156227761 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 156227761 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 141444593 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 141444593 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1587194 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1587194 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1559379 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1559379 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3768528 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3768528 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3766861 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3766861 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 299231733 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 299231733 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 300818927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 300818927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032399 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032399 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014650 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014650 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758449 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.758449 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785946 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.785946 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077745 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077745 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.027936 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.027936 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031790 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031790 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17071.627491 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17071.627491 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30923.956729 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30923.956729 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20375.054158 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20375.054158 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15260.509035 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15260.509035 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83750 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20989.698547 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20989.698547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18347.525625 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18347.525625 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1302212841 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1302212841 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 157972571 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 157972571 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 146050984 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 146050984 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 397864 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 397864 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 335205 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 335205 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3722931 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3722931 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4027066 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4027066 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 304358760 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 304358760 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 304756624 # number of overall hits +system.cpu.dcache.overall_hits::total 304756624 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5371907 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5371907 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2231014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2231014 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1323692 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1323692 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1234314 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1234314 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 305825 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 305825 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 8837235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8837235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10160927 # number of overall misses +system.cpu.dcache.overall_misses::total 10160927 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 92847463000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 92847463000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76601172000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76601172000 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 25428557000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 25428557000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4806019500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4806019500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 194877192000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 194877192000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 194877192000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 194877192000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 163344478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 163344478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 148281998 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 148281998 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1721556 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1721556 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1569519 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1569519 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4028756 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4028756 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4027067 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4027067 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 313195995 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 313195995 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 314917551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 314917551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032887 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032887 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015046 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015046 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.768893 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.768893 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786428 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786428 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.075911 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.075911 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.028216 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.028216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032265 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032265 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17283.892480 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17283.892480 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34334.689070 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34334.689070 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20601.368047 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20601.368047 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15714.933377 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15714.933377 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22051.828655 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22051.828655 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19179.076082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19179.076082 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7496626 # number of writebacks -system.cpu.dcache.writebacks::total 7496626 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21661 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21661 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21294 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21294 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70691 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 70691 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 42955 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 42955 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 42955 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 42955 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5039971 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5039971 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2050842 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2050842 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1203452 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1203452 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1225587 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1225587 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 222295 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 222295 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8316400 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8316400 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9519852 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9519852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80495651000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 80495651000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61277537000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61277537000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21572116000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21572116000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 23745814500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 23745814500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3066936500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3066936500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165519002500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 165519002500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187091118500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187091118500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6232858500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6232858500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6232858500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6232858500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032260 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032260 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014499 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014499 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.758226 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.758226 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785946 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785946 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058987 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058987 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027793 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027793 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031646 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031646 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15971.451225 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15971.451225 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29879.209125 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29879.209125 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17925.198512 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17925.198512 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19375.054158 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19375.054158 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13796.695832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13796.695832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82750 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82750 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.722632 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.722632 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.733940 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.733940 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.367650 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.367650 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.697935 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.697935 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 13486266 # number of replacements -system.cpu.icache.tags.tagsinuse 511.886684 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 846718931 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13486778 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 62.781409 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 32464203500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.886684 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999779 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999779 # Average percentage of cache occupancy +system.cpu.dcache.writebacks::writebacks 7954497 # number of writebacks +system.cpu.dcache.writebacks::total 7954497 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22835 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22835 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21214 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21214 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 72449 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 72449 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 44049 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44049 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 44049 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44049 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5349072 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5349072 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2209800 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2209800 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1323336 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1323336 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1234314 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1234314 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233376 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 233376 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 8793186 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8793186 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 10116522 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 10116522 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33620 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33620 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33624 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33624 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67244 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67244 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86573126000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 86573126000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73656101500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73656101500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23406113500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23406113500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 24194243000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 24194243000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3299673500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3299673500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 184423470500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 184423470500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207829584000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 207829584000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6212445000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6212445000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6212445000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6212445000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032747 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032747 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014903 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014903 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.768686 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.768686 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786428 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786428 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057928 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057928 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028076 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16184.700075 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16184.700075 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33331.569147 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33331.569147 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17687.203779 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17687.203779 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19601.368047 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19601.368047 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14138.872463 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14138.872463 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20973.452683 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20973.452683 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20543.580491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20543.580491 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184784.205830 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184784.205830 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92386.606984 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92386.606984 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 13796932 # number of replacements +system.cpu.icache.tags.tagsinuse 511.918468 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 816033841 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13797444 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.143841 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 29242894500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.918468 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999841 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999841 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 873692497 # Number of tag accesses -system.cpu.icache.tags.data_accesses 873692497 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 846718931 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 846718931 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 846718931 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 846718931 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 846718931 # number of overall hits -system.cpu.icache.overall_hits::total 846718931 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13486783 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13486783 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13486783 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13486783 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13486783 # number of overall misses -system.cpu.icache.overall_misses::total 13486783 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 183511474500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 183511474500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 183511474500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 183511474500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 183511474500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 183511474500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 860205714 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 860205714 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 860205714 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 860205714 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 860205714 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 860205714 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015679 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015679 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015679 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015679 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015679 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015679 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13606.764082 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13606.764082 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13606.764082 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13606.764082 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13606.764082 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13606.764082 # average overall miss latency +system.cpu.icache.tags.tag_accesses 843628739 # Number of tag accesses +system.cpu.icache.tags.data_accesses 843628739 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 816033841 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 816033841 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 816033841 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 816033841 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 816033841 # number of overall hits +system.cpu.icache.overall_hits::total 816033841 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13797449 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13797449 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13797449 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13797449 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13797449 # number of overall misses +system.cpu.icache.overall_misses::total 13797449 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188051577000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188051577000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188051577000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188051577000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188051577000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188051577000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 829831290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 829831290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 829831290 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 829831290 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 829831290 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 829831290 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016627 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016627 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016627 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016627 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016627 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016627 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13629.445342 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13629.445342 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13629.445342 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13629.445342 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13629.445342 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13629.445342 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 13486266 # number of writebacks -system.cpu.icache.writebacks::total 13486266 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13486783 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13486783 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13486783 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 13486783 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 13486783 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 13486783 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170024691500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170024691500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170024691500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170024691500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170024691500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170024691500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3557271000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3557271000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3557271000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 3557271000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015679 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015679 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015679 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12606.764082 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12606.764082 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12606.764082 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12606.764082 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12606.764082 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12606.764082 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82487.443478 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82487.443478 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1158711 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65407.211772 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 44429708 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1220523 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 36.402188 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6958052500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10958.963563 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 463.658135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 540.023475 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6661.801500 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46782.765099 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.167221 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007075 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.008240 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101651 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.713848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998035 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 301 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61511 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 301 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 815 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5756 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54668 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004593 # 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number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4545 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4325 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 80279 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 835938 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 925087 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4545 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4325 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 80279 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 835938 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 925087 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 4725 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33620 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 38345 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33624 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33624 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 4725 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67244 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 71969 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 549421500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 480421500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1029843000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 73648000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 73648000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 47289965000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 47289965000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8446072500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8446072500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30475204536 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30475204536 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9640713000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9640713000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 549421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 480421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8446072500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77765169536 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87241085036 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 549421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 480421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8446072500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77765169536 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87241085036 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340544500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5791390500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6131935000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340544500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5791390500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6131935000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015087 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.126436 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.126436 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205178 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205178 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005626 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039575 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039575 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.406019 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.406019 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079027 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.033459 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079027 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.033459 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118553.114366 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19035.696008 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19035.696008 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88585.610503 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88585.610503 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104789.855550 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104789.855550 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 107848.866012 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 107848.866012 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18664.248451 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18664.248451 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104789.855550 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95934.159906 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 97028.937094 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104789.855550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95934.159906 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 97028.937094 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.395657 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.693691 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.083482 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.220099 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 46927036 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23726903 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1976 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1976 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.251639 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.251639 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005818 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.041640 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.041640 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.418461 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.418461 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.092013 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.039415 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.092013 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039415 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 116104.058625 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19064.975408 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19064.975408 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86235.286287 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86235.286287 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 105208.989898 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 105208.989898 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105980.436911 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105980.436911 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18665.031984 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18665.031984 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 105208.989898 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 93027.436886 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94305.816681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 105208.989898 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 93027.436886 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94305.816681 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 72072.910053 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172260.276621 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159914.852002 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 72072.910053 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86125.014871 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85202.448276 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 48796648 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 24679855 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1750 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2089 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1011319 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20964705 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8482434 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13486266 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2389096 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 28798 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 28800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2022047 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2022047 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13486783 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6468652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1256381 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1225599 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40546082 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29332849 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 592477 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 884181 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 71355589 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1726447636 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023248134 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1853792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2483568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2754033130 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1585660 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66286896 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 25466403 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019742 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.139111 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1038155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21742291 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9114847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13796932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2555043 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 30556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 30557 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2179247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2179247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13797449 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6908747 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1261981 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1234328 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41401280 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31154016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 602385 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 985352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 74143033 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1766059284 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1090777710 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1869336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2834080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2861540410 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1794516 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 77615256 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 26600840 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.020202 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.140692 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24963657 98.03% 98.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 502746 1.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 26063442 97.98% 97.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 537398 2.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25466403 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 44736270000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 26600840 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 46435675500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1643382 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1669386 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20273299500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20700898500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13409418464 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14310442440 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 360753000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 368718000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 573735000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 631092000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40342 # Transaction distribution -system.iobus.trans_dist::ReadResp 40342 # Transaction distribution -system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 136571 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40260 # Transaction distribution +system.iobus.trans_dist::ReadResp 40260 # Transaction distribution +system.iobus.trans_dist::WriteReq 136485 # Transaction distribution +system.iobus.trans_dist::WriteResp 136485 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1332,13 +1334,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353490 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1351,13 +1353,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334600 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334632 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492520 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42151500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41845500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1379,75 +1381,75 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25717000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25729000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38602500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38606000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569022926 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569335764 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147802000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147810000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115502 # number of replacements -system.iocache.tags.tagsinuse 10.457099 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115507 # number of replacements +system.iocache.tags.tagsinuse 10.457942 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115518 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115523 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13154766854000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.510741 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946357 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219421 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434147 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653569 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13151557544000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511326 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946616 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219458 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434164 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653621 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040046 # Number of tag accesses -system.iocache.tags.data_accesses 1040046 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040082 # Number of tag accesses +system.iocache.tags.data_accesses 1040082 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8857 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8894 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8861 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8898 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115521 # number of demand (read+write) misses -system.iocache.demand_misses::total 115561 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115525 # number of demand (read+write) misses +system.iocache.demand_misses::total 115565 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115521 # number of overall misses -system.iocache.overall_misses::total 115561 # number of overall misses +system.iocache.overall_misses::realview.ide 115525 # number of overall misses +system.iocache.overall_misses::total 115565 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 2023754150 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 2028840650 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1980781165 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1985867665 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13483489276 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13483489276 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13389793099 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13389793099 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15507243426 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15512680926 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15370574264 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15376011764 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15507243426 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15512680926 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15370574264 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15376011764 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8857 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8894 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8861 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8898 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115521 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115561 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115525 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115565 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115521 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115561 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115525 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115565 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1462,52 +1464,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 228492.057130 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 228113.407915 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 223539.235414 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 223181.351427 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126410.872234 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126410.872234 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125532.448614 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125532.448614 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 134237.441037 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 134238.029491 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 133049.766406 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 133050.765924 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 134237.441037 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 134238.029491 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 52159 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 133049.766406 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 133050.765924 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 49780 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3349 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3342 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 15.574500 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 14.895272 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8857 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8861 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8898 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115521 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115561 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115525 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115565 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115521 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115561 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115525 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115565 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1580904150 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1584140650 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1537731165 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1540967665 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8144739087 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8144739087 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8050946475 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8050946475 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9725643237 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9729080737 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9588677640 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9592115140 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9725643237 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9729080737 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9588677640 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9592115140 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1522,95 +1524,95 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 178492.057130 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 178113.407915 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 173539.235414 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 173181.351427 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76358.837912 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76358.837912 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75479.510191 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75479.510191 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 84189.396188 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 84190.001272 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 83000.888466 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 83001.904902 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 84189.396188 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 84190.001272 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 2644146 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1308848 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.overall_avg_mshr_miss_latency::realview.ide 83000.888466 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 83001.904902 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 3026927 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1497963 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3722 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 76831 # Transaction distribution -system.membus.trans_dist::ReadResp 424240 # Transaction distribution -system.membus.trans_dist::WriteReq 33710 # Transaction distribution -system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1092438 # Transaction distribution -system.membus.trans_dist::CleanEvict 180711 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4469 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 414321 # Transaction distribution -system.membus.trans_dist::ReadExResp 414321 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 347409 # Transaction distribution -system.membus.trans_dist::InvalidateReq 604276 # Transaction distribution -system.membus.trans_dist::InvalidateResp 30630 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38345 # Transaction distribution +system.membus.trans_dist::ReadResp 423947 # Transaction distribution +system.membus.trans_dist::WriteReq 33624 # Transaction distribution +system.membus.trans_dist::WriteResp 33624 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1266981 # Transaction distribution +system.membus.trans_dist::CleanEvict 198449 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4422 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 547827 # Transaction distribution +system.membus.trans_dist::ReadExResp 547827 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 385602 # Transaction distribution +system.membus.trans_dist::InvalidateReq 623176 # Transaction distribution +system.membus.trans_dist::InvalidateResp 27559 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3256123 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3385827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3623083 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3733842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3863202 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4100411 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 111424480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 111594330 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7220672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 118815002 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 33993 # Total snoops (count) -system.membus.snoopTraffic 214720 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1481018 # Request fanout histogram -system.membus.snoop_fanout::mean 0.023235 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.150648 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 133430112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 133599618 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7217152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7217152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 140816770 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 30980 # Total snoops (count) +system.membus.snoopTraffic 218496 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1632997 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019173 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.137134 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1446607 97.68% 97.68% # Request fanout histogram -system.membus.snoop_fanout::1 34411 2.32% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1601687 98.08% 98.08% # Request fanout histogram +system.membus.snoop_fanout::1 31310 1.92% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1481018 # Request fanout histogram -system.membus.reqLayer0.occupancy 106898000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1632997 # Request fanout histogram +system.membus.reqLayer0.occupancy 106607500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5816000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5784000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7183768776 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8217045206 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4201020680 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5023572568 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 76902808 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 73701370 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1653,28 +1655,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |