diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
| commit | 93c0307d418e08db609818f19f5d2b02d45e7465 (patch) | |
| tree | 1f72a6617fb4a74d904a933bc48136fa0760bd19 /tests/long/fs | |
| parent | f2db2a96d181f796e6e475121f10230b9d1d007f (diff) | |
| download | gem5-93c0307d418e08db609818f19f5d2b02d45e7465.tar.xz | |
tests: Update regressions for the new kernels and various preceeding fixes.
Diffstat (limited to 'tests/long/fs')
63 files changed, 17502 insertions, 14787 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini index 20e3fa665..330249aa1 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,8 +26,8 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/dist/binaries/ts_osfpal +readfile=/work/gem5.latest/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -691,7 +691,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -714,7 +714,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -844,6 +844,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -894,7 +895,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr index 20fe2d682..518507880 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout index 089dd6b05..cc37eeb13 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:41:53 -gem5 started May 7 2014 10:52:34 -gem5 executing on cz3212c2d7 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor +gem5 compiled Oct 29 2014 09:12:51 +gem5 started Oct 29 2014 09:20:31 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1885187323500 because m5_exit instruction encountered +Exiting @ tick 1883224346500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 498e99dcf..85db7b5af 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.883224 # Nu sim_ticks 1883224346500 # Number of ticks simulated final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 293967 # Simulator instruction rate (inst/s) -host_op_rate 293967 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9864607727 # Simulator tick rate (ticks/s) -host_mem_usage 317632 # Number of bytes of host memory used -host_seconds 190.91 # Real time elapsed on the host +host_inst_rate 279379 # Simulator instruction rate (inst/s) +host_op_rate 279379 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9375076807 # Simulator tick rate (ticks/s) +host_mem_usage 311380 # Number of bytes of host memory used +host_seconds 200.88 # Real time elapsed on the host sim_insts 56120453 # Number of instructions simulated sim_ops 56120453 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -409,8 +409,6 @@ system.iocache.fast_writes 41552 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses @@ -425,16 +423,14 @@ system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60470.207379 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60470.207379 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index f8b77d3d8..9efbaffcd 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,8 +26,8 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/dist/binaries/ts_osfpal +readfile=/work/gem5.latest/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -1099,7 +1099,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -1122,7 +1122,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -1287,6 +1287,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -1337,7 +1338,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index c0d08bdf9..518507880 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -1,5 +1,5 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything -warn: Obsolete M5 ivlb instruction encountered. diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index d865b26f6..c80d76784 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 10:36:29 -gem5 started Jun 21 2014 13:05:58 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +gem5 compiled Oct 29 2014 09:12:51 +gem5 started Oct 29 2014 09:21:02 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 121062000 -Exiting @ tick 1906207240000 because m5_exit instruction encountered +info: Launching CPU 1 @ 119596000 +Exiting @ tick 1905067807000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 6b49ba8d7..7598617b8 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.905068 # Nu sim_ticks 1905067807000 # Number of ticks simulated final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133407 # Simulator instruction rate (inst/s) -host_op_rate 133407 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4441980470 # Simulator tick rate (ticks/s) -host_mem_usage 322876 # Number of bytes of host memory used -host_seconds 428.88 # Real time elapsed on the host +host_inst_rate 163944 # Simulator instruction rate (inst/s) +host_op_rate 163944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5458738398 # Simulator tick rate (ticks/s) +host_mem_usage 318552 # Number of bytes of host memory used +host_seconds 348.99 # Real time elapsed on the host sim_insts 57215334 # Number of instructions simulated sim_ops 57215334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -739,8 +739,6 @@ system.iocache.fast_writes 41552 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses @@ -755,16 +753,14 @@ system.iocache.overall_mshr_miss_latency::tsunami.ide 12381383 system.iocache.overall_mshr_miss_latency::total 12381383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999952 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999952 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60474.936465 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60474.936465 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 30c3fd76c..bce635119 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,8 +26,8 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/dist/binaries/ts_osfpal +readfile=/work/gem5.latest/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -640,7 +640,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -663,7 +663,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -793,6 +793,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -843,7 +844,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr index 20fe2d682..518507880 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index e834a5489..2666e2b50 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 10:36:29 -gem5 started Jun 21 2014 13:05:52 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 +gem5 compiled Oct 29 2014 09:12:51 +gem5 started Oct 29 2014 09:20:51 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1860172195000 because m5_exit instruction encountered +Exiting @ tick 1859038679000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 9bbc0f37f..987719302 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.859039 # Nu sim_ticks 1859038679000 # Number of ticks simulated final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145866 # Simulator instruction rate (inst/s) -host_op_rate 145866 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5123409698 # Simulator tick rate (ticks/s) -host_mem_usage 320704 # Number of bytes of host memory used -host_seconds 362.85 # Real time elapsed on the host +host_inst_rate 164458 # Simulator instruction rate (inst/s) +host_op_rate 164458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5776457310 # Simulator tick rate (ticks/s) +host_mem_usage 314484 # Number of bytes of host memory used +host_seconds 321.83 # Real time elapsed on the host sim_insts 52927600 # Number of instructions simulated sim_ops 52927600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -420,8 +420,6 @@ system.iocache.fast_writes 41552 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses @@ -436,16 +434,14 @@ system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.997935 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.997935 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60880.680280 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60880.680280 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index 7ff9bd533..3940f534b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,8 +26,8 @@ mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/dist/binaries/ts_osfpal +readfile=/work/gem5.latest/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -697,7 +697,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -720,7 +720,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -885,6 +885,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -935,7 +936,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr index b501a6b40..518507880 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr @@ -1,8 +1,5 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout index f92b070f8..9fb7b2d24 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 10:36:29 -gem5 started Jun 21 2014 13:11:51 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full +gem5 compiled Oct 29 2014 09:12:51 +gem5 started Oct 29 2014 09:24:03 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index d190e77d2..def1f96ac 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.841612 # Nu sim_ticks 1841612450000 # Number of ticks simulated final_tick 1841612450000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216403 # Simulator instruction rate (inst/s) -host_op_rate 216403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6103470891 # Simulator tick rate (ticks/s) -host_mem_usage 319676 # Number of bytes of host memory used -host_seconds 301.73 # Real time elapsed on the host +host_inst_rate 223623 # Simulator instruction rate (inst/s) +host_op_rate 223623 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6307109470 # Simulator tick rate (ticks/s) +host_mem_usage 313464 # Number of bytes of host memory used +host_seconds 291.99 # Real time elapsed on the host sim_insts 65295558 # Number of instructions simulated sim_ops 65295558 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -737,8 +737,6 @@ system.iocache.fast_writes 41552 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses @@ -753,16 +751,14 @@ system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60157.282465 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60157.282465 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini index a0c959df8..d98200efd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini @@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename= +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 -flags_addr=268435504 -gic_cpu_addr=520093952 +flags_addr=469827632 +gic_cpu_addr=738205696 have_generic_timer=false have_large_asid_64=false have_lpae=false @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 -load_offset=0 -machine_type=RealView_PBX +load_offset=2147483648 +machine_type=VExpress_EMM mem_mode=timing -mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -53,14 +53,14 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[0] +system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=268435456:520093695 1073741824:1610612735 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -705,6 +705,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu0.istage2_mmu] @@ -1424,6 +1425,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu1.istage2_mmu] @@ -1561,15 +1563,16 @@ type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 -use_default_range=false +use_default_range=true width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] type=BaseCache children=tags -addr_ranges=0:134217727 +addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain eventq_index=0 @@ -1588,8 +1591,8 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[26] -mem_side=system.membus.slave[2] +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] [system.iocache.tags] type=LRU @@ -1624,7 +1627,7 @@ tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c.tags] type=LRU @@ -1647,8 +1650,8 @@ system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -1704,6 +1707,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -1713,7 +1717,7 @@ mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive -range=0:134217727 +range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1742,46 +1746,37 @@ tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 -port=system.membus.master[6] +port=system.membus.master[5] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=0 +pci_cfg_base=805306368 pci_cfg_gen_offsets=false pci_io_base=0 system=system -[system.realview.a9scu] -type=A9SCU -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=520093696 -pio_latency=100000 -system=system -pio=system.membus.master[4] - [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268451840 +pio_addr=470024192 pio_latency=100000 system=system -pio=system.iobus.master[21] +pio=system.iobus.master[18] [system.realview.cf_ctrl] type=IdeController -BAR0=402653184 +BAR0=471465984 BAR0LegacyIO=true -BAR0Size=16 -BAR1=402653440 +BAR0Size=256 +BAR1=471466240 BAR1LegacyIO=true -BAR1Size=1 +BAR1Size=4096 BAR2=1 BAR2LegacyIO=false BAR2Size=8 @@ -1851,18 +1846,18 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 -disks=system.cf0 +disks= eventq_index=0 -io_shift=1 +io_shift=2 pci_bus=2 -pci_dev=7 +pci_dev=0 pci_func=0 pio_latency=30000 platform=system.realview system=system -config=system.iobus.master[8] +config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.clcd] type=Pl111 @@ -1871,8 +1866,8 @@ clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic -int_num=55 -pio_addr=268566528 +int_num=46 +pio_addr=471793664 pio_latency=10000 pixel_clock=41667 system=system @@ -1880,51 +1875,129 @@ vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] -[system.realview.dmac_fake] -type=AmbaFake -amba_id=0 +[system.realview.energy_ctrl] +type=EnergyCtrl clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler eventq_index=0 -ignore_access=false -pio_addr=268632064 +pio_addr=470286336 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[22] -[system.realview.energy_ctrl] -type=EnergyCtrl +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler +config_latency=20000 eventq_index=0 -pio_addr=268496896 -pio_latency=100000 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] pio=system.iobus.master[25] -[system.realview.flash_fake] -type=IsaFake -clk_domain=system.clk_domain +[system.realview.generic_timer] +type=GenericTimer eventq_index=0 -fake_mem=true -pio_addr=1073741824 -pio_latency=100000 -pio_size=536870912 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 +gic=system.realview.gic +int_num=29 system=system -update_data=false -warn_access= -pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain -cpu_addr=520093952 +cpu_addr=738205696 cpu_pio_delay=10000 -dist_addr=520097792 +dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 int_latency=10000 @@ -1934,38 +2007,111 @@ platform=system.realview system=system pio=system.membus.master[2] -[system.realview.gpio0_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268513280 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.gpio1_fake] -type=AmbaFake -amba_id=0 +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 clk_domain=system.clk_domain +enable_capture=true eventq_index=0 -ignore_access=false -pio_addr=268517376 -pio_latency=100000 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 system=system -pio=system.iobus.master[17] +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] -[system.realview.gpio2_fake] -type=AmbaFake -amba_id=0 +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 eventq_index=0 -ignore_access=false -pio_addr=268521472 -pio_latency=100000 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview system=system -pio=system.iobus.master[18] +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] [system.realview.kmi0] type=Pl050 @@ -1974,13 +2120,13 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=52 +int_num=44 is_mouse=false -pio_addr=268460032 +pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.kmi1] type=Pl050 @@ -1989,20 +2135,20 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=53 +int_num=45 is_mouse=true -pio_addr=268464128 +pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false -pio_addr=520101888 +pio_addr=739246080 pio_latency=100000 pio_size=4095 ret_bad_addr=false @@ -2013,7 +2159,25 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[3] +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer @@ -2022,10 +2186,10 @@ eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 -pio_addr=520095232 +pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[3] [system.realview.mmc_fake] type=AmbaFake @@ -2033,10 +2197,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268455936 +pio_addr=470089728 pio_latency=100000 system=system -pio=system.iobus.master[22] +pio=system.iobus.master[21] [system.realview.nvmem] type=SimpleMemory @@ -2048,18 +2212,30 @@ in_addr_map=true latency=30000 latency_var=0 null=false -range=2147483648:2214592511 +range=0:67108863 port=system.membus.master[1] +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 -idreg=0 -pio_addr=268435456 +idreg=35979264 +pio_addr=469827584 pio_latency=100000 -proc_id0=201326592 -proc_id1=201327138 +proc_id0=335544320 +proc_id1=335544320 system=system pio=system.iobus.master[1] @@ -2070,34 +2246,12 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=42 -pio_addr=268529664 +int_num=36 +pio_addr=471269376 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[23] - -[system.realview.sci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268492800 -pio_latency=100000 -system=system -pio=system.iobus.master[20] - -[system.realview.smc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=269357056 -pio_latency=100000 -system=system -pio=system.iobus.master[13] +pio=system.iobus.master[10] [system.realview.sp810_fake] type=AmbaFake @@ -2105,21 +2259,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true -pio_addr=268439552 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.ssp_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268488704 +pio_addr=469893120 pio_latency=100000 system=system -pio=system.iobus.master[19] +pio=system.iobus.master[16] [system.realview.timer0] type=Sp804 @@ -2129,9 +2272,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=36 -int_num1=36 -pio_addr=268505088 +int_num0=34 +int_num1=34 +pio_addr=470876160 pio_latency=100000 system=system pio=system.iobus.master[2] @@ -2144,9 +2287,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=37 -int_num1=37 -pio_addr=268509184 +int_num0=35 +int_num1=35 +pio_addr=470941696 pio_latency=100000 system=system pio=system.iobus.master[3] @@ -2158,8 +2301,8 @@ end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=44 -pio_addr=268472320 +int_num=37 +pio_addr=470351872 pio_latency=100000 platform=system.realview system=system @@ -2172,10 +2315,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268476416 +pio_addr=470417408 pio_latency=100000 system=system -pio=system.iobus.master[10] +pio=system.iobus.master[13] [system.realview.uart2_fake] type=AmbaFake @@ -2183,10 +2326,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268480512 +pio_addr=470482944 pio_latency=100000 system=system -pio=system.iobus.master[11] +pio=system.iobus.master[14] [system.realview.uart3_fake] type=AmbaFake @@ -2194,10 +2337,54 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268484608 +pio_addr=470548480 pio_latency=100000 system=system -pio=system.iobus.master[12] +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] [system.realview.watchdog_fake] type=AmbaFake @@ -2205,10 +2392,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268500992 +pio_addr=470745088 pio_latency=100000 system=system -pio=system.iobus.master[15] +pio=system.iobus.master[17] [system.terminal] type=Terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr index 9dee17aa2..99334c62c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr @@ -1,13 +1,44 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: LCD dual screen mode not supported +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR +warn: instruction 'mcr bpiall' unimplemented +warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout index a85df4ce3..f49caea0a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout @@ -1,17 +1,32 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 12:48:24 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:01:45 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu0.isa: ISA system set to: 0x15f94710 0x15f94710 - 0: system.cpu1.isa: ISA system set to: 0x15f94710 0x15f94710 -info: Using bootloader at address 0x80000000 -info: Using kernel entry physical address at 0x8000 +info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu0.isa: ISA system set to: 0x40cab00 0x40cab00 + 0: system.cpu1.isa: ISA system set to: 0x40cab00 0x40cab00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80008000 +info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1146870140500 because m5_exit instruction encountered +info: Read CNTFREQ_EL0 frequency +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +Exiting @ tick 2843718094000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 37ec7ce19..ffa50b552 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,163 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.658488 # Number of seconds simulated -sim_ticks 2658488068000 # Number of ticks simulated -final_tick 2658488068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.843718 # Number of seconds simulated +sim_ticks 2843718094000 # Number of ticks simulated +final_tick 2843718094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70694 # Simulator instruction rate (inst/s) -host_op_rate 85127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2981704600 # Simulator tick rate (ticks/s) -host_mem_usage 438480 # Number of bytes of host memory used -host_seconds 891.60 # Real time elapsed on the host -sim_insts 63030433 # Number of instructions simulated -sim_ops 75898814 # Number of ops (including micro ops) simulated +host_inst_rate 161241 # Simulator instruction rate (inst/s) +host_op_rate 195251 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3650642703 # Simulator tick rate (ticks/s) +host_mem_usage 606904 # Number of bytes of host memory used +host_seconds 778.96 # Real time elapsed on the host +sim_insts 125601128 # Number of instructions simulated +sim_ops 152093417 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 674300 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 5028416 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 10240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1341052 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10709120 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 495096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 5148352 # Number of bytes read from this memory -system.physmem.bytes_read::total 134030836 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 219456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 280832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4344000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7373136 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10595 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 78569 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 541088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1237760 # Number of bytes read from this memory +system.physmem.bytes_read::total 13841180 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 411264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 443200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7176832 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 9512912 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 21479 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 167330 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 80443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15512805 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 67875 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 825159 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46147806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 96 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 48 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 253640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 1891457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 186232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 1936571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50416189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82549 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 23087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 105636 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1634011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 6395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 1133026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2773432 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1634011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46147806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 96 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 48 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 1891457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1319258 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 1936571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53189621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15512805 # Number of read requests accepted -system.physmem.writeReqs 825159 # Number of write requests accepted -system.physmem.readBursts 15512805 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 825159 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992712960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 106560 # Total number of bytes read from write queue -system.physmem.bytesWritten 7389248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134030836 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7373136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1665 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709677 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 969393 # Per bank write bursts -system.physmem.perBankRdBursts::1 969270 # Per bank write bursts -system.physmem.perBankRdBursts::2 969024 # Per bank write bursts -system.physmem.perBankRdBursts::3 969581 # Per bank write bursts -system.physmem.perBankRdBursts::4 971912 # Per bank write bursts -system.physmem.perBankRdBursts::5 969565 # Per bank write bursts -system.physmem.perBankRdBursts::6 969152 # Per bank write bursts -system.physmem.perBankRdBursts::7 969036 # Per bank write bursts -system.physmem.perBankRdBursts::8 969555 # Per bank write bursts -system.physmem.perBankRdBursts::9 969606 # Per bank write bursts -system.physmem.perBankRdBursts::10 969469 # Per bank write bursts -system.physmem.perBankRdBursts::11 968910 # Per bank write bursts -system.physmem.perBankRdBursts::12 969137 # Per bank write bursts -system.physmem.perBankRdBursts::13 969414 # Per bank write bursts -system.physmem.perBankRdBursts::14 969294 # Per bank write bursts -system.physmem.perBankRdBursts::15 968822 # Per bank write bursts -system.physmem.perBankWrBursts::0 7303 # Per bank write bursts -system.physmem.perBankWrBursts::1 7359 # Per bank write bursts -system.physmem.perBankWrBursts::2 6981 # Per bank write bursts -system.physmem.perBankWrBursts::3 7260 # Per bank write bursts -system.physmem.perBankWrBursts::4 7486 # Per bank write bursts -system.physmem.perBankWrBursts::5 7442 # Per bank write bursts -system.physmem.perBankWrBursts::6 7374 # Per bank write bursts -system.physmem.perBankWrBursts::7 7195 # Per bank write bursts -system.physmem.perBankWrBursts::8 7413 # Per bank write bursts -system.physmem.perBankWrBursts::9 7378 # Per bank write bursts -system.physmem.perBankWrBursts::10 7327 # Per bank write bursts -system.physmem.perBankWrBursts::11 7067 # Per bank write bursts -system.physmem.perBankWrBursts::12 6951 # Per bank write bursts -system.physmem.perBankWrBursts::13 7051 # Per bank write bursts -system.physmem.perBankWrBursts::14 7072 # Per bank write bursts -system.physmem.perBankWrBursts::15 6798 # Per bank write bursts +system.physmem.num_reads::cpu1.inst 8478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 19340 # Number of read requests responded to by this memory +system.physmem.num_reads::total 216817 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 112138 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 152798 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 3601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 471584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3765887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 190275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 435261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4867283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 144622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155852 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2523749 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 815248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3345237 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2523749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 815586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 477810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3765887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 190289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 435261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8212520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 216817 # Number of read requests accepted +system.physmem.writeReqs 152798 # Number of write requests accepted +system.physmem.readBursts 216817 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 152798 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13860672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue +system.physmem.bytesWritten 9527424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 13841180 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9512912 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13461 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14081 # Per bank write bursts +system.physmem.perBankRdBursts::1 13907 # Per bank write bursts +system.physmem.perBankRdBursts::2 14464 # Per bank write bursts +system.physmem.perBankRdBursts::3 13988 # Per bank write bursts +system.physmem.perBankRdBursts::4 16210 # Per bank write bursts +system.physmem.perBankRdBursts::5 13087 # Per bank write bursts +system.physmem.perBankRdBursts::6 13697 # Per bank write bursts +system.physmem.perBankRdBursts::7 13930 # Per bank write bursts +system.physmem.perBankRdBursts::8 13098 # Per bank write bursts +system.physmem.perBankRdBursts::9 13410 # Per bank write bursts +system.physmem.perBankRdBursts::10 13015 # Per bank write bursts +system.physmem.perBankRdBursts::11 11706 # Per bank write bursts +system.physmem.perBankRdBursts::12 12947 # Per bank write bursts +system.physmem.perBankRdBursts::13 13659 # Per bank write bursts +system.physmem.perBankRdBursts::14 12722 # Per bank write bursts +system.physmem.perBankRdBursts::15 12652 # Per bank write bursts +system.physmem.perBankWrBursts::0 9756 # Per bank write bursts +system.physmem.perBankWrBursts::1 10039 # Per bank write bursts +system.physmem.perBankWrBursts::2 10215 # Per bank write bursts +system.physmem.perBankWrBursts::3 9785 # Per bank write bursts +system.physmem.perBankWrBursts::4 9214 # Per bank write bursts +system.physmem.perBankWrBursts::5 9161 # Per bank write bursts +system.physmem.perBankWrBursts::6 9492 # Per bank write bursts +system.physmem.perBankWrBursts::7 9434 # Per bank write bursts +system.physmem.perBankWrBursts::8 9026 # Per bank write bursts +system.physmem.perBankWrBursts::9 9356 # Per bank write bursts +system.physmem.perBankWrBursts::10 9095 # Per bank write bursts +system.physmem.perBankWrBursts::11 8550 # Per bank write bursts +system.physmem.perBankWrBursts::12 9129 # Per bank write bursts +system.physmem.perBankWrBursts::13 9225 # Per bank write bursts +system.physmem.perBankWrBursts::14 8893 # Per bank write bursts +system.physmem.perBankWrBursts::15 8496 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2658486560500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2843715756500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 59 # Read request sizes (log2) -system.physmem.readPktSize::3 15335449 # Read request sizes (log2) +system.physmem.readPktSize::2 559 # Read request sizes (log2) +system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 177297 # Read request sizes (log2) +system.physmem.readPktSize::6 216230 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 757284 # Write request sizes (log2) +system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 67875 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1046149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1019751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 986849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1098941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 993476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1059379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2733951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2632980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3427107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 133098 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 114256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 105608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 102115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148362 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17878 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 7470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see @@ -176,630 +179,633 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6904 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1037609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 963.852673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 885.641044 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 219.370096 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 32112 3.09% 3.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21277 2.05% 5.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9254 0.89% 6.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2543 0.25% 6.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3048 0.29% 6.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2181 0.21% 6.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8654 0.83% 7.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1069 0.10% 7.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 957471 92.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1037609 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6645 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2334.257336 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 73724.534105 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6636 99.86% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4.71859e+06-4.98074e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6645 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6645 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.375019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.329909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.281758 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2539 38.21% 38.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 27 0.41% 38.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3660 55.08% 93.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 195 2.93% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 85 1.28% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 57 0.86% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 40 0.60% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 11 0.17% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 9 0.14% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6645 # Writes before turning the bus around for reads -system.physmem.totQLat 404032545000 # Total ticks spent queuing -system.physmem.totMemAccLat 694866420000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77555700000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26047.89 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 253.241254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.538036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 308.020470 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46699 50.56% 50.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18860 20.42% 70.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6817 7.38% 78.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3583 3.88% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3053 3.31% 85.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2112 2.29% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1277 1.38% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1140 1.23% 90.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8814 9.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92355 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7471 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.988355 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 530.902810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7470 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7471 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7471 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.925847 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.607688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.837629 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6200 82.99% 82.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 464 6.21% 89.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 76 1.02% 90.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 210 2.81% 93.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 192 2.57% 95.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 15 0.20% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 27 0.36% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.20% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 29 0.39% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.13% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.12% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.08% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 2.18% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.07% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.05% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 14 0.19% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.04% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.11% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7471 # Writes before turning the bus around for reads +system.physmem.totQLat 7621074500 # Total ticks spent queuing +system.physmem.totMemAccLat 11681818250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1082865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35189.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44797.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53939.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.94 # Data bus utilization in percentage -system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.34 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 14503540 # Number of row buffer hits during reads -system.physmem.writeRowHits 85448 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.99 # Row buffer hit rate for writes -system.physmem.avgGap 162718.35 # Average gap between requests -system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2316452257000 # Time in different power states -system.physmem.memoryStateTime::REF 88772580000 # Time in different power states +system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing +system.physmem.readRowHits 183248 # Number of row buffer hits during reads +system.physmem.writeRowHits 89836 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 60.34 # Row buffer hit rate for writes +system.physmem.avgGap 7693723.89 # Average gap between requests +system.physmem.pageHitRate 74.72 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2710028687250 # Time in different power states +system.physmem.memoryStateTime::REF 94957980000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 253258119250 # Time in different power states +system.physmem.memoryStateTime::ACT 38731176500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3923753400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3920570640 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2140936875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2139200250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 60504077400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 60482814600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 378432000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 369729360 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 173639166480 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 173639166480 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 146077789680 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 145345956705 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1466951353500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1467593312250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1853615509335 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1853490750285 # Total energy per rank (pJ) -system.physmem.averagePower::0 697.245591 # Core power per rank (mW) -system.physmem.averagePower::1 697.198662 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 96 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 169 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 265 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 96 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 169 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 265 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16692376 # Transaction distribution -system.membus.trans_dist::ReadResp 16692376 # Transaction distribution -system.membus.trans_dist::WriteReq 768869 # Transaction distribution -system.membus.trans_dist::WriteResp 768869 # Transaction distribution -system.membus.trans_dist::Writeback 67875 # Transaction distribution -system.membus.trans_dist::UpgradeReq 55188 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 22300 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15674 # Transaction distribution -system.membus.trans_dist::ReadExReq 15293 # Transaction distribution -system.membus.trans_dist::ReadExResp 8420 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037240 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4436392 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35107240 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18720580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21143488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 143826880 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 68687 # Total snoops (count) -system.membus.snoop_fanout::samples 327086 # Request fanout histogram +system.physmem.actEnergy::0 365654520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 332549280 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 199513875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 181450500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 884239200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 805030200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 499582080 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 465069600 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 185737808880 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 185737808880 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 82126203345 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 81336736530 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1634190168750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1634882683500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1904003170650 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1903741328490 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.547151 # Core power per rank (mW) +system.physmem.averagePower::1 669.455073 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 1280 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 450 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 450 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 450 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 238282 # Transaction distribution +system.membus.trans_dist::ReadResp 238282 # Transaction distribution +system.membus.trans_dist::WriteReq 31054 # Transaction distribution +system.membus.trans_dist::WriteResp 31054 # Transaction distribution +system.membus.trans_dist::Writeback 112138 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 80328 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40430 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13461 # Transaction distribution +system.membus.trans_dist::ReadExReq 30145 # Transaction distribution +system.membus.trans_dist::ReadExResp 13182 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14040 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 705796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 827846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72718 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72718 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 900564 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1280 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21034796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21227006 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23546302 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 124500 # Total snoops (count) +system.membus.snoop_fanout::samples 499399 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 327086 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 499399 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 327086 # Request fanout histogram -system.membus.reqLayer0.occupancy 1769125500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 499399 # Request fanout histogram +system.membus.reqLayer0.occupancy 87896996 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11055000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12141500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1598500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17877285000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5004493562 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37922455685 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.4 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1620346498 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 2120331885 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38636884 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 92119 # number of replacements -system.l2c.tags.tagsinuse 55174.117162 # Cycle average of tags in use -system.l2c.tags.total_refs 396231 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 156723 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.528225 # Average number of references to valid blocks. +system.l2c.tags.replacements 151104 # number of replacements +system.l2c.tags.tagsinuse 64343.342453 # Cycle average of tags in use +system.l2c.tags.total_refs 537709 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 215892 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.490639 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 8029.027858 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.830738 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029129 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2503.920237 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29498.221526 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.298488 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2007.480710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13123.308478 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.122513 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.038207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.450107 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000127 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.030632 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200246 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.841890 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 53228 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 11362 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 13312.566907 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.661228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033237 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3627.484276 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 40388.691608 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.364745 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 878.502916 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6044.037536 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.203134 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001246 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.055351 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.616283 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000158 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.013405 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.092225 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.981801 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 46495 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 18259 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4763 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 48327 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1719 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 9346 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.812195 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.173370 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5120698 # Number of tag accesses -system.l2c.tags.data_accesses 5120698 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 193 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 42 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 14931 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88016 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 237 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 59 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 19686 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76288 # number of ReadReq hits -system.l2c.ReadReq_hits::total 199452 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 215010 # number of Writeback hits -system.l2c.Writeback_hits::total 215010 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 3051 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 2025 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5076 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 100 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 213 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 313 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 2211 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 2397 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4608 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 193 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 42 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 17142 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 88016 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 237 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 59 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 22083 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 76288 # number of demand (read+write) hits -system.l2c.demand_hits::total 204060 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 193 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 42 # number of overall hits -system.l2c.overall_hits::cpu0.inst 17142 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 88016 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 237 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 59 # number of overall hits -system.l2c.overall_hits::cpu1.inst 22083 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 76288 # number of overall hits -system.l2c.overall_hits::total 204060 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4222 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 78569 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1022::2 432 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6889 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 39173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 34 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2341 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 15618 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.709457 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000519 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.278610 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6702696 # Number of tag accesses +system.l2c.tags.data_accesses 6702696 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 575 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 122 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 36632 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 209337 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 45 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 12148 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 48809 # number of ReadReq hits +system.l2c.ReadReq_hits::total 307807 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 253703 # number of Writeback hits +system.l2c.Writeback_hits::total 253703 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 11935 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 1029 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 12964 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 208 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 174 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 382 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 3683 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 1200 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4883 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 575 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 122 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 40315 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 209337 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 139 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 45 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 13348 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 48809 # number of demand (read+write) hits +system.l2c.demand_hits::total 312690 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 575 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 122 # number of overall hits +system.l2c.overall_hits::cpu0.inst 40315 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 209337 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 139 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 45 # number of overall hits +system.l2c.overall_hits::cpu1.inst 13348 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 48809 # number of overall hits +system.l2c.overall_hits::total 312690 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 160 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 11021 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 167331 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3178 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 80451 # number of ReadReq misses -system.l2c.ReadReq_misses::total 166440 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 7948 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 5460 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13408 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 1046 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 1101 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2147 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 4019 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 4520 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 8539 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8241 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 78569 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.inst 2011 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 19340 # number of ReadReq misses +system.l2c.ReadReq_misses::total 199878 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 8877 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 2752 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11629 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 464 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 1248 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1712 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 6943 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 6359 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 13302 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 160 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17964 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 167331 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7698 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 80451 # number of demand (read+write) misses -system.l2c.demand_misses::total 174979 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8241 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 78569 # number of overall misses +system.l2c.demand_misses::cpu1.inst 8370 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 19340 # number of demand (read+write) misses +system.l2c.demand_misses::total 213180 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 160 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 17964 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 167331 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7698 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 80451 # number of overall misses -system.l2c.overall_misses::total 174979 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 256500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 326360000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1107250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 255357749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16477212323 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 13294932 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 6165736 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 19460668 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 621976 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 4504808 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 5126784 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 291276419 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 332394712 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 623671131 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 256500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 617636419 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1107250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 587752461 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17100883454 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 256500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 617636419 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1107250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 587752461 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17100883454 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 197 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 44 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 19153 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 166585 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 251 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 59 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 22864 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 156739 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 365892 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 215010 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 215010 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 10999 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 7485 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18484 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 1146 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 1314 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2460 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 6230 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 6917 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 13147 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 197 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 44 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 25383 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 166585 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 251 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 59 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 29781 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 156739 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 379039 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 197 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 44 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 25383 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 166585 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 251 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 59 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 29781 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 156739 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 379039 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.045455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.220435 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.138996 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.454888 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.722611 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.729459 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.725384 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.912740 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.837900 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.872764 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.645104 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.653462 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.649502 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.045455 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.324666 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.258487 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.461639 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.045455 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.324666 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.258487 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.461639 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 64125 # average ReadReq miss latency +system.l2c.overall_misses::cpu1.inst 8370 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 19340 # number of overall misses +system.l2c.overall_misses::total 213180 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 13245499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 927632991 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1117750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 171510999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 21228443106 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.inst 10247078 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.inst 3439358 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 13686436 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1071455 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1047955 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2119410 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.inst 585218901 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.inst 465754979 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1050973880 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 13245499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1512851892 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1117750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 637265978 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22279416986 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 13245499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1512851892 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1117750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 637265978 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22279416986 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 735 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 123 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 47653 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 376668 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 153 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 45 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 14159 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 68149 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 507685 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 253703 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 253703 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.inst 20812 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.inst 3781 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 24593 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.inst 672 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.inst 1422 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2094 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.inst 10626 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.inst 7559 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 18185 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 735 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 123 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 58279 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 376668 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 153 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 45 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 21718 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 68149 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 525870 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 735 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 123 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 58279 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 376668 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 153 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 45 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 21718 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 68149 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 525870 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008130 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.231276 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.142030 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.393705 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.426533 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.727850 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.472858 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.690476 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.877637 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.817574 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.inst 0.653397 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.inst 0.841249 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.731482 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.008130 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.308241 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.385395 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.405385 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.008130 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.308241 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.385395 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.405385 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77299.857887 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80351.714600 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 98997.911097 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1672.739305 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1129.255678 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1451.422136 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 594.623327 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 4091.560400 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2387.882627 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 72474.849216 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73538.653097 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73037.958894 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 64125 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84169.584520 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85286.424167 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 106207.001801 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1154.340205 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1249.766715 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1176.922865 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2309.170259 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 839.707532 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1237.973131 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84289.053867 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73243.431200 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 79008.711472 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 74946.780609 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76351.319953 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 97731.061750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 64125 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 84215.758851 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76136.914934 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 104509.883601 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 74946.780609 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76351.319953 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 97731.061750 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 255 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu0.inst 84215.758851 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76136.914934 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 104509.883601 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 27 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 6 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 42.500000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 67875 # number of writebacks -system.l2c.writebacks::total 67875 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 10 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 4222 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 112138 # number of writebacks +system.l2c.writebacks::total 112138 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 160 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 11020 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3176 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 166430 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 7948 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 5460 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 13408 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 1046 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1101 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2147 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 4019 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 4520 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 8539 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 8241 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 2011 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 199876 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.inst 8877 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2752 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11629 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 464 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1248 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1712 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.inst 6943 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.inst 6359 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 13302 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 160 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17963 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 7696 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 174969 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 8241 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 8370 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 213178 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 160 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17963 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 7696 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 174969 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 207500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 273765000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 936250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 215773749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 14418655831 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 80020888 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 54949416 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 134970304 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 10533533 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 11044096 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 21577629 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 240707081 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 275649788 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 516356869 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 207500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 514472081 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 936250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 491423537 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 14935012700 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 207500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 514472081 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 936250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 491423537 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 14935012700 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 12573700750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 155061349748 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167635050498 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1125597500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15721355858 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16846953358 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 13699298250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 170782705606 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184482003856 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.220435 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.138908 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.454861 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.722611 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.729459 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.725384 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.912740 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.837900 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.872764 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.645104 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.653462 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.649502 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.324666 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.258420 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.461612 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.324666 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.258420 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.461612 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average ReadReq mshr miss latency +system.l2c.overall_mshr_misses::cpu1.inst 8370 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 213178 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 790589241 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 946250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 146552499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 18767530106 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 89623803 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 27822731 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 117446534 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4677961 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12575743 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 17253704 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 498567599 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 385443021 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 884010620 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1289156840 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 946250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 531995520 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 19651540726 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1289156840 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 946250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 531995520 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 19651540726 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5455196250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 328328000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5783524250 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4031988000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 216852500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4248840500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9487184250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 545180500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10032364750 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.231255 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.142030 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.393701 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.426533 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.727850 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.472858 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.690476 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.877637 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.817574 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.653397 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.841249 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.731482 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.308224 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.385395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.405382 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.308224 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.385395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.405382 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64842.491710 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67938.837846 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 86634.956624 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10068.053347 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10063.995604 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.400955 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.299235 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10030.968211 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10050.129949 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 59892.281911 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60984.466372 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60470.414451 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71741.310436 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72875.434610 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 93895.865967 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10096.181480 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10110.003997 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10099.452575 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10081.812500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.717147 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.098131 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 71808.670459 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60613.779053 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 66456.970380 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -810,167 +816,194 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 1655552 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1655552 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 768869 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 768869 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 215010 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60145 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 22613 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 82758 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 22833 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 22833 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 801778 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302678 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5104456 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20000696 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23627528 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 43628224 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 170698 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 785697 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 675950 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 675935 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31054 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31054 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 253703 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 93172 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40812 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 133984 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 39254 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 39254 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1372089 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 383613 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1755702 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 42006746 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8315748 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 50322494 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 294957 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1100978 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.033136 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.178992 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 785697 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1064496 96.69% 96.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36482 3.31% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 785697 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2618065998 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1100978 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1599263913 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1234480729 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2606264414 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 16519582 # Transaction distribution -system.iobus.trans_dist::ReadResp 16519582 # Transaction distribution -system.iobus.trans_dist::WriteReq 8084 # Transaction distribution -system.iobus.trans_dist::WriteResp 8084 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8940 # Packet count per connected master and slave (bytes) +system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2370465695 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 831346703 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 31024 # Transaction distribution +system.iobus.trans_dist::ReadResp 31024 # Transaction distribution +system.iobus.trans_dist::WriteReq 59407 # Transaction distribution +system.iobus.trans_dist::WriteResp 59440 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384484 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33055332 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2392912 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 125076304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4476000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376400000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38686704315 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7252165 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5142285 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 425056 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4634449 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3350199 # Number of BTB hits +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326680325 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36847116 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 34854856 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17109626 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1616877 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20006820 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 14503231 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.289047 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 946301 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 66428 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.491435 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 10748202 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 771222 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -994,25 +1027,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6449087 # DTB read hits -system.cpu0.dtb.read_misses 22394 # DTB read misses -system.cpu0.dtb.write_hits 5803603 # DTB write hits -system.cpu0.dtb.write_misses 1784 # DTB write misses -system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1724 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1623 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch +system.cpu0.dtb.read_hits 23968692 # DTB read hits +system.cpu0.dtb.read_misses 61651 # DTB read misses +system.cpu0.dtb.write_hits 17871018 # DTB write hits +system.cpu0.dtb.write_misses 6619 # DTB write misses +system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 3502 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1211 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1921 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6471481 # DTB read accesses -system.cpu0.dtb.write_accesses 5805387 # DTB write accesses +system.cpu0.dtb.perms_faults 566 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24030343 # DTB read accesses +system.cpu0.dtb.write_accesses 17877637 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12252690 # DTB hits -system.cpu0.dtb.misses 24178 # DTB misses -system.cpu0.dtb.accesses 12276868 # DTB accesses +system.cpu0.dtb.hits 41839710 # DTB hits +system.cpu0.dtb.misses 68270 # DTB misses +system.cpu0.dtb.accesses 41907980 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1034,93 +1067,93 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 13302311 # ITB inst hits -system.cpu0.itb.inst_misses 3954 # ITB inst misses +system.cpu0.itb.inst_hits 70097291 # ITB inst hits +system.cpu0.itb.inst_misses 3844 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1195 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2220 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 3570 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7362 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 13306265 # ITB inst accesses -system.cpu0.itb.hits 13302311 # DTB hits -system.cpu0.itb.misses 3954 # DTB misses -system.cpu0.itb.accesses 13306265 # DTB accesses -system.cpu0.numCycles 86799146 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 70101135 # ITB inst accesses +system.cpu0.itb.hits 70097291 # DTB hits +system.cpu0.itb.misses 3844 # DTB misses +system.cpu0.itb.accesses 70101135 # DTB accesses +system.cpu0.numCycles 227722348 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29471412 # Number of instructions committed -system.cpu0.committedOps 35693999 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 1972340 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 41075 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5234564326 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.945198 # CPI: cycles per instruction -system.cpu0.ipc 0.339536 # IPC: instructions per cycle +system.cpu0.committedInsts 109201964 # Number of instructions committed +system.cpu0.committedOps 132004483 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8817575 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1858 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5459726684 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.085332 # CPI: cycles per instruction +system.cpu0.ipc 0.479540 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 47489 # number of quiesce instructions executed -system.cpu0.tickCycles 68192545 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 18606601 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 670908 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.780495 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 12627162 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 671420 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.806652 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6076833000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780495 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1864 # number of quiesce instructions executed +system.cpu0.tickCycles 192189087 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 35533261 # Total number of cycles that the object has spent stopped +system.cpu0.icache.tags.replacements 1960423 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.796865 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 68128653 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1960935 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.742943 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796865 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999603 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 27268595 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 27268595 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 12627162 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 12627162 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 12627162 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 12627162 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 12627162 # number of overall hits -system.cpu0.icache.overall_hits::total 12627162 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 671424 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 671424 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 671424 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 671424 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 671424 # number of overall misses -system.cpu0.icache.overall_misses::total 671424 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5600052378 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5600052378 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5600052378 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5600052378 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5600052378 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5600052378 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 13298586 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 13298586 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 13298586 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 13298586 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 13298586 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 13298586 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050488 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050488 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050488 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050488 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050488 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050488 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8340.560328 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8340.560328 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8340.560328 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8340.560328 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 142140155 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 142140155 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 68128653 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 68128653 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 68128653 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 68128653 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 68128653 # number of overall hits +system.cpu0.icache.overall_hits::total 68128653 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1960950 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1960950 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1960950 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1960950 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1960950 # number of overall misses +system.cpu0.icache.overall_misses::total 1960950 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16347715808 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 16347715808 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 16347715808 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 16347715808 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 16347715808 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 16347715808 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 70089603 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 70089603 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 70089603 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 70089603 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 70089603 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 70089603 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027978 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.027978 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027978 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.027978 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027978 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.027978 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8336.630617 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8336.630617 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8336.630617 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8336.630617 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8336.630617 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8336.630617 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1129,375 +1162,366 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 671424 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 671424 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 671424 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 671424 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 671424 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 671424 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4592017122 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4592017122 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4592017122 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4592017122 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4592017122 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4592017122 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 214843000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 214843000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 214843000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 214843000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050488 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050488 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050488 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6839.221002 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1960950 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1960950 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1960950 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1960950 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1960950 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1960950 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13404270692 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13404270692 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13404270692 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13404270692 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13404270692 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13404270692 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276968500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 276968500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027978 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027978 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027978 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6835.600445 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6835.600445 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6835.600445 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1296970 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1098887 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 10913 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 10913 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 275708 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 308200 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 48588 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23370 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 54742 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 144812 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 136646 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1347493 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1381165 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13298 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 66487 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 2808443 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43116416 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45547448 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21688 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119336 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 88804888 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 661783 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2010538 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.294459 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.455799 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2745512 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2644445 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28520 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28520 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 513053 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 701523 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 70947 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43092 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 94006 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 290299 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 280446 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3928023 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2381529 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11804 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166842 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6488198 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 125696704 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86351322 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17688 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 313268 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 212378982 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1094951 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4365889 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.223377 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.416509 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 1418517 70.55% 70.55% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 592021 29.45% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 3390648 77.66% 77.66% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 975241 22.34% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2010538 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1039622669 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 67426500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4365889 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2254798560 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 118870000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1011659878 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 704346240 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2947700808 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1230574902 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7877498 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7385992 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 36655495 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 88548223 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6510276 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 198706 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6081219 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2295 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17144913 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425558 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16187872 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8427 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2119 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 225934 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 452636 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6267 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 516786 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1326511 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 185629 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16039.205043 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1209112 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 201843 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.990359 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5120294500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4761.005363 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 22.831562 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.161164 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2118.524351 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9136.682602 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.290589 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001394 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000010 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.129304 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.557659 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.978955 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8350 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7848 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 57 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 864 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5964 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1431 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1438 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5471 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.509644 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.479004 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 22924468 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 22924468 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 29315 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5251 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 886043 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 920609 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 275708 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 275708 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 1811 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 1811 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 729 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 729 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 107812 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 107812 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 29315 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5251 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 993855 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1028421 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 29315 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5251 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 993855 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1028421 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 519 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 49158 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 49848 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 18945 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 18945 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 10134 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 10134 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 6 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 23532 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 23532 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 519 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 72690 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 73380 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 519 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 72690 # number of overall misses -system.cpu0.l2cache.overall_misses::total 73380 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11037500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3618999 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 1323798925 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1338455424 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 312100526 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 312100526 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 201024600 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 201024600 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 1393500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1393500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 857324396 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 857324396 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11037500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3618999 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2181123321 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 2195779820 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11037500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3618999 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2181123321 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 2195779820 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 29834 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5422 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 935201 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 970457 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 275708 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 275708 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 20756 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 20756 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 10863 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 10863 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 131344 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 131344 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 29834 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5422 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1066545 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1101801 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 29834 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5422 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1066545 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1101801 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031538 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.052564 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.051365 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.912748 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.912748 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.932891 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.932891 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.179163 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179163 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031538 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.068155 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.066600 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031538 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.068155 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.066600 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21163.736842 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26929.470788 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26850.734714 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 16474.031459 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 16474.031459 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19836.648905 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19836.648905 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 232250 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 232250 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 36432.279279 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 36432.279279 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21163.736842 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30005.823648 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 29923.409921 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21163.736842 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30005.823648 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 29923.409921 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked +system.cpu0.l2cache.tags.replacements 410501 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16214.104593 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2982888 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 426752 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.989746 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2824483316500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4342.913069 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.461328 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076713 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2208.018647 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9615.634836 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.265070 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002897 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134767 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.586892 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989630 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8959 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7283 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 66 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 107 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2957 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5162 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 667 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3107 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3633 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 224 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.546814 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.444519 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 54811525 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 54811525 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77296 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4241 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2365837 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 2447374 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 513053 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 513053 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4545 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 4545 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2277 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2277 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 221177 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 221177 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77296 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4241 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 2587014 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 2668551 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77296 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4241 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 2587014 # number of overall hits +system.cpu0.l2cache.overall_hits::total 2668551 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 1021 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 181 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94620 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 95822 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 28011 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 28011 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 18233 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18233 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46900 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 46900 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 1021 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 181 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 141520 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 142722 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 1021 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 181 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 141520 # number of overall misses +system.cpu0.l2cache.overall_misses::total 142722 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 34165499 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4027498 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2870753873 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 2908946870 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 500227988 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 500227988 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 361106760 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 361106760 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 90500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 90500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1915708255 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 1915708255 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 34165499 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4027498 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4786462128 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 4824655125 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 34165499 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4027498 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4786462128 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 4824655125 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78317 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4422 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2460457 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 2543196 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 513053 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 513053 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32556 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 32556 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20510 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20510 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 268077 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 268077 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78317 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4422 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 2728534 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2811273 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78317 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4422 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 2728534 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2811273 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040932 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.038456 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.037678 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.860394 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.860394 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.888981 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.888981 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.174950 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174950 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040932 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051867 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.050768 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040932 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051867 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.050768 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22251.370166 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30339.821105 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30357.818351 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17858.269537 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17858.269537 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19805.120386 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19805.120386 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 40846.657889 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 40846.657889 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22251.370166 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33821.807010 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 33804.564993 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22251.370166 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33821.807010 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 33804.564993 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 27297 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 390 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 24.300000 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 69.992308 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 114449 # number of writebacks -system.cpu0.l2cache.writebacks::total 114449 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2940 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 2940 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 800 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 800 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3740 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3740 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3740 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3740 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 519 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 171 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 46218 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 46908 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 225933 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 225933 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 18945 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 18945 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 10134 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10134 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 6 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 22732 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 22732 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 519 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 171 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 68950 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 69640 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 519 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 171 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 68950 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 225933 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 295573 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2421001 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 946752983 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 956578484 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8634543726 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8634543726 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 342474562 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 342474562 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 146006456 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 146006456 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1155500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1155500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 598541592 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 598541592 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2421001 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1545294575 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 1555120076 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2421001 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1545294575 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8634543726 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 10189663802 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14161707249 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14161707249 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1312859997 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1312859997 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15474567246 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15474567246 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.049420 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.048336 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.writebacks::writebacks 214261 # number of writebacks +system.cpu0.l2cache.writebacks::total 214261 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7719 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 7719 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3119 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 3119 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10838 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 10838 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10838 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 10838 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 1021 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 181 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86901 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 88103 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 516784 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 516784 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 28011 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 28011 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 18233 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18233 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43781 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 43781 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 1021 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 181 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 130682 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 131884 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 1021 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 181 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 130682 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 516784 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 648668 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2760498 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2099218995 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2128978496 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21179021871 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21179021871 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 474290503 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 474290503 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 241043533 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 241043533 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 69500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 69500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1189749710 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1189749710 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2760498 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3288968705 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 3318728206 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2760498 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3288968705 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21179021871 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 24497750077 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6107809749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6107809749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4518638513 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4518638513 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10626448262 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10626448262 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.035319 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034643 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.912748 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.912748 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.932891 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.932891 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.173072 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.173072 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.064648 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.063206 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.064648 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.860394 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.860394 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.888981 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.888981 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.163315 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163315 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047895 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046913 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047895 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.268264 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 20484.507832 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20392.651232 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 38217.275591 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 18077.305991 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18077.305991 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 14407.583975 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14407.583975 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 192583.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192583.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 26330.353335 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26330.353335 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22330.845434 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34474.271337 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230738 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24156.442331 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24164.653826 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40982.348275 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40982.348275 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16932.294563 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16932.294563 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13220.179510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13220.179510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27175.023640 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27175.023640 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25167.725509 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25163.994162 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25167.725509 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40982.348275 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37766.238009 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1505,99 +1529,98 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 362294 # number of replacements -system.cpu0.dcache.tags.tagsinuse 472.891448 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11414416 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 362806 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.461486 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 243086500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 472.891448 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.923616 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.923616 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 712097 # number of replacements +system.cpu0.dcache.tags.tagsinuse 497.191982 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 40404438 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 712609 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.699309 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 306793500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 497.191982 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.971078 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.971078 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 24357333 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 24357333 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 5805631 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5805631 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 5275579 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5275579 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 147422 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147422 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 146630 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 146630 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 11081210 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11081210 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 11081210 # number of overall hits -system.cpu0.dcache.overall_hits::total 11081210 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 308329 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 308329 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 276386 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 276386 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 10191 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 10191 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 10869 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10869 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 584715 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 584715 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 584715 # number of overall misses -system.cpu0.dcache.overall_misses::total 584715 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3680932639 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3680932639 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 4210104069 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4210104069 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 167480751 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 167480751 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 254581965 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 254581965 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 1495500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1495500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 7891036708 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 7891036708 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 7891036708 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7891036708 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113960 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6113960 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5551965 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5551965 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 157613 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157613 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 157499 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157499 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 11665925 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11665925 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 11665925 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11665925 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050430 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.050430 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.049782 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049782 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064658 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064658 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050122 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.050122 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050122 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.050122 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11938.327692 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11938.327692 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15232.696551 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15232.696551 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16434.182220 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16434.182220 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23422.758763 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23422.758763 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 83631959 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 83631959 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 22807107 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22807107 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 16791710 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16791710 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 380026 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 380026 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 361110 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361110 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 39598817 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 39598817 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 39598817 # number of overall hits +system.cpu0.dcache.overall_hits::total 39598817 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 535335 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 535335 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 529873 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 529873 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6515 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6515 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20510 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20510 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 1065208 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1065208 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 1065208 # number of overall misses +system.cpu0.dcache.overall_misses::total 1065208 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6583386279 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6583386279 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 7974270273 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7974270273 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 107544752 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 107544752 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 444281550 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 444281550 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 99500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 99500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 14557656552 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 14557656552 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 14557656552 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 14557656552 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23342442 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23342442 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17321583 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17321583 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 386541 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386541 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 381620 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381620 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 40664025 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 40664025 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 40664025 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 40664025 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.022934 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.022934 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030590 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030590 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016855 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016855 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.053745 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053745 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026195 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026195 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026195 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026195 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12297.694488 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12297.694488 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15049.399145 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15049.399145 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16507.252801 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16507.252801 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21661.704047 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21661.704047 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13495.526381 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13495.526381 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13495.526381 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13495.526381 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13666.491945 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13666.491945 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13666.491945 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13666.491945 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1606,76 +1629,74 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 275708 # number of writebacks -system.cpu0.dcache.writebacks::total 275708 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54553 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 54553 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124298 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 124298 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 74 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 178851 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 178851 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 178851 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 178851 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 253776 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 253776 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152088 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 152088 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10117 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10117 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10869 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 10869 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 405864 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 405864 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 405864 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 405864 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2514607539 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2514607539 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2141849701 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2141849701 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 146522249 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146522249 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231876035 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231876035 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1427500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1427500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4656457240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4656457240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4656457240 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4656457240 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14652229736 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14652229736 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394826498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394826498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16047056234 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16047056234 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041508 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041508 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027394 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027394 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064189 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064189 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034791 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034791 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034791 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.034791 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9908.768122 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9908.768122 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14082.963159 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14082.963159 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14482.776416 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14482.776416 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21333.704573 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21333.704573 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 513055 # number of writebacks +system.cpu0.dcache.writebacks::total 513055 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42339 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 42339 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 229244 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 229244 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 271583 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 271583 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 271583 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 271583 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 492996 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 492996 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 300629 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 300629 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6515 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6515 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20510 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20510 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 793625 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 793625 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 793625 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 793625 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5093716162 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5093716162 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4246170249 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4246170249 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 94499248 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94499248 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 402814450 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 402814450 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 93500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 93500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9339886411 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9339886411 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9339886411 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9339886411 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6120470998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6120470998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4732689487 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4732689487 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10853160485 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10853160485 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021120 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021120 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017356 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017356 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016855 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016855 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.053745 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053745 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019517 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.019517 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019517 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.019517 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10332.165295 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10332.165295 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14124.286908 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14124.286908 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14504.873062 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14504.873062 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19639.904924 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19639.904924 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11768.639359 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11768.639359 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11768.639359 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11768.639359 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1683,15 +1704,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7012649 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5102138 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 681212 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4956162 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3806104 # Number of BTB hits +system.cpu1.branchPred.lookups 4191050 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2447557 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 261619 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2683528 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1692147 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 76.795391 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 854817 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 71801 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 63.056804 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 827495 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 59633 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1715,25 +1736,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7899300 # DTB read hits -system.cpu1.dtb.read_misses 20789 # DTB read misses -system.cpu1.dtb.write_hits 6047693 # DTB write hits -system.cpu1.dtb.write_misses 2209 # DTB write misses -system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1917 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3619 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch +system.cpu1.dtb.read_hits 4177995 # DTB read hits +system.cpu1.dtb.read_misses 21525 # DTB read misses +system.cpu1.dtb.write_hits 3468676 # DTB write hits +system.cpu1.dtb.write_misses 1889 # DTB write misses +system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 2064 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 236 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 360 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 329 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7920089 # DTB read accesses -system.cpu1.dtb.write_accesses 6049902 # DTB write accesses +system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4199520 # DTB read accesses +system.cpu1.dtb.write_accesses 3470565 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13946993 # DTB hits -system.cpu1.dtb.misses 22998 # DTB misses -system.cpu1.dtb.accesses 13969991 # DTB accesses +system.cpu1.dtb.hits 7646671 # DTB hits +system.cpu1.dtb.misses 23414 # DTB misses +system.cpu1.dtb.accesses 7670085 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1755,91 +1776,92 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 14215184 # ITB inst hits -system.cpu1.itb.inst_misses 5010 # ITB inst misses +system.cpu1.itb.inst_hits 7954981 # ITB inst hits +system.cpu1.itb.inst_misses 2237 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1291 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 3360 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1936 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 14220194 # ITB inst accesses -system.cpu1.itb.hits 14215184 # DTB hits -system.cpu1.itb.misses 5010 # DTB misses -system.cpu1.itb.accesses 14220194 # DTB accesses -system.cpu1.numCycles 502294457 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7957218 # ITB inst accesses +system.cpu1.itb.hits 7954981 # DTB hits +system.cpu1.itb.misses 2237 # DTB misses +system.cpu1.itb.accesses 7957218 # DTB accesses +system.cpu1.numCycles 42108230 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 33559021 # Number of instructions committed -system.cpu1.committedOps 40204815 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 2028180 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 40425 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 4816571571 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 14.967494 # CPI: cycles per instruction -system.cpu1.ipc 0.066811 # IPC: instructions per cycle +system.cpu1.committedInsts 16399164 # Number of instructions committed +system.cpu1.committedOps 20088934 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1607897 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2744 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5644728223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.567706 # CPI: cycles per instruction +system.cpu1.ipc 0.389453 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 45433 # number of quiesce instructions executed -system.cpu1.tickCycles 438597056 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 63697401 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 777492 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.131548 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13433657 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 778004 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 17.266823 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 71929000500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.131548 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974866 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974866 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 2745 # number of quiesce instructions executed +system.cpu1.tickCycles 30601119 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 11507111 # Total number of cycles that the object has spent stopped +system.cpu1.icache.tags.replacements 921368 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.459165 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7030999 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 921880 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.626805 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 71222254500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459165 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 29201326 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 29201326 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13433657 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13433657 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13433657 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13433657 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13433657 # number of overall hits -system.cpu1.icache.overall_hits::total 13433657 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 778004 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 778004 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 778004 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 778004 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 778004 # number of overall misses -system.cpu1.icache.overall_misses::total 778004 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6472911750 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6472911750 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6472911750 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6472911750 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6472911750 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6472911750 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 14211661 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 14211661 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 14211661 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 14211661 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 14211661 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 14211661 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054744 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.054744 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054744 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.054744 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054744 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.054744 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8319.895206 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8319.895206 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8319.895206 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8319.895206 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 16827638 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 16827638 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 7030999 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7030999 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7030999 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7030999 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7030999 # number of overall hits +system.cpu1.icache.overall_hits::total 7030999 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 921880 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 921880 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 921880 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 921880 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 921880 # number of overall misses +system.cpu1.icache.overall_misses::total 921880 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7511609427 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7511609427 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7511609427 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7511609427 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7511609427 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7511609427 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7952879 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7952879 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7952879 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7952879 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7952879 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7952879 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115918 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.115918 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115918 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.115918 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115918 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.115918 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8148.142304 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8148.142304 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8148.142304 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8148.142304 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1848,370 +1870,362 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 778004 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 778004 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 778004 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 778004 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 778004 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 778004 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5304159248 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5304159248 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5304159248 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5304159248 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5304159248 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5304159248 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7302500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7302500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7302500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 7302500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054744 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.054744 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.054744 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6817.650357 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 921880 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 921880 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 921880 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 921880 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 921880 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 921880 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6126335573 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6126335573 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6126335573 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6126335573 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6126335573 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6126335573 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10451250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10451250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10451250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10451250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.115918 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.115918 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.115918 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6645.480510 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 2373135 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 2161912 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 757956 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 757956 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 242084 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 267987 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 52917 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23794 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 50912 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 145700 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 137856 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1555984 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4768118 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17545 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66434 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 6408081 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49785408 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44521800 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119152 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94456776 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 606235 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2002284 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.277104 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.447568 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1617912 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1172300 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2534 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2534 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 119069 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 160310 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 84990 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41555 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86189 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 79780 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67226 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1843990 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 788213 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6991 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 54848 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2694042 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59007680 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25579748 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10764 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 100400 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 84698592 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 851885 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2136582 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.360548 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.480160 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1447444 72.29% 72.29% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 554840 27.71% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1366242 63.95% 63.95% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 770340 36.05% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2002284 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2275579743 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 46369000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2136582 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 806533923 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80269000 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1168020751 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1384243177 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 2025918980 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9945491 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 391135835 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 4300499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 36649244 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 29750249 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6850018 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163294 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6486593 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2687 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7297386 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43768 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7137149 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1402 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2014 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 195430 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564382 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2677 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 112390 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 731398 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 179644 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15634.197458 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1195685 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 195044 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.130335 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 2581359096500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4491.320198 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 23.341759 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.933743 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.115946 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8353.485812 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.274128 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001425 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168708 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.509856 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.954236 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9491 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5898 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2061 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1580 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5850 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2269 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2711 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.579285 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359985 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 23405517 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 23405517 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29293 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7458 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 926354 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 963105 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 242084 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 242084 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1948 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1948 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1158 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1158 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112338 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 112338 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29293 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7458 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1038692 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1075443 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29293 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7458 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1038692 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1075443 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 495 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 146 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 61595 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 62236 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 18656 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 18656 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 12530 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 12530 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 23997 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 23997 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 495 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 146 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 85592 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 86233 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 495 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 146 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 85592 # number of overall misses -system.cpu1.l2cache.overall_misses::total 86233 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11596750 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3042000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1525132928 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1539771678 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 312251712 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 312251712 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 251269185 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 251269185 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 836500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 836500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1004785618 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1004785618 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 11596750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3042000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2529918546 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 2544557296 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 11596750 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3042000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2529918546 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 2544557296 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29788 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7604 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 987949 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 1025341 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 242084 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 242084 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 20604 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 20604 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 13688 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 13688 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 136335 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 136335 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29788 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7604 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1124284 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1161676 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29788 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7604 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1124284 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1161676 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019200 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.062346 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.060698 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.905455 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.905455 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.915400 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.915400 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.176015 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.176015 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.019200 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076130 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.074232 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.019200 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076130 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.074232 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20835.616438 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 24760.661223 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24740.852208 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 16737.334477 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16737.334477 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20053.406624 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20053.406624 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 278833.333333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 278833.333333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41871.301329 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41871.301329 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20835.616438 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29557.885620 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 29507.929633 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20835.616438 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29557.885620 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 29507.929633 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 1374 # number of cycles access was blocked +system.cpu1.l2cache.tags.replacements 85101 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15525.587179 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1172424 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 100275 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.692087 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5967.757550 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.503310 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.105046 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2342.307731 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7188.913541 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.364243 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001618 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142963 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.438776 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.947607 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10134 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5006 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 136 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6712 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3286 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2980 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1783 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.618530 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.305542 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 22015192 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 22015192 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 24492 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2447 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 1023306 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 1050245 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 119069 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 119069 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1895 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1895 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 736 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 736 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 30109 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 30109 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 24492 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2447 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 1053415 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 1080354 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 24492 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2447 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 1053415 # number of overall hits +system.cpu1.l2cache.overall_hits::total 1080354 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 608 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 244 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 73509 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 74361 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28314 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28314 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22589 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22589 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32639 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 32639 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 608 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 244 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 106148 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 107000 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 608 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 244 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 106148 # number of overall misses +system.cpu1.l2cache.overall_misses::total 107000 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13309748 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4879000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1671503870 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1689692618 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 534018919 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 534018919 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 443647551 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 443647551 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 303500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 303500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1129954380 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1129954380 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13309748 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4879000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2801458250 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 2819646998 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13309748 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4879000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2801458250 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 2819646998 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 25100 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2691 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1096815 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 1124606 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 119069 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 119069 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 30209 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 30209 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23325 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23325 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 62748 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 62748 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 25100 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2691 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 1159563 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1187354 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 25100 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2691 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 1159563 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1187354 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090673 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067020 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.066122 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.937270 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.937270 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.968446 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.968446 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.520160 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.520160 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090673 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.091541 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.090116 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090673 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.091541 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.090116 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19995.901639 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22738.764913 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22722.833448 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18860.596136 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18860.596136 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19639.981894 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19639.981894 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 34619.761022 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 34619.761022 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19995.901639 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26392.002204 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 26351.841103 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19995.901639 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26392.002204 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 26351.841103 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 5254 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 187 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24.981818 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28.096257 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 100561 # number of writebacks -system.cpu1.l2cache.writebacks::total 100561 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 3711 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 3711 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 1353 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 1353 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5064 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 5064 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5064 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 5064 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 495 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 146 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 57884 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 58525 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 195430 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 195430 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 18656 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 18656 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 12530 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 12530 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 22644 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 22644 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 495 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 146 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 80528 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 81169 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 495 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 146 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 80528 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 195430 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 276599 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2020000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1052949978 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1063101228 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10102217802 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10102217802 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 306954055 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 306954055 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 178539396 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 178539396 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 654500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 654500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 627825362 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 627825362 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2020000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1680775340 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 1690926590 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2020000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1680775340 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10102217802 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 11793144392 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 174927425750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174927425750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 28797119642 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28797119642 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 203724545392 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 203724545392 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.058590 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.057079 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 39442 # number of writebacks +system.cpu1.l2cache.writebacks::total 39442 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1735 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 1735 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 340 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 340 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2075 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 2075 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2075 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 2075 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 608 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 244 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 71774 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 72626 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 112390 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 112390 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28314 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28314 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22589 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22589 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 32299 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 32299 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 608 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 244 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 104073 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 104925 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 608 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 244 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 104073 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 112390 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 217315 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3171000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1134657222 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1146878474 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3172675528 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3172675528 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 408265220 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 408265220 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 310198725 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 310198725 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 254500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 254500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 858509328 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 858509328 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3171000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1993166550 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2005387802 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3171000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1993166550 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3172675528 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 5178063330 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 388960005 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 388960005 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 260468006 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 260468006 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 649428011 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 649428011 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.065439 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.064579 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.905455 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.905455 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.915400 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915400 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.166091 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.166091 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.071626 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.069872 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.071626 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.937270 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.937270 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.968446 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.968446 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.514742 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.514742 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.089752 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.088369 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.089752 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.238103 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18190.691348 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18164.907783 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51692.257084 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51692.257084 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16453.369157 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16453.369157 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 14248.954190 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14248.954190 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 218166.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 218166.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27725.903639 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27725.903639 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20832.172258 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51692.257084 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42636.251006 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183025 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15808.749993 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15791.568777 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28229.162096 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28229.162096 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14419.199689 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14419.199689 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13732.291159 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13732.291159 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 26580.059073 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26580.059073 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19151.620017 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19112.583293 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19151.620017 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28229.162096 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23827.454755 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2219,96 +2233,97 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 322748 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.331318 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11400815 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 323107 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.284952 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 72473667000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 491.331318 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.959631 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.959631 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 359 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24164293 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24164293 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 6375660 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6375660 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 4821255 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4821255 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 83384 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 83384 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 81522 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 81522 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 11196915 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11196915 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 11196915 # number of overall hits -system.cpu1.dcache.overall_hits::total 11196915 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 235192 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 235192 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 286280 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 286280 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 11913 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11913 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 13691 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 13691 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 521472 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 521472 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 521472 # number of overall misses -system.cpu1.dcache.overall_misses::total 521472 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3078984138 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3078984138 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 4572469338 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4572469338 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 214431997 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 214431997 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 314961410 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 314961410 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 915000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 915000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 7651453476 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7651453476 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 7651453476 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7651453476 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6610852 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6610852 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 5107535 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5107535 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 95297 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95297 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 95213 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95213 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 11718387 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11718387 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 11718387 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11718387 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.035577 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035577 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.056051 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.056051 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.125009 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125009 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.143793 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.143793 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044500 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044500 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044500 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044500 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 13091.364239 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13091.364239 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 15972.018087 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 15972.018087 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 17999.831864 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17999.831864 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23004.996713 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23004.996713 # average StoreCondReq miss latency +system.cpu1.dcache.tags.replacements 193696 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.979850 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7249545 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 194043 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.360508 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 107387908500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 469.979850 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.917929 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.917929 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 347 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 67 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.677734 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 15373685 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15373685 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.inst 3863317 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3863317 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.inst 3184030 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3184030 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 91016 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 91016 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 71184 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71184 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.inst 7047347 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 7047347 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 7047347 # number of overall hits +system.cpu1.dcache.overall_hits::total 7047347 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 184713 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 184713 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 145139 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 145139 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5273 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5273 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23325 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23325 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.inst 329852 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 329852 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.inst 329852 # number of overall misses +system.cpu1.dcache.overall_misses::total 329852 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2791622179 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2791622179 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3393821873 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3393821873 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 95816000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 95816000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 543674761 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 543674761 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 324500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 324500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 6185444052 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6185444052 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.inst 6185444052 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6185444052 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.inst 4048030 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4048030 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3329169 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3329169 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 96289 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96289 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 94509 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94509 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 7377199 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7377199 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 7377199 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7377199 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.045630 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045630 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043596 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.043596 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054762 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054762 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.246802 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246802 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044712 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044712 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044712 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044712 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15113.295648 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15113.295648 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23383.252420 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23383.252420 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18171.060118 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18171.060118 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23308.671426 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23308.671426 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14672.798302 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14672.798302 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14672.798302 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14672.798302 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18752.179923 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18752.179923 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18752.179923 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18752.179923 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2317,76 +2332,74 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 242084 # number of writebacks -system.cpu1.dcache.writebacks::total 242084 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36921 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 36921 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 129344 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 129344 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 46 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 166265 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 166265 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 166265 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 166265 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 198271 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 198271 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 156936 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 156936 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 11867 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11867 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 13691 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 13691 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 355207 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 355207 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 355207 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 355207 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2202163297 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202163297 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2284592028 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2284592028 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 190117000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 190117000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 286543590 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 286543590 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 863000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 863000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4486755325 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4486755325 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4486755325 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4486755325 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183747450747 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183747450747 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 34481854358 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34481854358 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 218229305105 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 218229305105 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.029992 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029992 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.030726 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030726 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.124526 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124526 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.143793 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.143793 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030312 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030312 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11106.835074 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11106.835074 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14557.475837 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14557.475837 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16020.645487 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16020.645487 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20929.339712 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20929.339712 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 119069 # number of writebacks +system.cpu1.dcache.writebacks::total 119069 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15047 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 15047 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 52186 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 52186 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 67233 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 67233 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 67233 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 67233 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 169666 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 169666 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 92953 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92953 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5273 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5273 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23325 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23325 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 262619 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 262619 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 262619 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 262619 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2247676267 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2247676267 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2022089921 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2022089921 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 85260000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85260000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 495802239 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 495802239 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 310500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 310500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4269766188 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4269766188 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4269766188 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4269766188 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 405245745 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 405245745 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 279561993 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 279561993 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 684807738 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 684807738 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.041913 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041913 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027921 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027921 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054762 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054762 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.246802 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246802 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.035599 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035599 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13247.652841 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13247.652841 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 21753.896281 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21753.896281 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16169.163664 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16169.163664 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21256.258907 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21256.258907 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2394,30 +2407,94 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.replacements 36445 # number of replacements +system.iocache.tags.tagsinuse 14.485749 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 268964842000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.485749 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.905359 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.905359 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328575 # Number of tag accesses +system.iocache.tags.data_accesses 328575 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31822377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31822377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31822377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31822377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31822377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31822377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 124793.635294 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124793.635294 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124793.635294 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124793.635294 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1759755743315 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1759755743315 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18561377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18561377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2257984064 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2257984064 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18561377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18561377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18561377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18561377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72789.713725 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72789.713725 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal Binary files differindex 04e1f4d41..89f9e916a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini index 240d456d3..28bc9e108 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini @@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain -atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename= +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 -flags_addr=268435504 -gic_cpu_addr=520093952 +flags_addr=469827632 +gic_cpu_addr=738205696 have_generic_timer=false have_large_asid_64=false have_lpae=false @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 -load_offset=0 -machine_type=RealView_PBX +load_offset=2147483648 +machine_type=VExpress_EMM mem_mode=timing -mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -53,14 +53,14 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[0] +system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=268435456:520093695 1073741824:1610612735 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -705,6 +705,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -771,7 +772,7 @@ tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.cpu.l2cache.tags] type=LRU @@ -825,15 +826,16 @@ type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 -use_default_range=false +use_default_range=true width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] type=BaseCache children=tags -addr_ranges=0:134217727 +addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain eventq_index=0 @@ -852,8 +854,8 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[26] -mem_side=system.membus.slave[2] +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] [system.iocache.tags] type=LRU @@ -876,8 +878,8 @@ system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -933,6 +935,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -942,7 +945,7 @@ mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive -range=0:134217727 +range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -971,46 +974,37 @@ tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 -port=system.membus.master[6] +port=system.membus.master[5] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=0 +pci_cfg_base=805306368 pci_cfg_gen_offsets=false pci_io_base=0 system=system -[system.realview.a9scu] -type=A9SCU -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=520093696 -pio_latency=100000 -system=system -pio=system.membus.master[4] - [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268451840 +pio_addr=470024192 pio_latency=100000 system=system -pio=system.iobus.master[21] +pio=system.iobus.master[18] [system.realview.cf_ctrl] type=IdeController -BAR0=402653184 +BAR0=471465984 BAR0LegacyIO=true -BAR0Size=16 -BAR1=402653440 +BAR0Size=256 +BAR1=471466240 BAR1LegacyIO=true -BAR1Size=1 +BAR1Size=4096 BAR2=1 BAR2LegacyIO=false BAR2Size=8 @@ -1080,18 +1074,18 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 -disks=system.cf0 +disks= eventq_index=0 -io_shift=1 +io_shift=2 pci_bus=2 -pci_dev=7 +pci_dev=0 pci_func=0 pio_latency=30000 platform=system.realview system=system -config=system.iobus.master[8] +config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.clcd] type=Pl111 @@ -1100,8 +1094,8 @@ clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic -int_num=55 -pio_addr=268566528 +int_num=46 +pio_addr=471793664 pio_latency=10000 pixel_clock=41667 system=system @@ -1109,51 +1103,129 @@ vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] -[system.realview.dmac_fake] -type=AmbaFake -amba_id=0 +[system.realview.energy_ctrl] +type=EnergyCtrl clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler eventq_index=0 -ignore_access=false -pio_addr=268632064 +pio_addr=470286336 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[22] -[system.realview.energy_ctrl] -type=EnergyCtrl +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler +config_latency=20000 eventq_index=0 -pio_addr=268496896 -pio_latency=100000 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] pio=system.iobus.master[25] -[system.realview.flash_fake] -type=IsaFake -clk_domain=system.clk_domain +[system.realview.generic_timer] +type=GenericTimer eventq_index=0 -fake_mem=true -pio_addr=1073741824 -pio_latency=100000 -pio_size=536870912 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 +gic=system.realview.gic +int_num=29 system=system -update_data=false -warn_access= -pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain -cpu_addr=520093952 +cpu_addr=738205696 cpu_pio_delay=10000 -dist_addr=520097792 +dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 int_latency=10000 @@ -1163,38 +1235,111 @@ platform=system.realview system=system pio=system.membus.master[2] -[system.realview.gpio0_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268513280 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.gpio1_fake] -type=AmbaFake -amba_id=0 +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 clk_domain=system.clk_domain +enable_capture=true eventq_index=0 -ignore_access=false -pio_addr=268517376 -pio_latency=100000 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 system=system -pio=system.iobus.master[17] +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] -[system.realview.gpio2_fake] -type=AmbaFake -amba_id=0 +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 eventq_index=0 -ignore_access=false -pio_addr=268521472 -pio_latency=100000 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview system=system -pio=system.iobus.master[18] +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] [system.realview.kmi0] type=Pl050 @@ -1203,13 +1348,13 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=52 +int_num=44 is_mouse=false -pio_addr=268460032 +pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.kmi1] type=Pl050 @@ -1218,20 +1363,20 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=53 +int_num=45 is_mouse=true -pio_addr=268464128 +pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false -pio_addr=520101888 +pio_addr=739246080 pio_latency=100000 pio_size=4095 ret_bad_addr=false @@ -1242,7 +1387,25 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[3] +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer @@ -1251,10 +1414,10 @@ eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 -pio_addr=520095232 +pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[3] [system.realview.mmc_fake] type=AmbaFake @@ -1262,10 +1425,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268455936 +pio_addr=470089728 pio_latency=100000 system=system -pio=system.iobus.master[22] +pio=system.iobus.master[21] [system.realview.nvmem] type=SimpleMemory @@ -1277,18 +1440,30 @@ in_addr_map=true latency=30000 latency_var=0 null=false -range=2147483648:2214592511 +range=0:67108863 port=system.membus.master[1] +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 -idreg=0 -pio_addr=268435456 +idreg=35979264 +pio_addr=469827584 pio_latency=100000 -proc_id0=201326592 -proc_id1=201327138 +proc_id0=335544320 +proc_id1=335544320 system=system pio=system.iobus.master[1] @@ -1299,34 +1474,12 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=42 -pio_addr=268529664 +int_num=36 +pio_addr=471269376 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[23] - -[system.realview.sci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268492800 -pio_latency=100000 -system=system -pio=system.iobus.master[20] - -[system.realview.smc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=269357056 -pio_latency=100000 -system=system -pio=system.iobus.master[13] +pio=system.iobus.master[10] [system.realview.sp810_fake] type=AmbaFake @@ -1334,21 +1487,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true -pio_addr=268439552 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.ssp_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268488704 +pio_addr=469893120 pio_latency=100000 system=system -pio=system.iobus.master[19] +pio=system.iobus.master[16] [system.realview.timer0] type=Sp804 @@ -1358,9 +1500,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=36 -int_num1=36 -pio_addr=268505088 +int_num0=34 +int_num1=34 +pio_addr=470876160 pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1373,9 +1515,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=37 -int_num1=37 -pio_addr=268509184 +int_num0=35 +int_num1=35 +pio_addr=470941696 pio_latency=100000 system=system pio=system.iobus.master[3] @@ -1387,8 +1529,8 @@ end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=44 -pio_addr=268472320 +int_num=37 +pio_addr=470351872 pio_latency=100000 platform=system.realview system=system @@ -1401,10 +1543,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268476416 +pio_addr=470417408 pio_latency=100000 system=system -pio=system.iobus.master[10] +pio=system.iobus.master[13] [system.realview.uart2_fake] type=AmbaFake @@ -1412,10 +1554,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268480512 +pio_addr=470482944 pio_latency=100000 system=system -pio=system.iobus.master[11] +pio=system.iobus.master[14] [system.realview.uart3_fake] type=AmbaFake @@ -1423,10 +1565,54 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268484608 +pio_addr=470548480 pio_latency=100000 system=system -pio=system.iobus.master[12] +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] [system.realview.watchdog_fake] type=AmbaFake @@ -1434,10 +1620,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268500992 +pio_addr=470745088 pio_latency=100000 system=system -pio=system.iobus.master[15] +pio=system.iobus.master[17] [system.terminal] type=Terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr index 9dee17aa2..99a5b93a6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr @@ -1,13 +1,38 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: LCD dual screen mode not supported +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: instruction 'mcr bpiall' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout index 7e5f71538..c0a4743fb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout @@ -1,16 +1,31 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 17:07:27 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:01:02 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu.isa: ISA system set to: 0x1a1f0030 0x1a1f0030 -info: Using bootloader at address 0x80000000 -info: Using kernel entry physical address at 0x8000 +info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu.isa: ISA system set to: 0x4defb00 0x4defb00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80008000 +info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2567809308500 because m5_exit instruction encountered +info: Read CNTFREQ_EL0 frequency +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +Exiting @ tick 2852200332000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 7ddeb2364..06709bcae 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,144 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.566404 # Number of seconds simulated -sim_ticks 2566404096500 # Number of ticks simulated -final_tick 2566404096500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852200 # Number of seconds simulated +sim_ticks 2852200332000 # Number of ticks simulated +final_tick 2852200332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75271 # Simulator instruction rate (inst/s) -host_op_rate 90613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3188038304 # Simulator tick rate (ticks/s) -host_mem_usage 412076 # Number of bytes of host memory used -host_seconds 805.01 # Real time elapsed on the host -sim_insts 60593541 # Number of instructions simulated -sim_ops 72944224 # Number of ops (including micro ops) simulated +host_inst_rate 169178 # Simulator instruction rate (inst/s) +host_op_rate 204545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4322499487 # Simulator tick rate (ticks/s) +host_mem_usage 558640 # Number of bytes of host memory used +host_seconds 659.85 # Real time elapsed on the host +sim_insts 111631963 # Number of instructions simulated +sim_ops 134968701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 256 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 256 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 4 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 4 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 100 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 100 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 100 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1664 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 6592 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10080024 # Number of bytes read from this memory -system.physmem.bytes_read::total 131192344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1001408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1001408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3810496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6826568 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 26 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 10875428 # Number of bytes read from this memory +system.physmem.bytes_read::total 10883108 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1665536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1665536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5669632 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory +system.physmem.bytes_written::total 8005492 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 103 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 157526 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15296370 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59539 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813557 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47190748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3927684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51119130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 390199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 390199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484761 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 1175213 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2659974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47190748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5102897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53779104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15296370 # Number of read requests accepted -system.physmem.writeReqs 813557 # Number of write requests accepted -system.physmem.readBursts 15296370 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813557 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978862336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 105344 # Total number of bytes read from write queue -system.physmem.bytesWritten 6837568 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131192344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6826568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1646 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706692 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4678 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955907 # Per bank write bursts -system.physmem.perBankRdBursts::1 955585 # Per bank write bursts -system.physmem.perBankRdBursts::2 955711 # Per bank write bursts -system.physmem.perBankRdBursts::3 955918 # Per bank write bursts -system.physmem.perBankRdBursts::4 957666 # Per bank write bursts -system.physmem.perBankRdBursts::5 955713 # Per bank write bursts -system.physmem.perBankRdBursts::6 955586 # Per bank write bursts -system.physmem.perBankRdBursts::7 955417 # Per bank write bursts -system.physmem.perBankRdBursts::8 956298 # Per bank write bursts -system.physmem.perBankRdBursts::9 955963 # Per bank write bursts -system.physmem.perBankRdBursts::10 955537 # Per bank write bursts -system.physmem.perBankRdBursts::11 955091 # Per bank write bursts -system.physmem.perBankRdBursts::12 956282 # Per bank write bursts -system.physmem.perBankRdBursts::13 955994 # Per bank write bursts -system.physmem.perBankRdBursts::14 956147 # Per bank write bursts -system.physmem.perBankRdBursts::15 955909 # Per bank write bursts -system.physmem.perBankWrBursts::0 6629 # Per bank write bursts -system.physmem.perBankWrBursts::1 6411 # Per bank write bursts -system.physmem.perBankWrBursts::2 6529 # Per bank write bursts -system.physmem.perBankWrBursts::3 6576 # Per bank write bursts -system.physmem.perBankWrBursts::4 6489 # Per bank write bursts -system.physmem.perBankWrBursts::5 6741 # Per bank write bursts -system.physmem.perBankWrBursts::6 6778 # Per bank write bursts -system.physmem.perBankWrBursts::7 6680 # Per bank write bursts -system.physmem.perBankWrBursts::8 7055 # Per bank write bursts -system.physmem.perBankWrBursts::9 6798 # Per bank write bursts -system.physmem.perBankWrBursts::10 6471 # Per bank write bursts -system.physmem.perBankWrBursts::11 6090 # Per bank write bursts -system.physmem.perBankWrBursts::12 7091 # Per bank write bursts -system.physmem.perBankWrBursts::13 6663 # Per bank write bursts -system.physmem.perBankWrBursts::14 6989 # Per bank write bursts -system.physmem.perBankWrBursts::15 6847 # Per bank write bursts +system.physmem.num_reads::cpu.inst 170448 # Number of read requests responded to by this memory +system.physmem.num_reads::total 170568 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 88588 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 129193 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 2311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3812996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3815688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 583948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 583948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1987810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 812824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.inst 6144 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2806778 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1987810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 813160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3819140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6622466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170568 # Number of read requests accepted +system.physmem.writeReqs 129193 # Number of write requests accepted +system.physmem.readBursts 170568 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129193 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10907008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 8019264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10883108 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8005492 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4599 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10529 # Per bank write bursts +system.physmem.perBankRdBursts::1 10427 # Per bank write bursts +system.physmem.perBankRdBursts::2 10726 # Per bank write bursts +system.physmem.perBankRdBursts::3 10519 # Per bank write bursts +system.physmem.perBankRdBursts::4 13519 # Per bank write bursts +system.physmem.perBankRdBursts::5 10191 # Per bank write bursts +system.physmem.perBankRdBursts::6 11164 # Per bank write bursts +system.physmem.perBankRdBursts::7 10885 # Per bank write bursts +system.physmem.perBankRdBursts::8 10359 # Per bank write bursts +system.physmem.perBankRdBursts::9 10882 # Per bank write bursts +system.physmem.perBankRdBursts::10 10112 # Per bank write bursts +system.physmem.perBankRdBursts::11 9441 # Per bank write bursts +system.physmem.perBankRdBursts::12 10326 # Per bank write bursts +system.physmem.perBankRdBursts::13 11222 # Per bank write bursts +system.physmem.perBankRdBursts::14 10031 # Per bank write bursts +system.physmem.perBankRdBursts::15 10089 # Per bank write bursts +system.physmem.perBankWrBursts::0 7745 # Per bank write bursts +system.physmem.perBankWrBursts::1 7827 # Per bank write bursts +system.physmem.perBankWrBursts::2 8372 # Per bank write bursts +system.physmem.perBankWrBursts::3 8091 # Per bank write bursts +system.physmem.perBankWrBursts::4 7875 # Per bank write bursts +system.physmem.perBankWrBursts::5 7401 # Per bank write bursts +system.physmem.perBankWrBursts::6 8203 # Per bank write bursts +system.physmem.perBankWrBursts::7 8042 # Per bank write bursts +system.physmem.perBankWrBursts::8 7896 # Per bank write bursts +system.physmem.perBankWrBursts::9 8173 # Per bank write bursts +system.physmem.perBankWrBursts::10 7527 # Per bank write bursts +system.physmem.perBankWrBursts::11 7251 # Per bank write bursts +system.physmem.perBankWrBursts::12 7760 # Per bank write bursts +system.physmem.perBankWrBursts::13 8405 # Per bank write bursts +system.physmem.perBankWrBursts::14 7350 # Per bank write bursts +system.physmem.perBankWrBursts::15 7383 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2566402308000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2852199845000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 18 # Read request sizes (log2) -system.physmem.readPktSize::3 15138826 # Read request sizes (log2) +system.physmem.readPktSize::2 541 # Read request sizes (log2) +system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157526 # Read request sizes (log2) +system.physmem.readPktSize::6 170013 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59539 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1111407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 958360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 963566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1076065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 974438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1039000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2689873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2594671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3384839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 130586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 112191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 103349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 100054 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124812 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6879 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -167,314 +158,370 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1014578 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.536840 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.616961 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 204.240777 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22129 2.18% 2.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22531 2.22% 4.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8793 0.87% 5.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2465 0.24% 5.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2547 0.25% 5.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1763 0.17% 5.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8722 0.86% 6.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 969 0.10% 6.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 944659 93.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1014578 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6201 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2466.490405 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 89690.748368 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6195 99.90% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6201 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6201 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.228995 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.200624 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.980358 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2397 38.66% 38.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 13 0.21% 38.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3771 60.81% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 16 0.26% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6201 # Writes before turning the bus around for reads -system.physmem.totQLat 395011426750 # Total ticks spent queuing -system.physmem.totMemAccLat 681787501750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76473620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25826.65 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60576 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.437401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.644234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.251922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22086 36.46% 36.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14485 23.91% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6694 11.05% 71.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3534 5.83% 77.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2501 4.13% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1624 2.68% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1087 1.79% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1062 1.75% 87.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7503 12.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60576 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6291 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.088221 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 577.877413 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6289 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6291 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6291 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.917501 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.380102 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.942111 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5514 87.65% 87.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 46 0.73% 88.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.49% 88.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 207 3.29% 92.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 183 2.91% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 14 0.22% 95.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.27% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 17 0.27% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 30 0.48% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.11% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.05% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 154 2.45% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.03% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.06% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 21 0.33% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 6 0.10% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.10% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6291 # Writes before turning the bus around for reads +system.physmem.totQLat 1680738000 # Total ticks spent queuing +system.physmem.totMemAccLat 4876150500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 852110000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9862.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44576.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.12 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28612.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.82 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.00 # Data bus utilization in percentage -system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.27 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing -system.physmem.readRowHits 14297539 # Number of row buffer hits during reads -system.physmem.writeRowHits 89444 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.70 # Row buffer hit rate for writes -system.physmem.avgGap 159305.64 # Average gap between requests -system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2209544766500 # Time in different power states -system.physmem.memoryStateTime::REF 85697820000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing +system.physmem.readRowHits 140727 # Number of row buffer hits during reads +system.physmem.writeRowHits 94419 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.34 # Row buffer hit rate for writes +system.physmem.avgGap 9514913.03 # Average gap between requests +system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2713226080000 # Time in different power states +system.physmem.memoryStateTime::REF 95241120000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 271160177250 # Time in different power states +system.physmem.memoryStateTime::ACT 43733042000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3833766720 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3836442960 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2091837000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2093297250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 59650523400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 59648323800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 342357840 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 349945920 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 167624935920 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 167624935920 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 149819559525 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 149631019200 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1408420983750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1408586370000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1791783964155 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1791770335050 # Total energy per rank (pJ) -system.physmem.averagePower::0 698.169437 # Core power per rank (mW) -system.physmem.averagePower::1 698.164127 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 16348869 # Transaction distribution -system.membus.trans_dist::ReadResp 16348869 # Transaction distribution -system.membus.trans_dist::WriteReq 763365 # Transaction distribution -system.membus.trans_dist::WriteResp 763365 # Transaction distribution -system.membus.trans_dist::Writeback 59539 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4678 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4678 # Transaction distribution -system.membus.trans_dist::ReadExReq 131592 # Transaction distribution -system.membus.trans_dist::ReadExResp 131592 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383066 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892039 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278915 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34556547 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390498 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19306742 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 140417270 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 219423 # Request fanout histogram +system.physmem.actEnergy::0 234125640 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 127747125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 686088000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 643195800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 411842880 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 400107600 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 186291630720 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 186291630720 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 82872817560 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 82165704345 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1638622788000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1639243062750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1909247039925 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1909089659010 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.395204 # Core power per rank (mW) +system.physmem.averagePower::1 669.340025 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 180 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 180 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 180 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 180 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 180 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 180 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 71824 # Transaction distribution +system.membus.trans_dist::ReadResp 71824 # Transaction distribution +system.membus.trans_dist::WriteReq 27607 # Transaction distribution +system.membus.trans_dist::WriteResp 27607 # Transaction distribution +system.membus.trans_dist::Writeback 88588 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4597 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4599 # Transaction distribution +system.membus.trans_dist::ReadExReq 129554 # Transaction distribution +system.membus.trans_dist::ReadExResp 129554 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 555288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 627985 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16569304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16733149 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19052445 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 219 # Total snoops (count) +system.membus.snoop_fanout::samples 296652 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 219423 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 296652 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 219423 # Request fanout histogram -system.membus.reqLayer0.occupancy 1783264500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 296652 # Request fanout histogram +system.membus.reqLayer0.occupancy 87220000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3414000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1713500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17618330500 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4827152764 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37437958000 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.5 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1383760500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1715299901 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38332500 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 16322171 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322171 # Transaction distribution -system.iobus.trans_dist::WriteReq 8178 # Transaction distribution -system.iobus.trans_dist::WriteResp 8178 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 524 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 30195 # Transaction distribution +system.iobus.trans_dist::ReadResp 30195 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383066 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660698 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2390498 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 123501026 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 524000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374888000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38185527000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36805500 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 12550628 # Number of BP lookups -system.cpu.branchPred.condPredicted 9093116 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1061685 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8575859 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6183324 # Number of BTB hits +system.cpu.branchPred.lookups 30761849 # Number of BP lookups +system.cpu.branchPred.condPredicted 16759561 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2494541 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18376022 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13249221 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.101512 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1560078 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 139853 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.100594 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7712174 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1491943 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -498,25 +545,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 13629467 # DTB read hits -system.cpu.dtb.read_misses 33605 # DTB read misses -system.cpu.dtb.write_hits 11376627 # DTB write hits -system.cpu.dtb.write_misses 3703 # DTB write misses -system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3447 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1539 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch +system.cpu.dtb.read_hits 24631139 # DTB read hits +system.cpu.dtb.read_misses 58263 # DTB read misses +system.cpu.dtb.write_hits 19400231 # DTB write hits +system.cpu.dtb.write_misses 6058 # DTB write misses +system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 4344 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1249 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 593 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 13663072 # DTB read accesses -system.cpu.dtb.write_accesses 11380330 # DTB write accesses +system.cpu.dtb.perms_faults 740 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24689402 # DTB read accesses +system.cpu.dtb.write_accesses 19406289 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 25006094 # DTB hits -system.cpu.dtb.misses 37308 # DTB misses -system.cpu.dtb.accesses 25043402 # DTB accesses +system.cpu.dtb.hits 44031370 # DTB hits +system.cpu.dtb.misses 64321 # DTB misses +system.cpu.dtb.accesses 44095691 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -538,94 +585,93 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 22908933 # ITB inst hits -system.cpu.itb.inst_misses 9079 # ITB inst misses +system.cpu.itb.inst_hits 57062578 # ITB inst hits +system.cpu.itb.inst_misses 5424 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2384 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 2982 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 5702 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8630 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 22918012 # ITB inst accesses -system.cpu.itb.hits 22908933 # DTB hits -system.cpu.itb.misses 9079 # DTB misses -system.cpu.itb.accesses 22918012 # DTB accesses -system.cpu.numCycles 572551547 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57068002 # ITB inst accesses +system.cpu.itb.hits 57062578 # DTB hits +system.cpu.itb.misses 5424 # DTB misses +system.cpu.itb.accesses 57068002 # DTB accesses +system.cpu.numCycles 313219225 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60593541 # Number of instructions committed -system.cpu.committedOps 72944224 # Number of ops (including micro ops) committed -system.cpu.discardedOps 3228444 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 77492 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 4562038068 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 9.449052 # CPI: cycles per instruction -system.cpu.ipc 0.105831 # IPC: instructions per cycle +system.cpu.committedInsts 111631963 # Number of instructions committed +system.cpu.committedOps 134968701 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7932752 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5391228164 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.805820 # CPI: cycles per instruction +system.cpu.ipc 0.356402 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 82978 # number of quiesce instructions executed -system.cpu.tickCycles 466653116 # Number of cycles that the object actually ticked -system.cpu.idleCycles 105898431 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 1529478 # number of replacements -system.cpu.icache.tags.tagsinuse 511.463685 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 21373010 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1529990 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.969379 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 9990881000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.463685 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998953 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998953 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed +system.cpu.tickCycles 224159041 # Number of cycles that the object actually ticked +system.cpu.idleCycles 89060184 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 2896816 # number of replacements +system.cpu.icache.tags.tagsinuse 511.427908 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54156207 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2897328 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.691776 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15213008250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.427908 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998883 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 24432991 # Number of tag accesses -system.cpu.icache.tags.data_accesses 24432991 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 21373010 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 21373010 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 21373010 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 21373010 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 21373010 # number of overall hits -system.cpu.icache.overall_hits::total 21373010 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1529991 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1529991 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1529991 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1529991 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1529991 # number of overall misses -system.cpu.icache.overall_misses::total 1529991 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20681368889 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20681368889 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20681368889 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20681368889 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20681368889 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20681368889 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22903001 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22903001 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22903001 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22903001 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22903001 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22903001 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066803 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.066803 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.066803 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.066803 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.066803 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.066803 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13517.314082 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13517.314082 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13517.314082 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13517.314082 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13517.314082 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13517.314082 # average overall miss latency +system.cpu.icache.tags.tag_accesses 59950884 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59950884 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54156207 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54156207 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54156207 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54156207 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54156207 # number of overall hits +system.cpu.icache.overall_hits::total 54156207 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2897339 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2897339 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2897339 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2897339 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2897339 # number of overall misses +system.cpu.icache.overall_misses::total 2897339 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39126605503 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39126605503 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39126605503 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39126605503 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39126605503 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39126605503 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57053546 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57053546 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57053546 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57053546 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57053546 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57053546 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050783 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050783 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050783 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050783 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050783 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050783 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.324314 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13504.324314 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.324314 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13504.324314 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.324314 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13504.324314 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -634,211 +680,225 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1529991 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1529991 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1529991 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1529991 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1529991 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1529991 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17615727111 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17615727111 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17615727111 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17615727111 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17615727111 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17615727111 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172140750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172140750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172140750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 172140750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066803 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.066803 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.066803 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11513.614859 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11513.614859 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11513.614859 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11513.614859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11513.614859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11513.614859 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897339 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2897339 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2897339 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2897339 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2897339 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2897339 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33322439497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33322439497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33322439497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33322439497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33322439497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33322439497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222173750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222173750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222173750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 222173750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050783 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050783 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050783 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11501.049583 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11501.049583 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11501.049583 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11501.049583 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11501.049583 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11501.049583 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3182062 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3182061 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 600919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2980 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2980 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247461 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247461 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3062730 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5773755 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 100548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8966005 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 97946560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84574454 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 165736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 182730554 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 26649 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2846983 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 3575425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3575329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 697864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2819 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2821 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295691 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5800652 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2504517 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15250 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 156288 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8476707 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185619904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98723549 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18892 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276412 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284638757 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 60515 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4573888 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.007972 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.088927 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2846983 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 4537427 99.20% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36461 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2846983 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3381152937 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4573888 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3011299661 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2301840639 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2547807667 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18027487 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 4355950753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1340010456 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 10527250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 59116998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 87188750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 65091 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51567.943403 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2406935 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 130479 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.446915 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2524835361000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36492.360835 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.402377 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15058.179616 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.556829 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000266 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 97184 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65075.712435 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4041226 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 162444 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.877656 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 93442219500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 47462.018914 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 55.401726 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009455 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 17558.282340 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.724213 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000845 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.229770 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.786864 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 15 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65373 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2561 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6578 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56121 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000229 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997513 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 22965227 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 22965227 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 41408 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10949 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1892934 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1945291 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 600919 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 600919 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.inst 25 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 25 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 114146 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 114146 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 41408 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10949 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 2007080 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2059437 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 41408 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10949 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 2007080 # number of overall hits -system.cpu.l2cache.overall_hits::total 2059437 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 26 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.267918 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992977 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65213 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2308 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6976 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55798 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995071 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 36570721 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 36570721 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69000 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4721 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 3405800 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3479521 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 697864 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 697864 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.inst 45 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 164314 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 164314 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 69000 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 4721 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 3570114 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3643835 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 69000 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 4721 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 3570114 # number of overall hits +system.cpu.l2cache.overall_hits::total 3643835 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 103 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 23655 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23683 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2955 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2955 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 133315 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133315 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 26 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 37510 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 37615 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2774 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2774 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 131377 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131377 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 103 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 156970 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156998 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 26 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 168887 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168992 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 103 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 156970 # number of overall misses -system.cpu.l2cache.overall_misses::total 156998 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2068000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1704040750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1706258250 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 348485 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9355155027 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9355155027 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2068000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11059195777 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11061413277 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2068000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11059195777 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11061413277 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 41434 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10951 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1916589 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1968974 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 600919 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 600919 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2980 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2980 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247461 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247461 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 41434 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 2164050 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2216435 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 41434 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2164050 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2216435 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000628 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000183 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012342 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.012028 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991611 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991611 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538731 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.538731 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000628 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000183 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072535 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.070834 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000628 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000183 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072535 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.070834 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79538.461538 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72037.233143 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72045.697336 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 117.930626 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 117.930626 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70173.311533 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70173.311533 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79538.461538 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70454.200019 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70455.759163 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79538.461538 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70454.200019 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70455.759163 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 168887 # number of overall misses +system.cpu.l2cache.overall_misses::total 168992 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 7796000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 163250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2760094000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2768053250 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 998957 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 998957 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 46498 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9221968427 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9221968427 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 7796000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 163250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11982062427 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11990021677 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 7796000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 163250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11982062427 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11990021677 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69103 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4723 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3443310 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 3517136 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 697864 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 697864 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2819 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2819 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295691 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 295691 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69103 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 4723 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 3739001 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 3812827 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69103 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 4723 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3739001 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 3812827 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001491 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000423 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010894 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.010695 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.984037 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984037 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.444305 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.444305 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001491 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000423 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045169 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.044322 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001491 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000423 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045169 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.044322 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 75689.320388 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81625 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73582.884564 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73589.080154 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 360.114275 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 360.114275 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23249 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70194.694863 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70194.694863 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 75689.320388 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81625 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70947.215754 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70950.232419 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 75689.320388 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81625 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70947.215754 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70950.232419 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -847,84 +907,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59539 # number of writebacks -system.cpu.l2cache.writebacks::total 59539 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 26 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 88588 # number of writebacks +system.cpu.l2cache.writebacks::total 88588 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 165 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 103 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23586 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23614 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2955 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2955 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133315 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133315 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 26 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37345 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37450 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2774 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2774 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131377 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131377 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 103 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 156901 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156929 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 26 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 168722 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168827 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 103 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 156901 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156929 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1746000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1404219250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1406090250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29553955 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29553955 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7656846473 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7656846473 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1746000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9061065723 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9062936723 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1746000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9061065723 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9062936723 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167363942750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167363942750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707802808 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707802808 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184071745558 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184071745558 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000628 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012306 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011993 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991611 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991611 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538731 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538731 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000628 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.070802 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000628 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.070802 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59536.133723 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59544.772169 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.338409 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.338409 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57434.245756 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57434.245756 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57750.210152 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57751.828680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57750.210152 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57751.828680 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 168722 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168827 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6531000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 138750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2281377500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2288047250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27781774 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27781774 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7543603073 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7543603073 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6531000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 138750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9824980573 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9831650323 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6531000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 138750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9824980573 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9831650323 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545609250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545609250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4106796000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4106796000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652405250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652405250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010846 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010648 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.984037 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984037 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.444305 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.444305 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045125 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044279 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045125 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044279 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 69375 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61089.235507 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61096.054740 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10015.059120 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.059120 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57419.510820 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57419.510820 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 69375 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58231.769259 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58235.059102 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 69375 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58231.769259 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58235.059102 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -932,86 +1000,94 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 635446 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.959259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21828831 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 635958 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.324328 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 227074250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999920 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999920 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 841153 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.953397 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42536757 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 841665 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.538821 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 279806250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953397 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 350 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 91723842 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 91723842 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 11595412 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11595412 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 9746012 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9746012 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236764 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236764 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 247613 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247613 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 21341424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21341424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 21341424 # number of overall hits -system.cpu.dcache.overall_hits::total 21341424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 458657 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 458657 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 476663 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 476663 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10850 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 10850 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.inst 935320 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 935320 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 935320 # number of overall misses -system.cpu.dcache.overall_misses::total 935320 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6947637684 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6947637684 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 22233411759 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22233411759 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 151795500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 151795500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 29181049443 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29181049443 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 29181049443 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29181049443 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 12054069 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12054069 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 10222675 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222675 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247614 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247614 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 247613 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247613 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 22276744 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22276744 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 22276744 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22276744 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.038050 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.038050 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046628 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046628 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.041986 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.041986 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.041986 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.041986 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15147.785129 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15147.785129 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46643.879972 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46643.879972 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13990.368664 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13990.368664 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31199.000816 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31199.000816 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31199.000816 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31199.000816 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 175509435 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 175509435 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 23374617 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23374617 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 18241170 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18241170 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457775 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457775 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 460281 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460281 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 41615787 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41615787 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 41615787 # number of overall hits +system.cpu.dcache.overall_hits::total 41615787 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 583566 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 583566 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 541192 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 541192 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8333 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8333 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.inst 1124758 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1124758 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1124758 # number of overall misses +system.cpu.dcache.overall_misses::total 1124758 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8637456588 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8637456588 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21531074313 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21531074313 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117993250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 117993250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 52502 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 52502 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 30168530901 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30168530901 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 30168530901 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30168530901 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 23958183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23958183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 18782362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18782362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466108 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466108 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460283 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460283 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 42740545 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42740545 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 42740545 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42740545 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024358 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.024358 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028814 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.028814 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017878 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017878 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.026316 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026316 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.026316 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026316 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14801.164886 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14801.164886 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39784.539152 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39784.539152 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14159.756390 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.756390 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26251 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26251 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26822.241674 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26822.241674 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26822.241674 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26822.241674 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1020,64 +1096,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 600919 # number of writebacks -system.cpu.dcache.writebacks::total 600919 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80937 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 80937 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 226224 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 226224 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 71 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 71 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 307161 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 307161 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 307161 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 307161 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377720 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 377720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250439 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250439 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10779 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 10779 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 628159 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 628159 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 628159 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 628159 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4824316311 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4824316311 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10814527330 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10814527330 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129220000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129220000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15638843641 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15638843641 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15638843641 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15638843641 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182633838500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182633838500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058035692 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058035692 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208691874192 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208691874192 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031335 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031335 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024498 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024498 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043531 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043531 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028198 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028198 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028198 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028198 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12772.202454 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12772.202454 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43182.281234 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43182.281234 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11988.125058 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11988.125058 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24896.313897 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24896.313897 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 697864 # number of writebacks +system.cpu.dcache.writebacks::total 697864 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45894 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45894 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242687 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 242687 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 288581 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 288581 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 288581 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 288581 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537672 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 537672 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298505 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298505 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8333 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8333 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 836177 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 836177 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 836177 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 836177 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6873353393 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6873353393 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11227746403 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11227746403 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101298750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101298750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18101099796 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18101099796 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18101099796 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18101099796 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5791247750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791247750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439329000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439329000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230576750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230576750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022442 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022442 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015893 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015893 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017878 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017878 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019564 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.019564 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019564 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019564 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12783.543486 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12783.543486 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37613.260759 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37613.260759 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12156.336253 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.336253 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24249 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24249 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21647.449997 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21647.449997 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21647.449997 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21647.449997 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -1085,30 +1167,90 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.replacements 36424 # number of replacements +system.iocache.tags.tagsinuse 1.031370 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 269945589000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.031370 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064461 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064461 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328122 # Number of tag accesses +system.iocache.tags.data_accesses 328122 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses +system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses +system.iocache.demand_misses::total 234 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 234 # number of overall misses +system.iocache.overall_misses::total 234 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 27970377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 27970377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 27970377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 27970377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 27970377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 27970377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 119531.525641 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119531.525641 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119531.525641 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119531.525641 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119531.525641 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119531.525641 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1737063641000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1737063641000 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 15801377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 15801377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2215530472 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2215530472 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 15801377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 15801377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 15801377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 15801377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67527.252137 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67527.252137 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67527.252137 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67527.252137 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67527.252137 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67527.252137 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal Binary files differindex 7aa71fcbc..b3be0ec54 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index a708031a0..c9ee24d0f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain -atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename= +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 -flags_addr=268435504 -gic_cpu_addr=520093952 +flags_addr=469827632 +gic_cpu_addr=738205696 have_generic_timer=false have_large_asid_64=false have_lpae=false @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 -load_offset=0 -machine_type=RealView_PBX +load_offset=2147483648 +machine_type=VExpress_EMM mem_mode=timing -mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +mem_ranges=2147483648:2415919103 +memories=system.physmem system.realview.vram system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -53,14 +53,14 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[0] +system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=268435456:520093695 1073741824:1610612735 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -308,6 +308,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.checker.istage2_mmu] @@ -762,6 +763,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -828,7 +830,7 @@ tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.cpu.l2cache.tags] type=LRU @@ -882,15 +884,16 @@ type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 -use_default_range=false +use_default_range=true width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] type=BaseCache children=tags -addr_ranges=0:134217727 +addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain eventq_index=0 @@ -909,8 +912,8 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[26] -mem_side=system.membus.slave[2] +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] [system.iocache.tags] type=LRU @@ -933,8 +936,8 @@ system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -990,6 +993,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -999,7 +1003,7 @@ mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive -range=0:134217727 +range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1028,46 +1032,37 @@ tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 -port=system.membus.master[6] +port=system.membus.master[5] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=0 +pci_cfg_base=805306368 pci_cfg_gen_offsets=false pci_io_base=0 system=system -[system.realview.a9scu] -type=A9SCU -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=520093696 -pio_latency=100000 -system=system -pio=system.membus.master[4] - [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268451840 +pio_addr=470024192 pio_latency=100000 system=system -pio=system.iobus.master[21] +pio=system.iobus.master[18] [system.realview.cf_ctrl] type=IdeController -BAR0=402653184 +BAR0=471465984 BAR0LegacyIO=true -BAR0Size=16 -BAR1=402653440 +BAR0Size=256 +BAR1=471466240 BAR1LegacyIO=true -BAR1Size=1 +BAR1Size=4096 BAR2=1 BAR2LegacyIO=false BAR2Size=8 @@ -1137,18 +1132,18 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 -disks=system.cf0 +disks= eventq_index=0 -io_shift=1 +io_shift=2 pci_bus=2 -pci_dev=7 +pci_dev=0 pci_func=0 pio_latency=30000 platform=system.realview system=system -config=system.iobus.master[8] +config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.clcd] type=Pl111 @@ -1157,8 +1152,8 @@ clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic -int_num=55 -pio_addr=268566528 +int_num=46 +pio_addr=471793664 pio_latency=10000 pixel_clock=41667 system=system @@ -1166,51 +1161,129 @@ vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] -[system.realview.dmac_fake] -type=AmbaFake -amba_id=0 +[system.realview.energy_ctrl] +type=EnergyCtrl clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler eventq_index=0 -ignore_access=false -pio_addr=268632064 +pio_addr=470286336 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[22] -[system.realview.energy_ctrl] -type=EnergyCtrl +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler +config_latency=20000 eventq_index=0 -pio_addr=268496896 -pio_latency=100000 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] pio=system.iobus.master[25] -[system.realview.flash_fake] -type=IsaFake -clk_domain=system.clk_domain +[system.realview.generic_timer] +type=GenericTimer eventq_index=0 -fake_mem=true -pio_addr=1073741824 -pio_latency=100000 -pio_size=536870912 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 +gic=system.realview.gic +int_num=29 system=system -update_data=false -warn_access= -pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain -cpu_addr=520093952 +cpu_addr=738205696 cpu_pio_delay=10000 -dist_addr=520097792 +dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 int_latency=10000 @@ -1220,38 +1293,111 @@ platform=system.realview system=system pio=system.membus.master[2] -[system.realview.gpio0_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268513280 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.gpio1_fake] -type=AmbaFake -amba_id=0 +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 clk_domain=system.clk_domain +enable_capture=true eventq_index=0 -ignore_access=false -pio_addr=268517376 -pio_latency=100000 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 system=system -pio=system.iobus.master[17] +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] -[system.realview.gpio2_fake] -type=AmbaFake -amba_id=0 +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 eventq_index=0 -ignore_access=false -pio_addr=268521472 -pio_latency=100000 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview system=system -pio=system.iobus.master[18] +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] [system.realview.kmi0] type=Pl050 @@ -1260,13 +1406,13 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=52 +int_num=44 is_mouse=false -pio_addr=268460032 +pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.kmi1] type=Pl050 @@ -1275,20 +1421,20 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=53 +int_num=45 is_mouse=true -pio_addr=268464128 +pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false -pio_addr=520101888 +pio_addr=739246080 pio_latency=100000 pio_size=4095 ret_bad_addr=false @@ -1299,7 +1445,25 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[3] +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer @@ -1308,10 +1472,10 @@ eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 -pio_addr=520095232 +pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[3] [system.realview.mmc_fake] type=AmbaFake @@ -1319,10 +1483,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268455936 +pio_addr=470089728 pio_latency=100000 system=system -pio=system.iobus.master[22] +pio=system.iobus.master[21] [system.realview.nvmem] type=SimpleMemory @@ -1334,18 +1498,30 @@ in_addr_map=true latency=30000 latency_var=0 null=false -range=2147483648:2214592511 +range=0:67108863 port=system.membus.master[1] +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 -idreg=0 -pio_addr=268435456 +idreg=35979264 +pio_addr=469827584 pio_latency=100000 -proc_id0=201326592 -proc_id1=201327138 +proc_id0=335544320 +proc_id1=335544320 system=system pio=system.iobus.master[1] @@ -1356,34 +1532,12 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=42 -pio_addr=268529664 +int_num=36 +pio_addr=471269376 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[23] - -[system.realview.sci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268492800 -pio_latency=100000 -system=system -pio=system.iobus.master[20] - -[system.realview.smc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=269357056 -pio_latency=100000 -system=system -pio=system.iobus.master[13] +pio=system.iobus.master[10] [system.realview.sp810_fake] type=AmbaFake @@ -1391,21 +1545,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true -pio_addr=268439552 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.ssp_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268488704 +pio_addr=469893120 pio_latency=100000 system=system -pio=system.iobus.master[19] +pio=system.iobus.master[16] [system.realview.timer0] type=Sp804 @@ -1415,9 +1558,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=36 -int_num1=36 -pio_addr=268505088 +int_num0=34 +int_num1=34 +pio_addr=470876160 pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1430,9 +1573,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=37 -int_num1=37 -pio_addr=268509184 +int_num0=35 +int_num1=35 +pio_addr=470941696 pio_latency=100000 system=system pio=system.iobus.master[3] @@ -1444,8 +1587,8 @@ end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=44 -pio_addr=268472320 +int_num=37 +pio_addr=470351872 pio_latency=100000 platform=system.realview system=system @@ -1458,10 +1601,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268476416 +pio_addr=470417408 pio_latency=100000 system=system -pio=system.iobus.master[10] +pio=system.iobus.master[13] [system.realview.uart2_fake] type=AmbaFake @@ -1469,10 +1612,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268480512 +pio_addr=470482944 pio_latency=100000 system=system -pio=system.iobus.master[11] +pio=system.iobus.master[14] [system.realview.uart3_fake] type=AmbaFake @@ -1480,10 +1623,54 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268484608 +pio_addr=470548480 pio_latency=100000 system=system -pio=system.iobus.master[12] +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] [system.realview.watchdog_fake] type=AmbaFake @@ -1491,10 +1678,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268500992 +pio_addr=470745088 pio_latency=100000 system=system -pio=system.iobus.master[15] +pio=system.iobus.master[17] [system.terminal] type=Terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index ec581702f..d913c3f34 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -1,30 +1,49 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: 6127336500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 6135886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 6171724500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6187045500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6729690500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 -warn: LCD dual screen mode not supported -warn: 51815926000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: 2464496392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 -warn: 2490035144500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2491240940500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2491596722500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 -warn: 2505538162500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 -warn: 2507237495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 -warn: 2512436106000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2512950831500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2518637805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2519704735000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2519705958000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: 8445832500: Instruction results do not match! (Values may not actually be integers) Inst: 0xa, checker: 0 +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] +warn: 81667444500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000 +warn: Returning zero for read from miscreg pmcr +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: Ignoring write to miscreg pmcr +warn: CP14 unimplemented crn[12], opc1[5], crm[8], opc2[0] +warn: 404836653500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000 +warn: instruction 'mcr bpiall' unimplemented +warn: instruction 'mcr dcisw' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 964505e0a..c5b41115c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,15 +1,47 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:22:42 -gem5 started Jun 21 2014 21:27:42 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:12:13 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu.checker.isa: ISA system set to: 0x639d990 0x639d990 - 0: system.cpu.isa: ISA system set to: 0x639d990 0x639d990 -info: Using bootloader at address 0x80000000 -info: Using kernel entry physical address at 0x8000 +info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu.checker.isa: ISA system set to: 0x59c2b00 0x59c2b00 + 0: system.cpu.isa: ISA system set to: 0x59c2b00 0x59c2b00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80008000 +info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2525888859000 because m5_exit instruction encountered +info: Read CNTFREQ_EL0 frequency +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +Exiting @ tick 2826845674500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 40f0cc994..2f04b9368 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,137 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542157 # Number of seconds simulated -sim_ticks 2542156879500 # Number of ticks simulated -final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826846 # Number of seconds simulated +sim_ticks 2826845674500 # Number of ticks simulated +final_tick 2826845674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45837 # Simulator instruction rate (inst/s) -host_op_rate 55223 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1932040285 # Simulator tick rate (ticks/s) -host_mem_usage 415140 # Number of bytes of host memory used -host_seconds 1315.79 # Real time elapsed on the host -sim_insts 60311972 # Number of instructions simulated -sim_ops 72661518 # Number of ops (including micro ops) simulated +host_inst_rate 73722 # Simulator instruction rate (inst/s) +host_op_rate 89421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1841455705 # Simulator tick rate (ticks/s) +host_mem_usage 559660 # Number of bytes of host memory used +host_seconds 1535.11 # Real time elapsed on the host +sim_insts 113172343 # Number of instructions simulated +sim_ops 137271263 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory -system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15295608 # Number of read requests accepted -system.physmem.writeReqs 812506 # Number of write requests accepted -system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue -system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955787 # Per bank write bursts -system.physmem.perBankRdBursts::1 955478 # Per bank write bursts -system.physmem.perBankRdBursts::2 953511 # Per bank write bursts -system.physmem.perBankRdBursts::3 951566 # Per bank write bursts -system.physmem.perBankRdBursts::4 958612 # Per bank write bursts -system.physmem.perBankRdBursts::5 955530 # Per bank write bursts -system.physmem.perBankRdBursts::6 953056 # Per bank write bursts -system.physmem.perBankRdBursts::7 951020 # Per bank write bursts -system.physmem.perBankRdBursts::8 956158 # Per bank write bursts -system.physmem.perBankRdBursts::9 955874 # Per bank write bursts -system.physmem.perBankRdBursts::10 952686 # Per bank write bursts -system.physmem.perBankRdBursts::11 950200 # Per bank write bursts -system.physmem.perBankRdBursts::12 956166 # Per bank write bursts -system.physmem.perBankRdBursts::13 955918 # Per bank write bursts -system.physmem.perBankRdBursts::14 953812 # Per bank write bursts -system.physmem.perBankRdBursts::15 951254 # Per bank write bursts -system.physmem.perBankWrBursts::0 6556 # Per bank write bursts -system.physmem.perBankWrBursts::1 6344 # Per bank write bursts -system.physmem.perBankWrBursts::2 6481 # Per bank write bursts -system.physmem.perBankWrBursts::3 6512 # Per bank write bursts -system.physmem.perBankWrBursts::4 6422 # Per bank write bursts -system.physmem.perBankWrBursts::5 6709 # Per bank write bursts -system.physmem.perBankWrBursts::6 6691 # Per bank write bursts -system.physmem.perBankWrBursts::7 6631 # Per bank write bursts -system.physmem.perBankWrBursts::8 6968 # Per bank write bursts -system.physmem.perBankWrBursts::9 6764 # Per bank write bursts -system.physmem.perBankWrBursts::10 6424 # Per bank write bursts -system.physmem.perBankWrBursts::11 6068 # Per bank write bursts -system.physmem.perBankWrBursts::12 7033 # Per bank write bursts -system.physmem.perBankWrBursts::13 6638 # Per bank write bursts -system.physmem.perBankWrBursts::14 6915 # Per bank write bursts -system.physmem.perBankWrBursts::15 6799 # Per bank write bursts +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1324880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9515236 # Number of bytes read from this memory +system.physmem.bytes_read::total 10842740 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1324880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1324880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5801024 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory +system.physmem.bytes_written::total 8136884 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22946 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 149195 # Number of read requests responded to by this memory +system.physmem.num_reads::total 172182 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 90641 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 131246 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3366026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3835632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2052119 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2878432 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2052119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3372225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6714064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 172183 # Number of read requests accepted +system.physmem.writeReqs 131246 # Number of write requests accepted +system.physmem.readBursts 172183 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 131246 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11011008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 8150720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10842804 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8136884 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10992 # Per bank write bursts +system.physmem.perBankRdBursts::1 10130 # Per bank write bursts +system.physmem.perBankRdBursts::2 11200 # Per bank write bursts +system.physmem.perBankRdBursts::3 11425 # Per bank write bursts +system.physmem.perBankRdBursts::4 13122 # Per bank write bursts +system.physmem.perBankRdBursts::5 10553 # Per bank write bursts +system.physmem.perBankRdBursts::6 11175 # Per bank write bursts +system.physmem.perBankRdBursts::7 11538 # Per bank write bursts +system.physmem.perBankRdBursts::8 10354 # Per bank write bursts +system.physmem.perBankRdBursts::9 11059 # Per bank write bursts +system.physmem.perBankRdBursts::10 10499 # Per bank write bursts +system.physmem.perBankRdBursts::11 9259 # Per bank write bursts +system.physmem.perBankRdBursts::12 10183 # Per bank write bursts +system.physmem.perBankRdBursts::13 10761 # Per bank write bursts +system.physmem.perBankRdBursts::14 10049 # Per bank write bursts +system.physmem.perBankRdBursts::15 9748 # Per bank write bursts +system.physmem.perBankWrBursts::0 8312 # Per bank write bursts +system.physmem.perBankWrBursts::1 7765 # Per bank write bursts +system.physmem.perBankWrBursts::2 8704 # Per bank write bursts +system.physmem.perBankWrBursts::3 8608 # Per bank write bursts +system.physmem.perBankWrBursts::4 7611 # Per bank write bursts +system.physmem.perBankWrBursts::5 7956 # Per bank write bursts +system.physmem.perBankWrBursts::6 8259 # Per bank write bursts +system.physmem.perBankWrBursts::7 8579 # Per bank write bursts +system.physmem.perBankWrBursts::8 7842 # Per bank write bursts +system.physmem.perBankWrBursts::9 8532 # Per bank write bursts +system.physmem.perBankWrBursts::10 7844 # Per bank write bursts +system.physmem.perBankWrBursts::11 6872 # Per bank write bursts +system.physmem.perBankWrBursts::12 7611 # Per bank write bursts +system.physmem.perBankWrBursts::13 8198 # Per bank write bursts +system.physmem.perBankWrBursts::14 7543 # Per bank write bursts +system.physmem.perBankWrBursts::15 7119 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2542155562500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 2826845408500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 18 # Read request sizes (log2) -system.physmem.readPktSize::3 15138826 # Read request sizes (log2) -system.physmem.readPktSize::4 3351 # Read request sizes (log2) +system.physmem.readPktSize::2 541 # Read request sizes (log2) +system.physmem.readPktSize::3 14 # Read request sizes (log2) +system.physmem.readPktSize::4 2993 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153413 # Read request sizes (log2) +system.physmem.readPktSize::6 168635 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 58488 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1110331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 964948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 965784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1077100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 974799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1038209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2680927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2586042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3366057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 129275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 112161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 103418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 99187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 19008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126865 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,331 +162,368 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads -system.physmem.totQLat 395458190750 # Total ticks spent queuing -system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62171 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 308.209036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.794963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.700925 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23473 37.76% 37.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14721 23.68% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6339 10.20% 71.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3681 5.92% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2625 4.22% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1528 2.46% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1121 1.80% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1145 1.84% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7538 12.12% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62171 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.780822 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.317098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.824875 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.368849 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.569917 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5609 87.31% 87.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 57 0.89% 88.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 29 0.45% 88.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 222 3.46% 92.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 216 3.36% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 23 0.36% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 19 0.30% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.19% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.22% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.06% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 154 2.40% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 11 0.17% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.16% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads +system.physmem.totQLat 2068507750 # Total ticks spent queuing +system.physmem.totMemAccLat 5294389000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 860235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12022.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30772.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.02 # Data bus utilization in percentage -system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing -system.physmem.readRowHits 14271218 # Number of row buffer hits during reads -system.physmem.writeRowHits 90719 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes -system.physmem.avgGap 157818.32 # Average gap between requests -system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states -system.physmem.memoryStateTime::REF 84888180000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.06 # Average write queue length when enqueuing +system.physmem.readRowHits 142034 # Number of row buffer hits during reads +system.physmem.writeRowHits 95196 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.74 # Row buffer hit rate for writes +system.physmem.avgGap 9316332.35 # Average gap between requests +system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2694724296750 # Time in different power states +system.physmem.memoryStateTime::REF 94394560000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states +system.physmem.memoryStateTime::ACT 37726803750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3819501000 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3820982760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2084053125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2084861625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 59549568000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 59530130400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 339202080 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 347386320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 166041280080 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 166041280080 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 145728636750 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 145839613185 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1397461683000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1397364335250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1775023924035 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1775028589620 # Total energy per rank (pJ) -system.physmem.averagePower::0 698.235540 # Core power per rank (mW) -system.physmem.averagePower::1 698.237375 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16348037 # Transaction distribution -system.membus.trans_dist::ReadResp 16348037 # Transaction distribution -system.membus.trans_dist::WriteReq 763357 # Transaction distribution -system.membus.trans_dist::WriteResp 763357 # Transaction distribution -system.membus.trans_dist::Writeback 58488 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution -system.membus.trans_dist::ReadExReq 131654 # Transaction distribution -system.membus.trans_dist::ReadExResp 131654 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 216513 # Request fanout histogram +system.physmem.actEnergy::0 245851200 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 224161560 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134145000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122310375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 703053000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 638905800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 426345120 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 398915280 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184635759360 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184635759360 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 80323317855 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 79082766720 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625647965000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1626736167750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1892116436535 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1891838986845 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.338580 # Core power per rank (mW) +system.physmem.averagePower::1 669.240432 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 67851 # Transaction distribution +system.membus.trans_dist::ReadResp 67850 # Transaction distribution +system.membus.trans_dist::WriteReq 27608 # Transaction distribution +system.membus.trans_dist::WriteResp 27608 # Transaction distribution +system.membus.trans_dist::Writeback 90641 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution +system.membus.trans_dist::ReadExReq 135128 # Transaction distribution +system.membus.trans_dist::ReadExResp 135128 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 633147 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16660328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16823793 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19143089 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 205 # Total snoops (count) +system.membus.snoop_fanout::samples 300256 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 300256 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 216513 # Request fanout histogram -system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 300256 # Request fanout histogram +system.membus.reqLayer0.occupancy 94208500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.5 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1358148499 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1678211205 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38219486 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution -system.iobus.trans_dist::WriteReq 8176 # Transaction distribution -system.iobus.trans_dist::WriteResp 8176 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 30181 # Transaction distribution +system.iobus.trans_dist::ReadResp 30181 # Transaction distribution +system.iobus.trans_dist::WriteReq 59035 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326561347 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36777514 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 13200672 # Number of BP lookups -system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits +system.cpu.branchPred.lookups 46931803 # Number of BP lookups +system.cpu.branchPred.condPredicted 24038690 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232826 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29540441 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21359776 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.306896 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11753594 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33738 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -507,25 +547,25 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 13156766 # DTB read hits -system.cpu.checker.dtb.read_misses 7319 # DTB read misses -system.cpu.checker.dtb.write_hits 11227349 # DTB write hits -system.cpu.checker.dtb.write_misses 2193 # DTB write misses -system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.read_hits 24593793 # DTB read hits +system.cpu.checker.dtb.read_misses 8242 # DTB read misses +system.cpu.checker.dtb.write_hits 19641565 # DTB write hits +system.cpu.checker.dtb.write_misses 1441 # DTB write misses +system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed +system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA +system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 4295 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1773 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 13164085 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229542 # DTB write accesses +system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 24602035 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19643006 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 24384115 # DTB hits -system.cpu.checker.dtb.misses 9512 # DTB misses -system.cpu.checker.dtb.accesses 24393627 # DTB accesses +system.cpu.checker.dtb.hits 44235358 # DTB hits +system.cpu.checker.dtb.misses 9683 # DTB misses +system.cpu.checker.dtb.accesses 44245041 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -547,28 +587,28 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61486106 # ITB inst hits -system.cpu.checker.itb.inst_misses 4473 # ITB inst misses +system.cpu.checker.itb.inst_hits 115874779 # ITB inst hits +system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 2372 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb 128 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA +system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 2977 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61490579 # ITB inst accesses -system.cpu.checker.itb.hits 61486106 # DTB hits -system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61490579 # DTB accesses -system.cpu.checker.numCycles 72947471 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 115879605 # ITB inst accesses +system.cpu.checker.itb.hits 115874779 # DTB hits +system.cpu.checker.itb.misses 4826 # DTB misses +system.cpu.checker.itb.accesses 115879605 # DTB accesses +system.cpu.checker.numCycles 139125744 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -594,25 +634,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31644036 # DTB read hits -system.cpu.dtb.read_misses 39518 # DTB read misses -system.cpu.dtb.write_hits 11381434 # DTB write hits -system.cpu.dtb.write_misses 10146 # DTB write misses -system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch +system.cpu.dtb.read_hits 25464394 # DTB read hits +system.cpu.dtb.read_misses 60419 # DTB read misses +system.cpu.dtb.write_hits 19915991 # DTB write hits +system.cpu.dtb.write_misses 9380 # DTB write misses +system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31683554 # DTB read accesses -system.cpu.dtb.write_accesses 11391580 # DTB write accesses +system.cpu.dtb.perms_faults 1298 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25524813 # DTB read accesses +system.cpu.dtb.write_accesses 19925371 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 43025470 # DTB hits -system.cpu.dtb.misses 49664 # DTB misses -system.cpu.dtb.accesses 43075134 # DTB accesses +system.cpu.dtb.hits 45380385 # DTB hits +system.cpu.dtb.misses 69799 # DTB misses +system.cpu.dtb.accesses 45450184 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -634,348 +674,349 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 24158829 # ITB inst hits -system.cpu.itb.inst_misses 10513 # ITB inst misses +system.cpu.itb.inst_hits 66292387 # ITB inst hits +system.cpu.itb.inst_misses 11931 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 128 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 24169342 # ITB inst accesses -system.cpu.itb.hits 24158829 # DTB hits -system.cpu.itb.misses 10513 # DTB misses -system.cpu.itb.accesses 24169342 # DTB accesses -system.cpu.numCycles 499362415 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66304318 # ITB inst accesses +system.cpu.itb.hits 66292387 # DTB hits +system.cpu.itb.misses 11931 # DTB misses +system.cpu.itb.accesses 66304318 # DTB accesses +system.cpu.numCycles 260551438 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104869846 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184735553 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46931803 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33113370 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145618302 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6158524 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 168617 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7866 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 338980 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 503793 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66292691 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1129489 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4986 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 254586778 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.885055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.237579 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155297274 61.00% 61.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29234666 11.48% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14075849 5.53% 78.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55978989 21.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 254586778 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180125 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.709018 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78083511 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105413176 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64659521 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3829076 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2601494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422198 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486019 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157443787 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3691480 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2601494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83923016 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10014229 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74542225 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62654018 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20851796 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146804356 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 950141 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 437053 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62758 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16395 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18089126 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150489312 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678755433 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164431250 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141833425 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8655884 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2845858 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2649612 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13844659 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26410647 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21300346 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1686617 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2194239 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143538852 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2120894 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143334300 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269212 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6251138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14652316 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125305 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 254586778 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.563008 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.882453 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166323253 65.33% 65.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45116884 17.72% 83.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32035807 12.58% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10297567 4.04% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813234 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254586778 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7369685 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5632098 24.94% 57.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9582629 42.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96007549 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113996 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26193546 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21008282 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued -system.cpu.iq.rate 0.188049 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143334300 # Type of FU issued +system.cpu.iq.rate 0.550119 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22584444 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157565 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564073322 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151915928 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140220511 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35712 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165892999 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23408 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 324281 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1489992 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 534 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18266 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701073 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88010 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6363 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2601494 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 945264 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 289569 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145860692 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26410647 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21300346 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096041 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 254692 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18266 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317528 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471649 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789177 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142391856 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25792498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872750 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 176011 # number of nop insts executed -system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed -system.cpu.iew.exec_branches 10791373 # Number of branches executed -system.cpu.iew.exec_stores 11888962 # Number of stores executed -system.cpu.iew.exec_rate 0.186737 # Inst execution rate -system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back -system.cpu.iew.wb_producers 35461894 # num instructions producing a value -system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value +system.cpu.iew.exec_nop 200946 # number of nop insts executed +system.cpu.iew.exec_refs 46671293 # number of memory reference insts executed +system.cpu.iew.exec_branches 26532601 # Number of branches executed +system.cpu.iew.exec_stores 20878795 # Number of stores executed +system.cpu.iew.exec_rate 0.546502 # Inst execution rate +system.cpu.iew.wb_sent 142004641 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140231942 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63282838 # num instructions producing a value +system.cpu.iew.wb_consumers 95859178 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back +system.cpu.iew.wb_rate 0.538212 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7590534 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995589 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755058 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251652322 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.546095 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.146746 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178202586 70.81% 70.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43292722 17.20% 88.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15476092 6.15% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4357171 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6368006 2.53% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1679722 0.67% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777425 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414219 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1084379 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60462353 # Number of instructions committed -system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251652322 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113327248 # Number of instructions committed +system.cpu.commit.committedOps 137426168 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 25244590 # Number of memory references committed -system.cpu.commit.loads 13512938 # Number of loads committed -system.cpu.commit.membars 403660 # Number of memory barriers committed -system.cpu.commit.branches 10308077 # Number of branches committed -system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 64250158 # Number of committed integer instructions. -system.cpu.commit.function_calls 991634 # Number of function calls committed. +system.cpu.commit.refs 45519928 # Number of memory references committed +system.cpu.commit.loads 24920655 # Number of loads committed +system.cpu.commit.membars 814679 # Number of memory barriers committed +system.cpu.commit.branches 26048896 # Number of branches committed +system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. +system.cpu.commit.int_insts 120245785 # Number of committed integer instructions. +system.cpu.commit.function_calls 4892513 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91784658 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112993 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24920655 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20599273 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction -system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137426168 # Class of committed instruction +system.cpu.commit.bw_lim_events 1084379 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 568215140 # The number of ROB reads -system.cpu.rob.rob_writes 154414029 # The number of ROB writes -system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60311972 # Number of Instructions Simulated -system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads -system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 109116744 # number of integer regfile reads -system.cpu.int_regfile_writes 47012213 # number of integer regfile writes -system.cpu.fp_regfile_reads 8305 # number of floating regfile reads -system.cpu.fp_regfile_writes 2780 # number of floating regfile writes -system.cpu.cc_regfile_reads 320409321 # number of cc regfile reads -system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes -system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 26770 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.rob.rob_reads 373356629 # The number of ROB reads +system.cpu.rob.rob_writes 292965429 # The number of ROB writes +system.cpu.timesIdled 892862 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5964660 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393139912 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113172343 # Number of Instructions Simulated +system.cpu.committedOps 137271263 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.302254 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.302254 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434357 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434357 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155828809 # number of integer regfile reads +system.cpu.int_regfile_writes 88634134 # number of integer regfile writes +system.cpu.fp_regfile_reads 9591 # number of floating regfile reads +system.cpu.fp_regfile_writes 2716 # number of floating regfile writes +system.cpu.cc_regfile_reads 503010936 # number of cc regfile reads +system.cpu.cc_regfile_writes 53185281 # number of cc regfile writes +system.cpu.misc_regfile_reads 444154417 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521566 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 2565070 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2565005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296628 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795251 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31166 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128727 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6450401 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121302864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98352737 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46636 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219917661 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65503 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3561986 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9.010233 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram @@ -986,273 +1027,283 @@ system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 2266210 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 3525536 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 36450 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2266210 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3090363565 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3561986 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2503006527 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2849563150 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2544137605 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 17681240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1334496858 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 19512240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 51517661 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74894955 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 959838 # number of replacements -system.cpu.icache.tags.tagsinuse 511.383389 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23148830 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 960350 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 24.104576 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 11339333250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.383389 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1894110 # number of replacements +system.cpu.icache.tags.tagsinuse 511.373809 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64308148 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1894622 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.942469 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.373809 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 25114544 # Number of tag accesses -system.cpu.icache.tags.data_accesses 25114544 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23148830 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23148830 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23148830 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23148830 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23148830 # number of overall hits -system.cpu.icache.overall_hits::total 23148830 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1005344 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1005344 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1005344 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1005344 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1005344 # number of overall misses -system.cpu.icache.overall_misses::total 1005344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13667748229 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13667748229 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13667748229 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13667748229 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13667748229 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13667748229 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24154174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24154174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24154174 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24154174 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24154174 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24154174 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.096036 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13595.096036 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13595.096036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13595.096036 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1628 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68184330 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68184330 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64308148 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64308148 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64308148 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64308148 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64308148 # number of overall hits +system.cpu.icache.overall_hits::total 64308148 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1981542 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1981542 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1981542 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1981542 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1981542 # number of overall misses +system.cpu.icache.overall_misses::total 1981542 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763338374 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26763338374 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26763338374 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26763338374 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26763338374 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26763338374 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66289690 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66289690 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66289690 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66289690 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66289690 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66289690 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029892 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029892 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029892 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029892 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029892 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029892 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.319005 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13506.319005 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13506.319005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13506.319005 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2089 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 118 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 104 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 13.796610 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.086538 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44974 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 44974 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 44974 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 44974 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 44974 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 44974 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960370 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 960370 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 960370 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 960370 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 960370 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 960370 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11288731510 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11288731510 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11288731510 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11288731510 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11288731510 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11288731510 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223034500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223034500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223034500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 223034500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039760 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.039760 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.039760 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11754.564918 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11754.564918 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86900 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 86900 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 86900 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 86900 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 86900 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 86900 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894642 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1894642 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1894642 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1894642 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1894642 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1894642 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22157720096 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22157720096 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22157720096 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22157720096 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22157720096 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22157720096 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202542500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202542500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202542500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 202542500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028581 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028581 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028581 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11694.937669 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11694.937669 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 63303 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51126.923594 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1828959 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 128691 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.212019 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2530750696500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37301.769799 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.815946 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7722.177507 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.159639 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.569180 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000104 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117831 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.093020 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.780135 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65381 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3025 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6220 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997635 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18315394 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18315394 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33880 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9473 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 947730 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 377075 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1368158 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 599947 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 599947 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113210 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113210 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 33880 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 9473 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 947730 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 490285 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1481368 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 33880 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 9473 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 947730 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 490285 # number of overall hits -system.cpu.l2cache.overall_hits::total 1481368 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 11652 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10148 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 21814 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2909 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133357 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133357 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 11 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 11652 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143505 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 155171 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 11 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 11652 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143505 # number of overall misses -system.cpu.l2cache.overall_misses::total 155171 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 835556749 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 759914000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1596499749 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 349485 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 349485 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9345897297 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9345897297 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 835556749 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10105811297 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10942397046 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 835556749 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10105811297 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10942397046 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33891 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9476 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 959382 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 387223 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1389972 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 599947 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 599947 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2950 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33891 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 9476 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 959382 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 633790 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1636539 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33891 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 9476 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 959382 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 633790 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1636539 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000325 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000317 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012145 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015694 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986102 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986102 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540855 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540855 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000325 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000317 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012145 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.226424 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.094817 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000325 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000317 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012145 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.226424 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.094817 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71886.363636 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79416.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71709.298747 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74883.129681 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73186.932658 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 120.139223 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 120.139223 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70081.790210 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70081.790210 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70518.312352 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70518.312352 # average overall miss latency +system.cpu.l2cache.tags.replacements 98637 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65077.786040 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3021048 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163850 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.437888 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 49563.565409 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798460 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.530935 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5190.672892 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.756280 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157326 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.079203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.993008 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65200 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2970 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7016 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55034 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 28438268 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 28438268 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53837 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11652 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1874630 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 528067 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2468186 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 695424 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 695424 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 34 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 34 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 159691 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 159691 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 53837 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 11652 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1874630 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 687758 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2627877 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 53837 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 11652 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1874630 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 687758 # number of overall hits +system.cpu.l2cache.overall_hits::total 2627877 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 19979 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 13624 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33629 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2734 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2734 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 136937 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 136937 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 19979 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 150561 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 170566 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 19979 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 150561 # number of overall misses +system.cpu.l2cache.overall_misses::total 170566 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1661750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1496766000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1081319750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2580283750 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 582975 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 582975 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46498 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9921795191 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9921795191 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1661750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1496766000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11003114941 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12502078941 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1661750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1496766000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11003114941 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12502078941 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53856 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11659 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894609 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 541691 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2501815 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 695424 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 695424 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2768 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2768 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296628 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296628 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53856 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 11659 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1894609 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 838319 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2798443 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53856 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 11659 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1894609 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 838319 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2798443 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000353 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000600 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010545 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025151 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.013442 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987717 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987717 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461646 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.461646 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000353 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000600 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010545 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.179599 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060950 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000353 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000600 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010545 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.179599 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060950 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87460.526316 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76607.142857 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74916.962811 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79368.742660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76727.935710 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.231529 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.231529 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23249 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72455.181514 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72455.181514 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73297.602928 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73297.602928 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1261,104 +1312,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58488 # number of writebacks -system.cpu.l2cache.writebacks::total 58488 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11638 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10108 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 21759 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133357 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133357 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 11638 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143465 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 155116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 11638 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143465 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 155116 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 596250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 201250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 688774749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 631278500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1320850749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29121909 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29121909 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7684221703 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7684221703 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 596250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 201250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 688774749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8315500203 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9005072452 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 596250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 201250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 688774749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8315500203 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9005072452 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174356000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167012344750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167186700750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17146783596 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17146783596 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174356000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184159128346 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184333484346 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026104 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015654 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540855 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540855 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.094783 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.094783 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59183.257347 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62453.353779 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60703.651317 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.969062 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.969062 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57621.434968 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57621.434968 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 90641 # number of writebacks +system.cpu.l2cache.writebacks::total 90641 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 19 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19954 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13512 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33492 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2734 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2734 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136937 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 136937 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 19954 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 150449 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 170429 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19954 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 150449 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 170429 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1426250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1244689750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 905485750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152053000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27405734 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27405734 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8208319809 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8208319809 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1426250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1244689750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9113805559 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10360372809 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1426250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1244689750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9113805559 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10360372809 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157860000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387400000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545260000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107351500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107351500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157860000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494751500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652611500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024944 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013387 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987717 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987717 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461646 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461646 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060901 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060901 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62377.956801 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67013.451007 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64255.732712 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.043160 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.043160 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59942.307842 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59942.307842 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1368,184 +1424,184 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 633278 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.949941 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19068568 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 633790 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.086571 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.949941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 837784 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958472 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40159350 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838296 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.905931 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 244993250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958472 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 91796938 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 91796938 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11311263 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11311263 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7209463 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7209463 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60828 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60828 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236419 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236419 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18520726 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18520726 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18581554 # number of overall hits -system.cpu.dcache.overall_hits::total 18581554 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 573243 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 573243 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3012489 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3012489 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 126499 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 126499 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 12987 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 12987 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3585732 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3585732 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3712231 # number of overall misses -system.cpu.dcache.overall_misses::total 3712231 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7223298916 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7223298916 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126143348315 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126143348315 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 177246500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 177246500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133366647231 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133366647231 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133366647231 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133366647231 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 11884506 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 11884506 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10221952 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10221952 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 187327 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 187327 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249406 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 249406 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 22106458 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22106458 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 22293785 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22293785 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048234 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.048234 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675284 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.675284 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.162203 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.162203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166514 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166514 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12600.762532 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12600.762532 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41873.463543 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41873.463543 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13647.994148 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13647.994148 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37193.701936 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37193.701936 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35926.279165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35926.279165 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17394 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 459 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1226 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.187602 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 459 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 179375223 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179375223 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23322313 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23322313 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15585229 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15585229 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346650 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346650 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441994 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441994 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460302 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460302 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38907542 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38907542 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39254192 # number of overall hits +system.cpu.dcache.overall_hits::total 39254192 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 700487 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 700487 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3573434 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3573434 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177076 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177076 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26736 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26736 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 4273921 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4273921 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4450997 # number of overall misses +system.cpu.dcache.overall_misses::total 4450997 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9902093641 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9902093641 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 135168862785 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 135168862785 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356751499 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 356751499 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145070956426 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145070956426 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145070956426 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145070956426 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24022800 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24022800 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19158663 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19158663 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523726 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523726 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468730 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468730 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460307 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460307 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43181463 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43181463 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43705189 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43705189 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029159 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029159 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186518 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186518 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.098976 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.098976 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.101841 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.101841 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14136.013432 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14136.013432 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37826.041501 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37826.041501 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13343.488143 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13343.488143 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33943.293857 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33943.293857 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.912650 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32592.912650 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 507999 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6927 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 73.336076 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 599947 # number of writebacks -system.cpu.dcache.writebacks::total 599947 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271762 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 271762 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3034890 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3034890 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3034890 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3034890 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301481 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 301481 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249361 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249361 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74144 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 74144 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11754 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11754 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 550842 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 695424 # number of writebacks +system.cpu.dcache.writebacks::total 695424 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286296 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 286296 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274169 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3274169 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3560465 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3560465 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3560465 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3560465 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414191 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414191 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299265 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299265 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8325 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8325 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 713456 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713456 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 832762 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 832762 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5344701667 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5344701667 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11882128205 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11882128205 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479845001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479845001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110272000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110272000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17226829872 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17226829872 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18706674873 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18706674873 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792653500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792653500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440471453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440471453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233124953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233124953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227802 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227802 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017761 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017761 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016522 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016522 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019054 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019054 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12903.954135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12903.954135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39704.369722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39704.369722 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.776851 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.776851 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.885886 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.885886 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.609361 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.609361 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22463.410762 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22463.410762 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1553,32 +1609,96 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.replacements 36410 # number of replacements +system.iocache.tags.tagsinuse 0.999683 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.999683 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328020 # Number of tag accesses +system.iocache.tags.data_accesses 328020 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses +system.iocache.ReadReq_misses::total 220 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses +system.iocache.demand_misses::total 220 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 220 # number of overall misses +system.iocache.overall_misses::total 220 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 26405377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 26405377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 26405377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 26405377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 26405377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 26405377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36227 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36227 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000083 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000083 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 120024.440909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120024.440909 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120024.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120024.440909 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 14964377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14964377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2231467484 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2231467484 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 14964377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14964377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 14964377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14964377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68019.895455 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68019.895455 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index a054d64a7..205f12926 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename= +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 -flags_addr=268435504 -gic_cpu_addr=520093952 +flags_addr=469827632 +gic_cpu_addr=738205696 have_generic_timer=false have_large_asid_64=false have_lpae=false @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 -load_offset=0 -machine_type=RealView_PBX +load_offset=2147483648 +machine_type=VExpress_EMM mem_mode=timing -mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +mem_ranges=2147483648:2415919103 +memories=system.realview.nvmem system.physmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -53,14 +53,14 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[0] +system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=268435456:520093695 1073741824:1610612735 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -612,6 +612,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu0.istage2_mmu] @@ -1238,6 +1239,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu1.istage2_mmu] @@ -1375,15 +1377,16 @@ type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 -use_default_range=false +use_default_range=true width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] type=BaseCache children=tags -addr_ranges=0:134217727 +addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain eventq_index=0 @@ -1402,8 +1405,8 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[26] -mem_side=system.membus.slave[2] +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] [system.iocache.tags] type=LRU @@ -1438,7 +1441,7 @@ tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c.tags] type=LRU @@ -1461,8 +1464,8 @@ system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -1518,6 +1521,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -1527,7 +1531,7 @@ mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive -range=0:134217727 +range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1556,46 +1560,37 @@ tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 -port=system.membus.master[6] +port=system.membus.master[5] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=0 +pci_cfg_base=805306368 pci_cfg_gen_offsets=false pci_io_base=0 system=system -[system.realview.a9scu] -type=A9SCU -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=520093696 -pio_latency=100000 -system=system -pio=system.membus.master[4] - [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268451840 +pio_addr=470024192 pio_latency=100000 system=system -pio=system.iobus.master[21] +pio=system.iobus.master[18] [system.realview.cf_ctrl] type=IdeController -BAR0=402653184 +BAR0=471465984 BAR0LegacyIO=true -BAR0Size=16 -BAR1=402653440 +BAR0Size=256 +BAR1=471466240 BAR1LegacyIO=true -BAR1Size=1 +BAR1Size=4096 BAR2=1 BAR2LegacyIO=false BAR2Size=8 @@ -1665,18 +1660,18 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 -disks=system.cf0 +disks= eventq_index=0 -io_shift=1 +io_shift=2 pci_bus=2 -pci_dev=7 +pci_dev=0 pci_func=0 pio_latency=30000 platform=system.realview system=system -config=system.iobus.master[8] +config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.clcd] type=Pl111 @@ -1685,8 +1680,8 @@ clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic -int_num=55 -pio_addr=268566528 +int_num=46 +pio_addr=471793664 pio_latency=10000 pixel_clock=41667 system=system @@ -1694,51 +1689,129 @@ vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] -[system.realview.dmac_fake] -type=AmbaFake -amba_id=0 +[system.realview.energy_ctrl] +type=EnergyCtrl clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler eventq_index=0 -ignore_access=false -pio_addr=268632064 +pio_addr=470286336 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[22] -[system.realview.energy_ctrl] -type=EnergyCtrl +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler +config_latency=20000 eventq_index=0 -pio_addr=268496896 -pio_latency=100000 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] pio=system.iobus.master[25] -[system.realview.flash_fake] -type=IsaFake -clk_domain=system.clk_domain +[system.realview.generic_timer] +type=GenericTimer eventq_index=0 -fake_mem=true -pio_addr=1073741824 -pio_latency=100000 -pio_size=536870912 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 +gic=system.realview.gic +int_num=29 system=system -update_data=false -warn_access= -pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain -cpu_addr=520093952 +cpu_addr=738205696 cpu_pio_delay=10000 -dist_addr=520097792 +dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 int_latency=10000 @@ -1748,38 +1821,111 @@ platform=system.realview system=system pio=system.membus.master[2] -[system.realview.gpio0_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268513280 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.gpio1_fake] -type=AmbaFake -amba_id=0 +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 clk_domain=system.clk_domain +enable_capture=true eventq_index=0 -ignore_access=false -pio_addr=268517376 -pio_latency=100000 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 system=system -pio=system.iobus.master[17] +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] -[system.realview.gpio2_fake] -type=AmbaFake -amba_id=0 +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 eventq_index=0 -ignore_access=false -pio_addr=268521472 -pio_latency=100000 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview system=system -pio=system.iobus.master[18] +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] [system.realview.kmi0] type=Pl050 @@ -1788,13 +1934,13 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=52 +int_num=44 is_mouse=false -pio_addr=268460032 +pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.kmi1] type=Pl050 @@ -1803,20 +1949,20 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=53 +int_num=45 is_mouse=true -pio_addr=268464128 +pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false -pio_addr=520101888 +pio_addr=739246080 pio_latency=100000 pio_size=4095 ret_bad_addr=false @@ -1827,7 +1973,25 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[3] +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer @@ -1836,10 +2000,10 @@ eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 -pio_addr=520095232 +pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[3] [system.realview.mmc_fake] type=AmbaFake @@ -1847,10 +2011,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268455936 +pio_addr=470089728 pio_latency=100000 system=system -pio=system.iobus.master[22] +pio=system.iobus.master[21] [system.realview.nvmem] type=SimpleMemory @@ -1862,18 +2026,30 @@ in_addr_map=true latency=30000 latency_var=0 null=false -range=2147483648:2214592511 +range=0:67108863 port=system.membus.master[1] +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 -idreg=0 -pio_addr=268435456 +idreg=35979264 +pio_addr=469827584 pio_latency=100000 -proc_id0=201326592 -proc_id1=201327138 +proc_id0=335544320 +proc_id1=335544320 system=system pio=system.iobus.master[1] @@ -1884,34 +2060,12 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=42 -pio_addr=268529664 +int_num=36 +pio_addr=471269376 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[23] - -[system.realview.sci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268492800 -pio_latency=100000 -system=system -pio=system.iobus.master[20] - -[system.realview.smc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=269357056 -pio_latency=100000 -system=system -pio=system.iobus.master[13] +pio=system.iobus.master[10] [system.realview.sp810_fake] type=AmbaFake @@ -1919,21 +2073,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true -pio_addr=268439552 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.ssp_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268488704 +pio_addr=469893120 pio_latency=100000 system=system -pio=system.iobus.master[19] +pio=system.iobus.master[16] [system.realview.timer0] type=Sp804 @@ -1943,9 +2086,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=36 -int_num1=36 -pio_addr=268505088 +int_num0=34 +int_num1=34 +pio_addr=470876160 pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1958,9 +2101,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=37 -int_num1=37 -pio_addr=268509184 +int_num0=35 +int_num1=35 +pio_addr=470941696 pio_latency=100000 system=system pio=system.iobus.master[3] @@ -1972,8 +2115,8 @@ end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=44 -pio_addr=268472320 +int_num=37 +pio_addr=470351872 pio_latency=100000 platform=system.realview system=system @@ -1986,10 +2129,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268476416 +pio_addr=470417408 pio_latency=100000 system=system -pio=system.iobus.master[10] +pio=system.iobus.master[13] [system.realview.uart2_fake] type=AmbaFake @@ -1997,10 +2140,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268480512 +pio_addr=470482944 pio_latency=100000 system=system -pio=system.iobus.master[11] +pio=system.iobus.master[14] [system.realview.uart3_fake] type=AmbaFake @@ -2008,10 +2151,54 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268484608 +pio_addr=470548480 pio_latency=100000 system=system -pio=system.iobus.master[12] +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] [system.realview.watchdog_fake] type=AmbaFake @@ -2019,10 +2206,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268500992 +pio_addr=470745088 pio_latency=100000 system=system -pio=system.iobus.master[15] +pio=system.iobus.master[17] [system.terminal] type=Terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 9dee17aa2..061d104e8 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -1,13 +1,44 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: LCD dual screen mode not supported +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR +warn: instruction 'mcr bpiall' unimplemented +warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: allocating bonus target for snoop +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: instruction 'mcr dcisw' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 52743013f..a9432ee5f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,15 +1,32 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:22:42 -gem5 started Jun 21 2014 21:27:42 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:14:43 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu0.isa: ISA system set to: 0x628e100 0x628e100 - 0: system.cpu1.isa: ISA system set to: 0x628e100 0x628e100 -info: Using bootloader at address 0x80000000 -info: Using kernel entry physical address at 0x8000 +info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu0.isa: ISA system set to: 0x5555b00 0x5555b00 + 0: system.cpu1.isa: ISA system set to: 0x5555b00 0x5555b00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80008000 +info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2605245500000 because m5_exit instruction encountered +info: Read CNTFREQ_EL0 frequency +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +Exiting @ tick 2824356167500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 3111af0d9..dc7744710 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,192 +1,199 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.607932 # Number of seconds simulated -sim_ticks 2607931908500 # Number of ticks simulated -final_tick 2607931908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.824356 # Number of seconds simulated +sim_ticks 2824356167500 # Number of ticks simulated +final_tick 2824356167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52184 # Simulator instruction rate (inst/s) -host_op_rate 62850 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2168410643 # Simulator tick rate (ticks/s) -host_mem_usage 492092 # Number of bytes of host memory used -host_seconds 1202.69 # Real time elapsed on the host -sim_insts 62761278 # Number of instructions simulated -sim_ops 75589768 # Number of ops (including micro ops) simulated +host_inst_rate 95847 # Simulator instruction rate (inst/s) +host_op_rate 116283 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2253286315 # Simulator tick rate (ticks/s) +host_mem_usage 605880 # Number of bytes of host memory used +host_seconds 1253.44 # Real time elapsed on the host +sim_insts 120137953 # Number of instructions simulated +sim_ops 145753814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 208 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 336 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 208 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 336 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 74 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 119 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 74 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 119 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 74 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 122112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 457724 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 4608960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 71568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 618744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 5382208 # Number of bytes read from this memory -system.physmem.bytes_read::total 132372740 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 122112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 71568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4391552 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7420688 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 286048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1048060 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10518784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 32848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 551328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1337024 # Number of bytes read from this memory +system.physmem.bytes_read::total 13777996 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 286048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 32848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 318896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7262976 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 9599056 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 4443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 7211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 72015 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1161 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9686 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 84097 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15317443 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 68618 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 825902 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46439298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 46823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 175512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 1767285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 27442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 237255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 2063784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50757744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 46823 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 27442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 74266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1683921 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1154990 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2845430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1683921 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46439298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 46823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 182031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 1767285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 27442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1392245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 2063784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53603174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15317443 # Number of read requests accepted -system.physmem.writeReqs 825902 # Number of write requests accepted -system.physmem.readBursts 15317443 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 825902 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976329024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3987328 # Total number of bytes read from write queue -system.physmem.bytesWritten 7443968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132372740 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7420688 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 62302 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709563 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 16003 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 957415 # Per bank write bursts -system.physmem.perBankRdBursts::1 954356 # Per bank write bursts -system.physmem.perBankRdBursts::2 951532 # Per bank write bursts -system.physmem.perBankRdBursts::3 951095 # Per bank write bursts -system.physmem.perBankRdBursts::4 960453 # Per bank write bursts -system.physmem.perBankRdBursts::5 954333 # Per bank write bursts -system.physmem.perBankRdBursts::6 950562 # Per bank write bursts -system.physmem.perBankRdBursts::7 950350 # Per bank write bursts -system.physmem.perBankRdBursts::8 957423 # Per bank write bursts -system.physmem.perBankRdBursts::9 955252 # Per bank write bursts -system.physmem.perBankRdBursts::10 950399 # Per bank write bursts -system.physmem.perBankRdBursts::11 949996 # Per bank write bursts -system.physmem.perBankRdBursts::12 957025 # Per bank write bursts -system.physmem.perBankRdBursts::13 954231 # Per bank write bursts -system.physmem.perBankRdBursts::14 950565 # Per bank write bursts -system.physmem.perBankRdBursts::15 950154 # Per bank write bursts -system.physmem.perBankWrBursts::0 7537 # Per bank write bursts -system.physmem.perBankWrBursts::1 7271 # Per bank write bursts -system.physmem.perBankWrBursts::2 7519 # Per bank write bursts -system.physmem.perBankWrBursts::3 7339 # Per bank write bursts -system.physmem.perBankWrBursts::4 7525 # Per bank write bursts -system.physmem.perBankWrBursts::5 7506 # Per bank write bursts -system.physmem.perBankWrBursts::6 7304 # Per bank write bursts -system.physmem.perBankWrBursts::7 7173 # Per bank write bursts -system.physmem.perBankWrBursts::8 7520 # Per bank write bursts -system.physmem.perBankWrBursts::9 7613 # Per bank write bursts -system.physmem.perBankWrBursts::10 6934 # Per bank write bursts -system.physmem.perBankWrBursts::11 6533 # Per bank write bursts -system.physmem.perBankWrBursts::12 7225 # Per bank write bursts -system.physmem.perBankWrBursts::13 7011 # Per bank write bursts -system.physmem.perBankWrBursts::14 7249 # Per bank write bursts -system.physmem.perBankWrBursts::15 7053 # Per bank write bursts +system.physmem.num_reads::cpu0.inst 6715 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 16901 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 164356 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 580 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8638 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 20891 # Number of read requests responded to by this memory +system.physmem.num_reads::total 218142 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 113484 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 154144 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 101279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 371079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3724312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 11630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 195205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 473391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4878279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 101279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11630 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2571551 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 820837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3398671 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2571551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 821177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 101279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 377348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3724312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 11630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 195219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 473391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8276949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 218142 # Number of read requests accepted +system.physmem.writeReqs 154144 # Number of write requests accepted +system.physmem.readBursts 218142 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 154144 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13946624 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 14464 # Total number of bytes read from write queue +system.physmem.bytesWritten 9613440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 13777996 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9599056 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 226 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13812 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 13742 # Per bank write bursts +system.physmem.perBankRdBursts::1 13629 # Per bank write bursts +system.physmem.perBankRdBursts::2 14383 # Per bank write bursts +system.physmem.perBankRdBursts::3 14277 # Per bank write bursts +system.physmem.perBankRdBursts::4 15951 # Per bank write bursts +system.physmem.perBankRdBursts::5 13005 # Per bank write bursts +system.physmem.perBankRdBursts::6 13913 # Per bank write bursts +system.physmem.perBankRdBursts::7 13901 # Per bank write bursts +system.physmem.perBankRdBursts::8 13634 # Per bank write bursts +system.physmem.perBankRdBursts::9 13374 # Per bank write bursts +system.physmem.perBankRdBursts::10 12813 # Per bank write bursts +system.physmem.perBankRdBursts::11 11699 # Per bank write bursts +system.physmem.perBankRdBursts::12 13387 # Per bank write bursts +system.physmem.perBankRdBursts::13 14173 # Per bank write bursts +system.physmem.perBankRdBursts::14 13330 # Per bank write bursts +system.physmem.perBankRdBursts::15 12705 # Per bank write bursts +system.physmem.perBankWrBursts::0 9697 # Per bank write bursts +system.physmem.perBankWrBursts::1 9775 # Per bank write bursts +system.physmem.perBankWrBursts::2 10292 # Per bank write bursts +system.physmem.perBankWrBursts::3 9920 # Per bank write bursts +system.physmem.perBankWrBursts::4 9082 # Per bank write bursts +system.physmem.perBankWrBursts::5 9049 # Per bank write bursts +system.physmem.perBankWrBursts::6 9470 # Per bank write bursts +system.physmem.perBankWrBursts::7 9454 # Per bank write bursts +system.physmem.perBankWrBursts::8 9424 # Per bank write bursts +system.physmem.perBankWrBursts::9 9315 # Per bank write bursts +system.physmem.perBankWrBursts::10 9173 # Per bank write bursts +system.physmem.perBankWrBursts::11 8636 # Per bank write bursts +system.physmem.perBankWrBursts::12 9486 # Per bank write bursts +system.physmem.perBankWrBursts::13 9567 # Per bank write bursts +system.physmem.perBankWrBursts::14 9156 # Per bank write bursts +system.physmem.perBankWrBursts::15 8714 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2607930021000 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 2824354558500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 59 # Read request sizes (log2) -system.physmem.readPktSize::3 15138841 # Read request sizes (log2) -system.physmem.readPktSize::4 3437 # Read request sizes (log2) +system.physmem.readPktSize::2 559 # Read request sizes (log2) +system.physmem.readPktSize::3 28 # Read request sizes (log2) +system.physmem.readPktSize::4 3083 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175106 # Read request sizes (log2) +system.physmem.readPktSize::6 214472 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 757284 # Write request sizes (log2) +system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 68618 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1022635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1020084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 981701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1092290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 979402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1043990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2669652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2569034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3344990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 138441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 119851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 110072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 105368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149708 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 53602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 76817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11051 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -202,671 +209,716 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1020956 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 963.580205 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 884.289338 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 220.002398 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 33463 3.28% 3.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19295 1.89% 5.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8776 0.86% 6.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2662 0.26% 6.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3249 0.32% 6.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2138 0.21% 6.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8494 0.83% 7.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1074 0.11% 7.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 941805 92.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1020956 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6723 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2269.096237 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 97829.440322 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6717 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6723 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6723 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.300610 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.224413 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.695658 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3618 53.82% 53.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 52 0.77% 54.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1623 24.14% 78.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 981 14.59% 93.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 153 2.28% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 115 1.71% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 65 0.97% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 63 0.94% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 23 0.34% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 16 0.24% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.10% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6723 # Writes before turning the bus around for reads -system.physmem.totQLat 400005056750 # Total ticks spent queuing -system.physmem.totMemAccLat 686038950500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76275705000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26221.00 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 253.699567 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.705803 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 308.390709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46941 50.55% 50.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18915 20.37% 70.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6813 7.34% 78.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3565 3.84% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3222 3.47% 85.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2153 2.32% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1230 1.32% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1078 1.16% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8949 9.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92866 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7533 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.928183 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 527.934330 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7532 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7533 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7533 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.940263 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.639504 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.756386 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6124 81.30% 81.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 560 7.43% 88.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 110 1.46% 90.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 221 2.93% 93.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 195 2.59% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.28% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.23% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 21 0.28% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 30 0.40% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.11% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.04% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.04% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 162 2.15% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.09% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.08% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.17% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.09% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7533 # Writes before turning the bus around for reads +system.physmem.totQLat 8921648500 # Total ticks spent queuing +system.physmem.totMemAccLat 13007573500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1089580000 # Total ticks spent in databus transfers +system.physmem.avgQLat 40940.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44971.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.76 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 59690.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.95 # Data bus utilization in percentage -system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.13 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing -system.physmem.readRowHits 14262971 # Number of row buffer hits during reads -system.physmem.writeRowHits 87526 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.23 # Row buffer hit rate for writes -system.physmem.avgGap 161548.30 # Average gap between requests -system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2277790546750 # Time in different power states -system.physmem.memoryStateTime::REF 87084400000 # Time in different power states +system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.17 # Average write queue length when enqueuing +system.physmem.readRowHits 185257 # Number of row buffer hits during reads +system.physmem.writeRowHits 90003 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.91 # Row buffer hit rate for writes +system.physmem.avgGap 7586518.32 # Average gap between requests +system.physmem.pageHitRate 74.77 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2697281054000 # Time in different power states +system.physmem.memoryStateTime::REF 94311360000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 243051888250 # Time in different power states +system.physmem.memoryStateTime::ACT 32761026000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3862736640 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3855690720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2107644000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2103799500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 59514748800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 59475351000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 383447520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 370254240 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 170337086400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 170337086400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 141921165285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 140687744850 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1440263842500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1441345790250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1818390671145 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1818175716960 # Total energy per rank (pJ) -system.physmem.averagePower::0 697.255251 # Core power per rank (mW) -system.physmem.averagePower::1 697.172828 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 16496763 # Transaction distribution -system.membus.trans_dist::ReadResp 16496763 # Transaction distribution -system.membus.trans_dist::WriteReq 769202 # Transaction distribution -system.membus.trans_dist::WriteResp 769202 # Transaction distribution -system.membus.trans_dist::Writeback 68618 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58416 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 23667 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16003 # Transaction distribution -system.membus.trans_dist::ReadExReq 15703 # Transaction distribution -system.membus.trans_dist::ReadExResp 8933 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384368 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13898 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045296 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4445638 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34723270 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27796 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18682900 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21107657 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 142218185 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 72850 # Total snoops (count) -system.membus.snoop_fanout::samples 332577 # Request fanout histogram +system.physmem.actEnergy::0 364739760 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 337327200 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 199014750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 184057500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 879847800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 819897000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 497268720 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 476092080 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184473020160 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184473020160 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 78882264090 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 78474830085 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625417087250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1625774485500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1890713242530 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1890539709525 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.432241 # Core power per rank (mW) +system.physmem.averagePower::1 669.370799 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 237803 # Transaction distribution +system.membus.trans_dist::ReadResp 237803 # Transaction distribution +system.membus.trans_dist::WriteReq 30981 # Transaction distribution +system.membus.trans_dist::WriteResp 30981 # Transaction distribution +system.membus.trans_dist::Writeback 113484 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 79622 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40753 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13812 # Transaction distribution +system.membus.trans_dist::ReadExReq 31225 # Transaction distribution +system.membus.trans_dist::ReadExResp 14907 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 709115 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 830877 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 903587 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27500 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21057756 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21248442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23567738 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123113 # Total snoops (count) +system.membus.snoop_fanout::samples 501114 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 332577 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 501114 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 332577 # Request fanout histogram -system.membus.reqLayer0.occupancy 1569259492 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 13500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 501114 # Request fanout histogram +system.membus.reqLayer0.occupancy 81319989 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11956494 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11512493 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1552000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17698783999 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5007965719 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37372928091 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.4 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1643090249 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 2114237552 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38543657 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 91666 # number of replacements -system.l2c.tags.tagsinuse 54831.199714 # Cycle average of tags in use -system.l2c.tags.total_refs 387443 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 156491 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.475817 # Average number of references to valid blocks. +system.l2c.tags.replacements 153338 # number of replacements +system.l2c.tags.tagsinuse 64407.351795 # Cycle average of tags in use +system.l2c.tags.total_refs 520948 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 218016 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.389494 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 7736.589041 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.331203 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.025467 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 672.803532 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1677.780077 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24285.244228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.407687 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 678.722766 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3493.963497 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 16278.332216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.118051 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000020 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 14039.109160 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 10.926266 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.063683 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1406.687456 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2124.369402 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39350.084930 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.463090 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.906491 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 305.066680 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 911.182744 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6250.491894 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.214220 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000167 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.010266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.025601 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370563 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.010356 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.053314 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.248388 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.836658 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 52524 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 12291 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5897 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 46469 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 327 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2272 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 9679 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.801453 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000153 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.187546 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5049935 # Number of tag accesses -system.l2c.tags.data_accesses 5049935 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 116 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 44 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 4746 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 14884 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 72204 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 168 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 72 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 7407 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 16636 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 74707 # number of ReadReq hits -system.l2c.ReadReq_hits::total 190984 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 213987 # number of Writeback hits -system.l2c.Writeback_hits::total 213987 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3107 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2045 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5152 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 90 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 245 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 335 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 1803 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2746 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4549 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 116 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 44 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 4746 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 16687 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 72204 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 168 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 72 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7407 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 19382 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 74707 # number of demand (read+write) hits -system.l2c.demand_hits::total 195533 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 116 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 44 # number of overall hits -system.l2c.overall_hits::cpu0.inst 4746 # number of overall hits -system.l2c.overall_hits::cpu0.data 16687 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 72204 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 168 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 72 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7407 # number of overall hits -system.l2c.overall_hits::cpu1.data 19382 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 74707 # number of overall hits -system.l2c.overall_hits::total 195533 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.021464 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.032415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.600435 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000114 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004655 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013904 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.095375 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.982778 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 44311 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 20347 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 406 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 7760 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 36145 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4612 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 15362 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.676132 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.310471 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6600636 # Number of tag accesses +system.l2c.tags.data_accesses 6600636 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 292 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 154 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 12492 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 39083 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182457 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 82 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 48 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 4094 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11500 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44186 # number of ReadReq hits +system.l2c.ReadReq_hits::total 294388 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 252842 # number of Writeback hits +system.l2c.Writeback_hits::total 252842 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 11706 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 12433 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 197 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 154 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 351 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3674 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1157 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4831 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 292 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 154 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 12492 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 42757 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 182457 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 82 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 48 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 4094 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 12657 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 44186 # number of demand (read+write) hits +system.l2c.demand_hits::total 299219 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 292 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 154 # number of overall hits +system.l2c.overall_hits::cpu0.inst 12492 # number of overall hits +system.l2c.overall_hits::cpu0.data 42757 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 182457 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 82 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 48 # number of overall hits +system.l2c.overall_hits::cpu1.inst 4094 # number of overall hits +system.l2c.overall_hits::cpu1.data 12657 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 44186 # number of overall hits +system.l2c.overall_hits::total 299219 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 31 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 1063 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 3259 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1104 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4621 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq misses -system.l2c.ReadReq_misses::total 166173 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 7830 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5610 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13440 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1272 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1187 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2459 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 3945 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5092 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 9037 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 3722 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8649 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164359 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 492 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1396 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 20906 # number of ReadReq misses +system.l2c.ReadReq_misses::total 199570 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8911 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2815 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11726 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 768 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1215 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1983 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 7775 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7235 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 15010 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 31 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 1063 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 7204 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1104 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9713 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) misses -system.l2c.demand_misses::total 175210 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses +system.l2c.demand_misses::cpu0.inst 3722 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 16424 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 164359 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 492 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8631 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 20906 # number of demand (read+write) misses +system.l2c.demand_misses::total 214580 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 31 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 1063 # number of overall misses -system.l2c.overall_misses::cpu0.data 7204 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 72015 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1104 # number of overall misses -system.l2c.overall_misses::cpu1.data 9713 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 84097 # number of overall misses -system.l2c.overall_misses::total 175210 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 195250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 182000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 88517249 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 251848999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 744500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 96486500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 359268498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17143743646 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 12214974 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 6369731 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 18584705 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 508980 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4358314 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4867294 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 294129193 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 380271953 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 674401146 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 195250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 182000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 88517249 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 545978192 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 744500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 96486500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 739540451 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17818144792 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 195250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 182000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 88517249 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 545978192 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 744500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 96486500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 739540451 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17818144792 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 119 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 47 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 5809 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 18143 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 144219 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 176 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 72 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 8511 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 21257 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 158804 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 357157 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 213987 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 213987 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10937 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 7655 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18592 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1362 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1432 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2794 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 5748 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 7838 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 13586 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 119 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 47 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 5809 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 23891 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 144219 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 176 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 72 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 8511 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 29095 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 158804 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 370743 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 119 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 47 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 5809 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 23891 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 144219 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 176 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 72 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 8511 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 29095 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 158804 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 370743 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.063830 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.182992 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.179629 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.129714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.217387 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.465266 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.715918 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.732854 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.722892 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.933921 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.828911 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.880100 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.686326 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.649656 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.665170 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.063830 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.182992 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.301536 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.129714 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.333837 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.472592 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.063830 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.182992 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.301536 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.129714 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.333837 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.472592 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83271.165569 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 77277.999079 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 87397.192029 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 77746.915819 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 103168.045627 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1560.022222 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1135.424421 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1382.790551 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 400.141509 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3671.705139 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1979.379423 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74557.463371 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74680.273566 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 74626.662167 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 101695.935118 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 101695.935118 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 369 # number of cycles access was blocked +system.l2c.overall_misses::cpu0.inst 3722 # number of overall misses +system.l2c.overall_misses::cpu0.data 16424 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 164359 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 492 # number of overall misses +system.l2c.overall_misses::cpu1.data 8631 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 20906 # number of overall misses +system.l2c.overall_misses::total 214580 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2653000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 225500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 348764246 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 769947990 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 875000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 50097250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 119367500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 22807506228 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 7178208 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2570892 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 9749100 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1432440 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 791466 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2223906 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 708658416 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 564088479 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1272746895 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2653000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 225500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 348764246 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1478606406 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 875000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 50097250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 683455979 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 24080253123 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2653000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 225500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 348764246 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1478606406 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 875000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 50097250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 683455979 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of overall miss cycles +system.l2c.overall_miss_latency::total 24080253123 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 323 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 157 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 16214 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 47732 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346816 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 93 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 49 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 4586 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12896 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65092 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 493958 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 252842 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 252842 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 20617 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3542 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 24159 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 965 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1369 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2334 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 11449 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 8392 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 19841 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 323 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 157 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 16214 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 59181 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346816 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 93 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 49 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 4586 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 21288 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65092 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 513799 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 323 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 157 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 16214 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 59181 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346816 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 93 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 49 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 4586 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 21288 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65092 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 513799 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019108 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.229555 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.181199 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020408 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.107283 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.108251 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.404022 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.432216 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.794749 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.485368 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.795855 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.887509 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.849614 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.679099 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.862131 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.756514 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.019108 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.229555 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.277522 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.020408 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.107283 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.405440 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.417634 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.019108 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.229555 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.277522 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.020408 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.107283 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.405440 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.417634 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75166.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 93703.451370 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 89021.619840 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 101823.678862 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 85506.805158 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 114283.240106 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 805.544608 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 913.283126 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 831.408835 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1865.156250 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 651.412346 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1121.485628 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91145.776977 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77966.617692 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 84793.264157 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75166.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 93703.451370 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 90027.180102 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 101823.678862 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 79186.186884 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 112220.398560 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75166.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 93703.451370 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 90027.180102 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 101823.678862 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 79186.186884 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 112220.398560 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 435 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 26 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 36.900000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 16.730769 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 68618 # number of writebacks -system.l2c.writebacks::total 68618 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 113484 # number of writebacks +system.l2c.writebacks::total 113484 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 15 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 31 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 1063 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 3259 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1104 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4621 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 166173 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 7830 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 5610 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 13440 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1272 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1187 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2459 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 3945 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 5092 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 9037 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 3721 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8649 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 491 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1396 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 199550 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8911 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2815 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11726 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 768 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1215 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1983 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 7775 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7235 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 15010 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 31 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 1063 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 7204 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1104 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9713 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 175210 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 3721 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 16424 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 491 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8631 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 214560 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 31 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 1063 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 7204 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1104 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9713 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 175210 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 158750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 145000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 75361749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 211101499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 645000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 82874000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 301675998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15091446656 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 79003615 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56662566 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 135666181 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12832754 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11966179 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 24798933 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 244772807 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 316260047 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 561032854 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 158750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 145000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 75361749 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 455874306 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 645000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 82874000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 617936045 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 15652479510 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 158750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 145000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 75361749 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 455874306 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 645000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 82874000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 617936045 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 15652479510 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 178129250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12343853503 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3278250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154953535743 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167478796746 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1076363997 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16025248776 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17101612773 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 178129250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13420217500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3278250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170978784519 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184580409519 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.179629 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217387 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.465266 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.715918 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.732854 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.722892 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.933921 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.828911 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.880100 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.686326 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.649656 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.665170 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.472592 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.472592 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64774.930654 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65283.704393 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 90817.681910 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.861430 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10100.279144 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10094.209896 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10088.643082 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.026959 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10084.966653 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62046.338910 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62109.200118 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62081.758770 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 3721 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 16424 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 491 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8631 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 214560 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 187500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 302749246 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 662570490 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 738500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 43998750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 101980500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 20353955728 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 90147824 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28509296 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 118657120 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7897727 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12233707 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 20131434 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 612435582 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 472780517 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1085216099 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 187500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 302749246 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1275006072 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 738500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 43998750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 574761017 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 21439171827 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 187500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 302749246 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1275006072 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 738500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 43998750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 574761017 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 21439171827 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 158715000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3685804000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5055250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919801500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5769375750 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713908502 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535177501 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4249086003 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 158715000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6399712502 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5055250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3454979001 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10018461753 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181199 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.108251 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.403982 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.432216 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.794749 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.485368 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795855 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.887509 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.849614 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.679099 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.862131 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.756514 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.417595 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.417595 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76606.600763 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73051.934097 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 101999.277013 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10116.465492 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10127.636234 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.147194 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10283.498698 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10068.894650 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10152.009077 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78769.849775 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65346.305045 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72299.540240 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -881,167 +933,194 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 1650974 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1650974 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 769202 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 769202 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 213987 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 63464 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 24002 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 87466 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 23286 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 23286 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760669 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337396 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5098065 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18146443 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24785598 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 42932041 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 177868 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 783993 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 660507 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 660492 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30981 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30981 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 252842 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 91952 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41104 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 133056 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 40101 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 40101 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1300560 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426210 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1726770 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40798474 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8541616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 49340090 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 291850 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1084776 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.033629 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.180273 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 783993 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1048296 96.64% 96.64% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36480 3.36% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 783993 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2614417508 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1084776 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1587917075 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1150691896 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2659939258 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 16322916 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322916 # Transaction distribution -system.iobus.trans_dist::WriteReq 8084 # Transaction distribution -system.iobus.trans_dist::WriteResp 8084 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8832 # Packet count per connected master and slave (bytes) +system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2276216676 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 846189675 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 31016 # Transaction distribution +system.iobus.trans_dist::ReadResp 31016 # Transaction distribution +system.iobus.trans_dist::WriteReq 59419 # Transaction distribution +system.iobus.trans_dist::WriteResp 59440 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 21 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 740 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384368 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32662000 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 394 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4422000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 442000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376284000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38188943909 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6445077 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4515785 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 302094 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3732049 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2838132 # Number of BTB hits +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326647327 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36834343 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 24027935 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15717476 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 977431 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 14651046 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 10773468 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.047555 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 777958 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 15130 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.533780 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3878036 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32430 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1065,25 +1144,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6738270 # DTB read hits -system.cpu0.dtb.read_misses 20792 # DTB read misses -system.cpu0.dtb.write_hits 5108254 # DTB write hits -system.cpu0.dtb.write_misses 4938 # DTB write misses -system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch +system.cpu0.dtb.read_hits 17722520 # DTB read hits +system.cpu0.dtb.read_misses 56371 # DTB read misses +system.cpu0.dtb.write_hits 14647463 # DTB write hits +system.cpu0.dtb.write_misses 8727 # DTB write misses +system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 304 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2355 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6759062 # DTB read accesses -system.cpu0.dtb.write_accesses 5113192 # DTB write accesses +system.cpu0.dtb.perms_faults 853 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17778891 # DTB read accesses +system.cpu0.dtb.write_accesses 14656190 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 11846524 # DTB hits -system.cpu0.dtb.misses 25730 # DTB misses -system.cpu0.dtb.accesses 11872254 # DTB accesses +system.cpu0.dtb.hits 32369983 # DTB hits +system.cpu0.dtb.misses 65098 # DTB misses +system.cpu0.dtb.accesses 32435081 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1105,811 +1184,793 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 11251934 # ITB inst hits -system.cpu0.itb.inst_misses 5844 # ITB inst misses +system.cpu0.itb.inst_hits 37749886 # ITB inst hits +system.cpu0.itb.inst_misses 10298 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2364 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2392 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1942 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 11257778 # ITB inst accesses -system.cpu0.itb.hits 11251934 # DTB hits -system.cpu0.itb.misses 5844 # DTB misses -system.cpu0.itb.accesses 11257778 # DTB accesses -system.cpu0.numCycles 70547986 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 37760184 # ITB inst accesses +system.cpu0.itb.hits 37749886 # DTB hits +system.cpu0.itb.misses 10298 # DTB misses +system.cpu0.itb.accesses 37760184 # DTB accesses +system.cpu0.numCycles 126958641 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 4766943 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 34365037 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6445077 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3616090 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 61724532 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 827468 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 75473 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 31308 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 103372 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 2299403 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 9118 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 11252710 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 69213 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1641 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 69423883 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.597378 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.081788 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 18143411 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 112712815 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 24027935 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 14651504 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 104787507 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2823240 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 133419 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 39139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 365906 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 432078 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 38034 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 37750510 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 265510 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3919 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 125351114 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.084784 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.263056 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 50336190 72.51% 72.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 6591848 9.50% 82.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2607109 3.76% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 9888736 14.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 62795131 50.10% 50.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 21461544 17.12% 67.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8765998 6.99% 74.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 32328441 25.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 69423883 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.091357 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.487116 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 6423281 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 48508889 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12244404 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1928072 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 319237 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 872011 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 96101 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 34918059 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 1200237 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 319237 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 8391286 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 22294228 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 11033133 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 12128468 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 15257531 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 33562016 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 347139 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 4725852 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2951017 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 10590659 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 2752771 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 34856617 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 154488080 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 39935090 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 3818 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30135138 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4721470 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 454498 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 374192 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4720858 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 6116778 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5560819 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 585791 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 708239 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 32317524 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 796272 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 32794597 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 169276 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 3620256 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 7615411 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 145849 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 69423883 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.472382 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.871380 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 125351114 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.189258 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.887792 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19217150 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58693987 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 41414238 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4958351 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1067388 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3055751 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 348432 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 110728193 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3997819 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1067388 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24968075 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11998776 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 36565512 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 40482982 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10268381 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 105647193 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1060681 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1440352 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 161094 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 60996 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6068574 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 109731042 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 482381977 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 120921551 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9385 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 98136808 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11594231 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1228692 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1087401 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12320869 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18735521 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 16202725 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1699910 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2282844 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 102687285 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1694390 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 100670059 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 484670 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9020348 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22495673 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 122680 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 125351114 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.803105 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.034773 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 50273243 72.41% 72.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9200980 13.25% 85.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 6622047 9.54% 95.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2961360 4.27% 99.47% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 365822 0.53% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 431 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 69205207 55.21% 55.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 23183333 18.49% 73.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 22514733 17.96% 91.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 9334141 7.45% 99.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1113663 0.89% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 69423883 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 125351114 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2899348 33.55% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 364 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 2954493 34.19% 67.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 2788370 32.26% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 9379501 40.75% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 82 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5582636 24.26% 65.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8053143 34.99% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14544 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 20241553 61.72% 61.77% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 42703 0.13% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7058068 21.52% 83.42% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5437045 16.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 66409608 65.97% 65.97% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 93111 0.09% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18430675 18.31% 84.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 15726281 15.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 32794597 # Type of FU issued -system.cpu0.iq.rate 0.464855 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 8642575 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.263537 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 143812961 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 36735702 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 31078347 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11966 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4590 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 41415013 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7615 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 165813 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 100670059 # Type of FU issued +system.cpu0.iq.rate 0.792936 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 23015362 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228622 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 350159403 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 113409879 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 98581657 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 31861 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9722 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 123662544 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 20604 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 365489 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 774144 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 762 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 6359 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 332945 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2006423 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2595 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19219 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1022338 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1087991 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 169554 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 106441 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 337136 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 319237 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7637691 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 6668537 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 33216242 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1615648 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 188928 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 104556414 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 6116778 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5560819 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 485296 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 10796 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6648479 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 6359 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 101328 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 128415 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 229743 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 32427250 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 6903411 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 342013 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 18735521 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 16202725 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 876047 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27263 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 138025 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19219 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 291871 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 400586 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 692457 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 99572602 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 17974009 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1032494 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 102446 # number of nop insts executed -system.cpu0.iew.exec_refs 12283212 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4700114 # Number of branches executed -system.cpu0.iew.exec_stores 5379801 # Number of stores executed -system.cpu0.iew.exec_rate 0.459648 # Inst execution rate -system.cpu0.iew.wb_sent 32232102 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 31082185 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 15739944 # num instructions producing a value -system.cpu0.iew.wb_consumers 27168343 # num instructions consuming a value +system.cpu0.iew.exec_nop 174739 # number of nop insts executed +system.cpu0.iew.exec_refs 33508875 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16843329 # Number of branches executed +system.cpu0.iew.exec_stores 15534866 # Number of stores executed +system.cpu0.iew.exec_rate 0.784292 # Inst execution rate +system.cpu0.iew.wb_sent 99041613 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 98591379 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 51320038 # num instructions producing a value +system.cpu0.iew.wb_consumers 84796920 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.440582 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.579349 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.776563 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.605211 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 3250105 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 650423 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 207597 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 68788504 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.427377 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.179796 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 8526320 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1571710 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 633199 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 123596989 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.768069 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.480980 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 54880088 79.78% 79.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7965099 11.58% 91.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2563469 3.73% 95.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1116854 1.62% 96.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 779155 1.13% 97.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 426783 0.62% 98.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 259327 0.38% 98.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 232321 0.34% 99.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 565408 0.82% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 79268840 64.13% 64.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 24713999 20.00% 84.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 8247824 6.67% 90.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3215855 2.60% 93.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3439875 2.78% 96.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1518279 1.23% 97.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1140929 0.92% 98.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 533748 0.43% 98.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1517640 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 68788504 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24068410 # Number of instructions committed -system.cpu0.commit.committedOps 29398607 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 123596989 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 78900966 # Number of instructions committed +system.cpu0.commit.committedOps 94931037 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10570507 # Number of memory references committed -system.cpu0.commit.loads 5342633 # Number of loads committed -system.cpu0.commit.membars 231974 # Number of memory barriers committed -system.cpu0.commit.branches 4351471 # Number of branches committed -system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 25743783 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499778 # Number of function calls committed. +system.cpu0.commit.refs 31909485 # Number of memory references committed +system.cpu0.commit.loads 16729098 # Number of loads committed +system.cpu0.commit.membars 647159 # Number of memory barriers committed +system.cpu0.commit.branches 16205509 # Number of branches committed +system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 81880566 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1929583 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 18787662 63.91% 63.91% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 39754 0.14% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 684 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 5342633 18.17% 82.22% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5227874 17.78% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 62922752 66.28% 66.28% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 90691 0.10% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 16729098 17.62% 84.01% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 15180387 15.99% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 29398607 # Class of committed instruction -system.cpu0.commit.bw_lim_events 565408 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 94931037 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1517640 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 99997744 # The number of ROB reads -system.cpu0.rob.rob_writes 65895627 # The number of ROB writes -system.cpu0.timesIdled 89184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 1124103 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5145325170 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23987668 # Number of Instructions Simulated -system.cpu0.committedOps 29317865 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.941011 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.941011 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.340019 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.340019 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 37156240 # number of integer regfile reads -system.cpu0.int_regfile_writes 18851805 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads -system.cpu0.fp_regfile_writes 840 # number of floating regfile writes -system.cpu0.cc_regfile_reads 113767432 # number of cc regfile reads -system.cpu0.cc_regfile_writes 12814569 # number of cc regfile writes -system.cpu0.misc_regfile_reads 112163009 # number of misc regfile reads -system.cpu0.misc_regfile_writes 502202 # number of misc regfile writes -system.cpu0.toL2Bus.trans_dist::ReadReq 900797 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 693938 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 10818 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 10818 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 228050 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 268938 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 56335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24640 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 62766 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 133470 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 124418 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651974 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1223749 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16358 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46407 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 1938488 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20698608 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38615195 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 26900 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 80012 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 59420715 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 640729 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 1524410 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.372076 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.483359 # Request fanout histogram +system.cpu0.rob.rob_reads 221353668 # The number of ROB reads +system.cpu0.rob.rob_writes 208668086 # The number of ROB writes +system.cpu0.timesIdled 109562 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1607527 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5521753720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 78778915 # Number of Instructions Simulated +system.cpu0.committedOps 94808986 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.611581 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.611581 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.620508 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.620508 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 110614815 # number of integer regfile reads +system.cpu0.int_regfile_writes 59737885 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8165 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes +system.cpu0.cc_regfile_reads 350771001 # number of cc regfile reads +system.cpu0.cc_regfile_writes 41073809 # number of cc regfile writes +system.cpu0.misc_regfile_reads 245697526 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1224542 # number of misc regfile writes +system.cpu0.toL2Bus.trans_dist::ReadReq 2022292 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1921231 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19109 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19109 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 512497 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 635775 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 81120 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43298 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 105236 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 291864 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 281152 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2535030 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2361050 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28910 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120430 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5045420 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80976096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86183658 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50232 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 218780 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 167428766 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1029243 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3600041 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.252406 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.434393 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 957213 62.79% 62.79% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 567197 37.21% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2691370 74.76% 74.76% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 908671 25.24% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 1524410 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 761732905 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 71201999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3600041 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1889888022 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 117489749 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 488672410 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 613319434 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1901826585 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1220473591 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 9639487 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 16363478 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 26428702 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 65772430 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 322116 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.545879 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10915164 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 322628 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 33.832042 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6524367000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.545879 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999113 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999113 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1263981 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.774384 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36445999 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1264493 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.822618 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6310719000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774384 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 22821148 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 22821148 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 10915164 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10915164 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 10915164 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10915164 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 10915164 # number of overall hits -system.cpu0.icache.overall_hits::total 10915164 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 334091 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 334091 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 334091 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 334091 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 334091 # number of overall misses -system.cpu0.icache.overall_misses::total 334091 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 2863305358 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 2863305358 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 2863305358 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 2863305358 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 2863305358 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 2863305358 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 11249255 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11249255 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 11249255 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11249255 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 11249255 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11249255 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029699 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029699 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029699 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029699 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029699 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029699 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8570.435474 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8570.435474 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8570.435474 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8570.435474 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 177531 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 22346 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.944643 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 61.400000 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 76759130 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 76759130 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36445999 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36445999 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36445999 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36445999 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36445999 # number of overall hits +system.cpu0.icache.overall_hits::total 36445999 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1301304 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1301304 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1301304 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1301304 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1301304 # number of overall misses +system.cpu0.icache.overall_misses::total 1301304 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11020664802 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11020664802 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11020664802 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11020664802 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11020664802 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11020664802 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37747303 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37747303 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37747303 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37747303 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37747303 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37747303 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034474 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.034474 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034474 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.034474 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034474 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.034474 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8468.939465 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8468.939465 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8468.939465 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8468.939465 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8468.939465 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8468.939465 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 725662 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 96193 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.543813 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 11453 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 11453 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 11453 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 11453 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 11453 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 11453 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 322638 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 322638 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 322638 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 322638 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 322638 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 322638 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2310628588 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 2310628588 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2310628588 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 2310628588 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2310628588 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 2310628588 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 272886999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 272886999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 272886999 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 272886999 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028681 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028681 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028681 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7161.675277 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36779 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 36779 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 36779 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 36779 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 36779 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 36779 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264525 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1264525 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264525 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1264525 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264525 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1264525 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8921757516 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8921757516 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8921757516 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8921757516 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8921757516 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8921757516 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243776998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 243776998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 243776998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 243776998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033500 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033500 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033500 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7055.422009 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7055.422009 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7055.422009 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 3529222 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 247992 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2979692 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86609 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11570902 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525454 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10431616 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 117790 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16144 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 198785 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 261906 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25307 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 470730 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881250 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 165160 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15951.411231 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 747099 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 181321 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.120311 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 4999805500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4772.372752 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.637155 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.084033 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 735.053900 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1518.442449 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8912.820942 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.291283 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000710 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000066 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044864 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.092678 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.543995 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.973597 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7338 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8811 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1027 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5229 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 943 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1656 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6017 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.447876 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.537781 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 15517001 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 15517001 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 19658 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 6554 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 314769 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 162769 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 503750 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 228045 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 228045 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 6593 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 6593 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 622 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 622 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 95529 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 95529 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 19658 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 6554 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 314769 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 258298 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 599279 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 19658 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 6554 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 314769 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 258298 # number of overall hits -system.cpu0.l2cache.overall_hits::total 599279 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 345 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 7801 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 50805 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 59122 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 5 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 5 # number of Writeback misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 19680 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 19680 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10856 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 10856 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 23597 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 23597 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 345 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 7801 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 74402 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 82719 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 345 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 7801 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 74402 # number of overall misses -system.cpu0.l2cache.overall_misses::total 82719 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7498249 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3753000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 255179729 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1303745054 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1570176032 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 310997961 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 310997961 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 212766148 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 212766148 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 609000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 609000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 893661798 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 893661798 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7498249 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3753000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 255179729 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 2197406852 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 2463837830 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7498249 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3753000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 255179729 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 2197406852 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 2463837830 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 20003 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 6725 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 322570 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 213574 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 562872 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 228050 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 228050 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11478 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 11478 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 119126 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 119126 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 20003 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 6725 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 322570 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 332700 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 681998 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 20003 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 6725 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 322570 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 332700 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 681998 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025428 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.024184 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.237880 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.105036 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000022 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000022 # miss rate for Writeback accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.749058 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.749058 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.945809 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.945809 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.198084 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.198084 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025428 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.024184 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.223631 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.121289 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025428 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.024184 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.223631 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.121289 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21947.368421 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 32711.156134 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25661.746954 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26558.236054 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15802.741921 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15802.741921 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19598.945099 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19598.945099 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 609000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 609000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37871.839556 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37871.839556 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 29785.633651 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 29785.633651 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 4781 # number of cycles access was blocked +system.cpu0.l2cache.tags.replacements 397283 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16205.229139 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2244912 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 413530 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.428656 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2809069613500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4639.805304 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.151524 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.649414 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 948.692737 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1410.057987 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9191.872173 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.283191 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000803 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000101 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.057904 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086063 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.561027 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989089 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8152 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8085 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 51 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 237 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3322 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4084 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 458 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 501 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3682 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3594 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 245 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.497559 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.493469 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 43590224 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 43590224 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54156 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12330 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242747 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 407291 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1716524 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 512497 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 512497 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15462 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 15462 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2188 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2188 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216542 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 216542 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54156 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12330 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1242747 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 623833 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1933066 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54156 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12330 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1242747 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 623833 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1933066 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 539 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 228 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21755 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 91027 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 113549 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27999 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 27999 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18512 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18512 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52925 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 52925 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 539 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 228 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 21755 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 143952 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 166474 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 539 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 228 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 21755 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 143952 # number of overall misses +system.cpu0.l2cache.overall_misses::total 166474 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14141500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5255000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 812129434 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2705700107 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 3537226041 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502587457 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 502587457 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362338282 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362338282 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 217500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 217500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2594310029 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2594310029 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14141500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5255000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 812129434 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 5300010136 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 6131536070 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14141500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5255000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 812129434 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 5300010136 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 6131536070 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54695 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12558 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1264502 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498318 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1830073 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 512497 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 512497 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43461 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 43461 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20700 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20700 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269467 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269467 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54695 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12558 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1264502 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 767785 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2099540 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54695 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12558 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1264502 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 767785 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2099540 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.018156 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017204 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182668 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.062046 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.644233 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.644233 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.894300 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.894300 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.196406 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.196406 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.018156 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017204 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.187490 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.079291 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.018156 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017204 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.187490 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.079291 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23048.245614 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37330.702551 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29724.148956 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31151.538464 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17950.193114 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17950.193114 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19573.156979 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19573.156979 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49018.611790 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49018.611790 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23048.245614 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37330.702551 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36817.898577 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 36831.793974 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23048.245614 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37330.702551 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36817.898577 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 36831.793974 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 59871 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 266 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 1464 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 17.973684 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 40.895492 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 105131 # number of writebacks -system.cpu0.l2cache.writebacks::total 105131 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 212118 # number of writebacks +system.cpu0.l2cache.writebacks::total 212118 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1845 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 997 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 2844 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 936 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 936 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 5582 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3121 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 8705 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8957 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 8957 # number of ReadExReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1845 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1933 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3780 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5582 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 12078 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 17662 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1845 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1933 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3780 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 344 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 170 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 5956 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 49808 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 56278 # number of ReadReq MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::writebacks 5 # number of Writeback MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::total 5 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 198779 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 19680 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 19680 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10856 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10856 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 22661 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 22661 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 344 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 170 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 5956 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 72469 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 78939 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 344 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 170 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 5956 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 72469 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 277718 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2550500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 181100759 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 940424592 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1129080602 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8151036272 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 354005766 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 354005766 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 158485722 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 158485722 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 490000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 490000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 601346170 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 601346170 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2550500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 181100759 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1541770762 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 1730426772 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2550500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 181100759 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1541770762 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 9881463044 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244240750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 13865359008 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14109599758 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1262027985 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262027985 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 244240750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 15127386993 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15371627743 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.233212 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099984 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000022 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000022 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5582 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 12078 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 17662 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 538 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 227 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16173 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 87906 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 104844 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 470726 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 470726 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27999 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27999 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18512 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18512 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43968 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 43968 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 538 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 227 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16173 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131874 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 148812 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 538 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 227 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16173 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131874 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 470726 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 619538 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3653000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 584863774 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2018675176 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2617551450 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21918972757 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21918972757 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 483477329 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 483477329 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 250147229 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 250147229 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 175500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 175500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1315007380 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1315007380 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3653000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 584863774 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3333682556 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 3932558830 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3653000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 584863774 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3333682556 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21918972757 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 25851531587 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218357500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053329974 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4271687474 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040369451 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040369451 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218357500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7093699425 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312056925 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176405 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057290 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.749058 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.749058 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.945809 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.945809 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190227 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190227 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115747 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.644233 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.644233 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.894300 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.894300 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163167 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163167 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171759 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070878 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171759 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.407212 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18880.994860 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20062.557340 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41005.520060 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17988.097866 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17988.097866 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14598.905859 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14598.905859 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 490000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 490000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26536.612241 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26536.612241 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.062745 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35580.923973 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.295083 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22964.020385 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24966.154000 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46564.185443 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46564.185443 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17267.664167 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17267.664167 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13512.706839 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13512.706839 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29908.282842 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29908.282842 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25279.301121 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26426.355603 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25279.301121 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46564.185443 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41727.112117 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1919,192 +1980,192 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 297335 # number of replacements -system.cpu0.dcache.tags.tagsinuse 469.059398 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9029469 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 297847 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.315796 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 284699500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 469.059398 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.916132 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.916132 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 712949 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.466444 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28841621 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 713461 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.424944 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 256469000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.466444 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965755 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.965755 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 20887113 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 20887113 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4736171 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 4736171 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3900194 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3900194 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45240 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 45240 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135351 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 135351 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133505 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 133505 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8636365 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8636365 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8681605 # number of overall hits -system.cpu0.dcache.overall_hits::total 8681605 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 322447 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 322447 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 906986 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 906986 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 75027 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 75027 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10798 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 10798 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11479 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 11479 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1229433 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1229433 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1304460 # number of overall misses -system.cpu0.dcache.overall_misses::total 1304460 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3662752641 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3662752641 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13080008270 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 13080008270 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182730500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 182730500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 273467244 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 273467244 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 660000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 660000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 16742760911 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 16742760911 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 16742760911 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 16742760911 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5058618 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5058618 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4807180 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4807180 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120267 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 120267 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146149 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 146149 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144984 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144984 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9865798 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9865798 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9986065 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9986065 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063742 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063742 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.188673 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188673 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.623837 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.623837 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073884 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073884 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079174 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079174 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124616 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.124616 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130628 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.130628 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11359.239320 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11359.239320 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14421.400408 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14421.400408 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16922.624560 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16922.624560 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23823.263699 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23823.263699 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63482821 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63482821 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15588564 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15588564 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 12071351 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 12071351 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311001 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 311001 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363214 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363214 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360561 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 360561 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27659915 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27659915 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 27970916 # number of overall hits +system.cpu0.dcache.overall_hits::total 27970916 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 638335 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 638335 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1832649 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1832649 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146162 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 146162 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24977 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 24977 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20700 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20700 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2470984 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2470984 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2617146 # number of overall misses +system.cpu0.dcache.overall_misses::total 2617146 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8102181310 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8102181310 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25003432618 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 25003432618 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 396859499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 396859499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 455692776 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 455692776 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 235500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 235500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 33105613928 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 33105613928 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 33105613928 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 33105613928 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226899 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16226899 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904000 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13904000 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457163 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 457163 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388191 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388191 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381261 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381261 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30130899 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30130899 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30588062 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30588062 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039338 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.039338 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131807 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.131807 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319715 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319715 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064342 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064342 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054294 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054294 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082008 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.082008 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085561 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.085561 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12692.679095 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12692.679095 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13643.328656 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 13643.328656 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15888.997838 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15888.997838 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22014.143768 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22014.143768 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13618.278435 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13618.278435 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12835.012887 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12835.012887 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1895359 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 9 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 100025 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 18.948853 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13397.745161 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13397.745161 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12649.509782 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12649.509782 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1233 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3385599 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 70 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 191316 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.614286 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 17.696371 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 228050 # number of writebacks -system.cpu0.dcache.writebacks::total 228050 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162419 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 162419 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 762846 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 762846 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1187 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1187 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 925265 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 925265 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 925265 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 925265 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160028 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 160028 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144140 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 144140 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 44124 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 44124 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9611 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9611 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11479 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 11479 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 304168 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 304168 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 348292 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 348292 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1657269084 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1657269084 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2153079279 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2153079279 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 708295495 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 708295495 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147083500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147083500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 249287756 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 249287756 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 626000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 626000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3810348363 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 3810348363 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4518643858 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4518643858 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541407491 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541407491 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345528496 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345528496 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15886935987 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15886935987 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031635 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029984 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029984 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366884 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366884 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065762 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065762 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079174 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079174 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030831 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030831 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034878 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.034878 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10356.119454 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10356.119454 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14937.416949 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14937.416949 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16052.386343 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.386343 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15303.662470 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15303.662470 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21716.853036 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21716.853036 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 512498 # number of writebacks +system.cpu0.dcache.writebacks::total 512498 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248017 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 248017 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519903 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1519903 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18417 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18417 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767920 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1767920 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767920 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1767920 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390318 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 390318 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312746 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312746 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101547 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 101547 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6560 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6560 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20700 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20700 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 703064 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 703064 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 804611 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 804611 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4171307993 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4171307993 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4996022111 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4996022111 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1423316745 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1423316745 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98363500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98363500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 413570224 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 413570224 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9167330104 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9167330104 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10590646849 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10590646849 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4216535499 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4216535499 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187175989 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187175989 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7403711488 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7403711488 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024054 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024054 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022493 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022493 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222124 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222124 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016899 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016899 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023334 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023334 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026305 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026305 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10686.947548 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10686.947548 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15974.695475 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15974.695475 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14016.334751 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14016.334751 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14994.435976 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14994.435976 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19979.237874 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19979.237874 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12527.117787 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12527.117787 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12973.722790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12973.722790 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13039.111808 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13039.111808 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13162.443527 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13162.443527 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -2112,15 +2173,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9149866 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6786400 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 422129 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5825788 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4286605 # Number of BTB hits +system.cpu1.branchPred.lookups 33913093 # Number of BP lookups +system.cpu1.branchPred.condPredicted 11564399 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 305039 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 18757536 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 14959019 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.579832 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 927303 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 19424 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 79.749382 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12491385 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7180 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2144,25 +2205,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25102636 # DTB read hits -system.cpu1.dtb.read_misses 30137 # DTB read misses -system.cpu1.dtb.write_hits 6841685 # DTB write hits -system.cpu1.dtb.write_misses 6769 # DTB write misses -system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1912 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1186 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch +system.cpu1.dtb.read_hits 10162981 # DTB read hits +system.cpu1.dtb.read_misses 18754 # DTB read misses +system.cpu1.dtb.write_hits 6542585 # DTB write hits +system.cpu1.dtb.write_misses 2848 # DTB write misses +system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 49 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 375 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 731 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25132773 # DTB read accesses -system.cpu1.dtb.write_accesses 6848454 # DTB write accesses +system.cpu1.dtb.perms_faults 394 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10181735 # DTB read accesses +system.cpu1.dtb.write_accesses 6545433 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31944321 # DTB hits -system.cpu1.dtb.misses 36906 # DTB misses -system.cpu1.dtb.accesses 31981227 # DTB accesses +system.cpu1.dtb.hits 16705566 # DTB hits +system.cpu1.dtb.misses 21602 # DTB misses +system.cpu1.dtb.accesses 16727168 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2184,803 +2245,803 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 16803682 # ITB inst hits -system.cpu1.itb.inst_misses 6173 # ITB inst misses +system.cpu1.itb.inst_hits 43643100 # ITB inst hits +system.cpu1.itb.inst_misses 6996 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 1201 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2309 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 544 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16809855 # ITB inst accesses -system.cpu1.itb.hits 16803682 # DTB hits -system.cpu1.itb.misses 6173 # DTB misses -system.cpu1.itb.accesses 16809855 # DTB accesses -system.cpu1.numCycles 436917069 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 43650096 # ITB inst accesses +system.cpu1.itb.hits 43643100 # DTB hits +system.cpu1.itb.misses 6996 # DTB misses +system.cpu1.itb.accesses 43650096 # DTB accesses +system.cpu1.numCycles 104633766 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 7779761 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 51586006 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9149866 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5213908 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 424935366 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 1119898 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 77514 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 41827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 113975 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 2395843 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 15405 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 16801187 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 110293 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1839 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 435919640 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.141195 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 0.582401 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9986103 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 109171918 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 33913093 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 27450404 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 91805384 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3775592 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 78970 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 32292 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 198987 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 295254 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 7461 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 43642483 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 116201 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2279 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104292247 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.296794 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.339797 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 407581344 93.50% 93.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 9416514 2.16% 95.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4632400 1.06% 96.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 14289382 3.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 47342099 45.39% 45.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 14034599 13.46% 58.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7535653 7.23% 66.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 35379896 33.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 435919640 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.020942 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.118068 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 9900868 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 404219752 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 17609153 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3776585 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 413282 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1053225 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 148821 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53082842 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1693858 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 413282 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 13042184 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 210392870 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 23473030 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 17900158 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 170698116 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51361658 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 445811 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 60462789 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 44486963 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 161544271 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 5689953 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 54453588 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 239756743 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 64654520 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6270 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 48767925 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 5685663 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 754764 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 650155 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 9515727 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9671211 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7398216 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 539915 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 877439 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 49754499 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1063600 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 65146152 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 226823 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 4308815 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 9268536 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 164257 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 435919640 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.149445 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.502702 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 104292247 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.324112 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.043372 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 13023476 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 61678123 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 26726804 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1110708 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1753136 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 754254 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 137537 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 68065454 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1169726 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1753136 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17456234 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2244493 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 56986986 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 23381097 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2470301 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 55158602 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 230731 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 262273 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 35381 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18008 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1443637 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 54999686 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 260535269 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 58684549 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1692 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 52221656 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2778030 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1878103 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1805469 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13100518 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10455886 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6917101 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 629442 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 825387 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 54265513 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 589015 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 53909819 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 113491 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2298739 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 5813202 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 48820 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104292247 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.516911 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.852558 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 391740283 89.87% 89.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 28930464 6.64% 96.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 10221316 2.34% 98.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4337467 1.00% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 689895 0.16% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 215 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 71040936 68.12% 68.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16527616 15.85% 83.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 13076642 12.54% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3359306 3.22% 99.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 287734 0.28% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 13 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 435919640 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104292247 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 4426779 17.51% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 17782110 70.33% 87.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3074512 12.16% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2924694 45.09% 45.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 678 0.01% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1673523 25.80% 70.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1887909 29.10% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 14260 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 32351105 49.66% 49.68% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 60186 0.09% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.77% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 25491005 39.13% 88.91% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7227894 11.09% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36727877 68.13% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46567 0.09% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 10379543 19.25% 87.47% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6752424 12.53% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 65146152 # Type of FU issued -system.cpu1.iq.rate 0.149104 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 25284092 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.388113 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 591701467 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 55128847 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 48339304 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 21392 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7974 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6777 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 90402329 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 13655 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 164874 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 53909819 # Type of FU issued +system.cpu1.iq.rate 0.515224 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6486804 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.120327 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 218706402 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57161340 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 51920676 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5778 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2054 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 60392866 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3691 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 91423 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 922858 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 700 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 9957 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 405915 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 489842 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 678 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10158 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 359303 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16016509 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 155340 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 51794 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 70407 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 413282 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 90103879 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 101302025 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 50907640 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1753136 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 542605 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 110606 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 54906673 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9671211 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7398216 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 775761 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 15322 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 101224655 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 9957 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 133208 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 167801 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 301009 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 64655254 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25297716 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 454169 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 10455886 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6917101 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 301543 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 9870 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 93230 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10158 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 54900 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 127108 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 182008 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 53638957 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10277477 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 249277 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 89541 # number of nop insts executed -system.cpu1.iew.exec_refs 32443779 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6846575 # Number of branches executed -system.cpu1.iew.exec_stores 7146063 # Number of stores executed -system.cpu1.iew.exec_rate 0.147981 # Inst execution rate -system.cpu1.iew.wb_sent 64439493 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 48346081 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25811466 # num instructions producing a value -system.cpu1.iew.wb_consumers 39458467 # num instructions consuming a value +system.cpu1.iew.exec_nop 52145 # number of nop insts executed +system.cpu1.iew.exec_refs 16965020 # number of memory reference insts executed +system.cpu1.iew.exec_branches 11808497 # Number of branches executed +system.cpu1.iew.exec_stores 6687543 # Number of stores executed +system.cpu1.iew.exec_rate 0.512635 # Inst execution rate +system.cpu1.iew.wb_sent 53498311 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 51922462 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25227303 # num instructions producing a value +system.cpu1.iew.wb_consumers 38487680 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.110653 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.654143 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.496230 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.655464 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3859068 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899343 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 275462 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 435139005 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.106498 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 0.626723 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3659313 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 540195 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 170379 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 102361190 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.498018 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.158864 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 413392451 95.00% 95.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12955608 2.98% 97.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 3521257 0.81% 98.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1360882 0.31% 99.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1313314 0.30% 99.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 777449 0.18% 99.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 559175 0.13% 99.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 305729 0.07% 99.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 953140 0.22% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 76777637 75.01% 75.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 14293980 13.96% 88.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6079057 5.94% 94.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 703860 0.69% 95.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1980599 1.93% 97.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1570719 1.53% 99.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 440748 0.43% 99.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 123191 0.12% 99.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 391399 0.38% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 435139005 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38843249 # Number of instructions committed -system.cpu1.commit.committedOps 46341542 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 102361190 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41391892 # Number of instructions committed +system.cpu1.commit.committedOps 50977682 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 15740654 # Number of memory references committed -system.cpu1.commit.loads 8748353 # Number of loads committed -system.cpu1.commit.membars 195273 # Number of memory barriers committed -system.cpu1.commit.branches 6419002 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 41058956 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553431 # Number of function calls committed. +system.cpu1.commit.refs 16523842 # Number of memory references committed +system.cpu1.commit.loads 9966044 # Number of loads committed +system.cpu1.commit.membars 209647 # Number of memory barriers committed +system.cpu1.commit.branches 11639863 # Number of branches committed +system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 45828051 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3366801 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 30541068 65.90% 65.90% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 1702 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 8748353 18.88% 84.91% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6992301 15.09% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 34404842 67.49% 67.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 45659 0.09% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9966044 19.55% 87.14% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6557798 12.86% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 46341542 # Class of committed instruction -system.cpu1.commit.bw_lim_events 953140 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 50977682 # Class of committed instruction +system.cpu1.commit.bw_lim_events 391399 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 483317632 # The number of ROB reads -system.cpu1.rob.rob_writes 101136219 # The number of ROB writes -system.cpu1.timesIdled 117466 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 997429 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4778390126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38773610 # Number of Instructions Simulated -system.cpu1.committedOps 46271903 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 11.268413 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 11.268413 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.088744 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.088744 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 76047297 # number of integer regfile reads -system.cpu1.int_regfile_writes 30995697 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4960 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes -system.cpu1.cc_regfile_reads 220730482 # number of cc regfile reads -system.cpu1.cc_regfile_writes 19377985 # number of cc regfile writes -system.cpu1.misc_regfile_reads 520419201 # number of misc regfile reads -system.cpu1.misc_regfile_writes 723683 # number of misc regfile writes -system.cpu1.toL2Bus.trans_dist::ReadReq 2172606 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1978157 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 758384 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 758384 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 291033 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 272197 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 56199 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25233 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 54439 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 157045 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 149477 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1093505 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4944143 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17380 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65233 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 6120261 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34983760 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51460526 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28972 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 118552 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 86591810 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 595717 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1871452 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.290652 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.454063 # Request fanout histogram +system.cpu1.rob.rob_reads 136568898 # The number of ROB reads +system.cpu1.rob.rob_writes 111201426 # The number of ROB writes +system.cpu1.timesIdled 53211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 341519 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5543537240 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41359038 # Number of Instructions Simulated +system.cpu1.committedOps 50944828 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.529889 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.529889 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.395274 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.395274 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 56284416 # number of integer regfile reads +system.cpu1.int_regfile_writes 35740317 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads +system.cpu1.fp_regfile_writes 520 # number of floating regfile writes +system.cpu1.cc_regfile_reads 191161573 # number of cc regfile reads +system.cpu1.cc_regfile_writes 15561298 # number of cc regfile writes +system.cpu1.misc_regfile_reads 205957562 # number of misc regfile reads +system.cpu1.misc_regfile_writes 388863 # number of misc regfile writes +system.cpu1.toL2Bus.trans_dist::ReadReq 1295443 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 865390 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11872 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11872 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 116918 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 158167 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 84977 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41950 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 87258 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 79543 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66388 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215693 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825104 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17440 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38012 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2096249 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897120 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25415568 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31072 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 64411288 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 836156 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1798706 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.418986 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.493393 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1327511 70.93% 70.93% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 543941 29.07% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1045073 58.10% 58.10% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 753633 41.90% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1871452 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2995139487 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 46865000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1798706 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 658940429 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 81408998 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 820984463 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 913008604 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 2122961296 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 10148477 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 404124267 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 9811221 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 36069550 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 21199862 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.icache.tags.replacements 546235 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.934216 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 16238797 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 546747 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 29.700752 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 73709463000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.934216 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974481 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974481 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 607230 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.524831 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 43017967 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 607742 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 70.783272 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 78622263500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524831 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975634 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975634 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 34148852 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 34148852 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 16238797 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16238797 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16238797 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16238797 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16238797 # number of overall hits -system.cpu1.icache.overall_hits::total 16238797 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 562244 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 562244 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 562244 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 562244 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 562244 # number of overall misses -system.cpu1.icache.overall_misses::total 562244 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4743193454 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4743193454 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4743193454 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4743193454 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4743193454 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4743193454 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16801041 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16801041 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16801041 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16801041 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16801041 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16801041 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033465 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.033465 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033465 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.033465 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033465 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.033465 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.183319 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.183319 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8436.183319 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8436.183319 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 307905 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 40708 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.563747 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 87892389 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 87892389 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 43017967 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 43017967 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 43017967 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 43017967 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 43017967 # number of overall hits +system.cpu1.icache.overall_hits::total 43017967 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 624354 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 624354 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 624354 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 624354 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 624354 # number of overall misses +system.cpu1.icache.overall_misses::total 624354 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5095463294 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5095463294 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5095463294 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5095463294 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5095463294 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5095463294 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43642321 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43642321 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43642321 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43642321 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43642321 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43642321 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014306 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014306 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014306 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014306 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014306 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014306 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8161.176663 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8161.176663 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8161.176663 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8161.176663 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 277985 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 36153 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.689127 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15474 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 15474 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 15474 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 15474 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 15474 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 15474 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 546770 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 546770 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 546770 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 546770 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 546770 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 546770 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3839673113 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3839673113 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3839673113 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3839673113 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3839673113 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3839673113 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5117249 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5117249 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5117249 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5117249 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032544 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.032544 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.032544 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7022.464863 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16607 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 16607 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 16607 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 16607 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 16607 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 16607 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607747 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 607747 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 607747 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 607747 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 607747 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 607747 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4104727229 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4104727229 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4104727229 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4104727229 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4104727229 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4104727229 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7919750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7919750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7919750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 7919750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6754.006567 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6754.006567 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6754.006567 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5063185 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 195793 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4609637 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49643 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841798 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 42982 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4639721 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 43013 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 8256 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 199856 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 430863 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6040 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 110042 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564522 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 189917 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15760.362755 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1051721 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 205349 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.121627 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 2533057390500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4796.141133 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.055492 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.249384 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 825.564654 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2172.411955 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7947.940138 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.292733 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001041 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000076 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.050388 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132594 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485104 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.961936 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8428 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6994 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2154 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2511 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3763 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2597 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1568 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2829 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.514404 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.426880 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21502320 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21502320 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29274 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7085 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 535244 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 196892 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 768495 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 291031 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 291031 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2209 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2209 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1205 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1205 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 122716 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 122716 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29274 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7085 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 535244 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 319608 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 891211 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29274 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7085 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 535244 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 319608 # number of overall hits -system.cpu1.l2cache.overall_hits::total 891211 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 364 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 158 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 11361 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 60780 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 72663 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 2 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20588 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 20588 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 13188 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 13188 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 25387 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 25387 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 364 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 158 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 11361 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 86167 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 98050 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 364 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 158 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 11361 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 86167 # number of overall misses -system.cpu1.l2cache.overall_misses::total 98050 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8462000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3365000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 344449975 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1612650155 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1968927130 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 357562229 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 357562229 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 267838079 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 267838079 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1192000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1192000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1149303620 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1149303620 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8462000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3365000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 344449975 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2761953775 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3118230750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8462000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3365000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 344449975 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2761953775 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3118230750 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29638 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7243 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 546605 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 257672 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 841158 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 291033 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 291033 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 22797 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 22797 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 14393 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 14393 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 148103 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 148103 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29638 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7243 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 546605 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 405775 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 989261 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29638 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7243 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 546605 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 405775 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 989261 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.021814 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020785 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.235881 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.086384 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.903101 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.903101 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.916279 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.916279 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.replacements 85604 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15613.661542 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 844840 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 100686 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 8.390839 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5991.162043 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.384982 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.931077 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 706.431382 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1962.742096 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6937.009962 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.365672 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000878 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.043117 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.119796 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.423401 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.952982 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9479 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5582 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 323 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8003 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1153 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4223 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 941 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.578552 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001282 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.340698 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 16875679 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 16875679 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16408 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7497 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601881 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 101311 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 727097 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 116917 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 116917 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2261 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2261 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 836 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 836 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28901 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 28901 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16408 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7497 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 601881 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 130212 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 755998 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16408 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7497 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 601881 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 130212 # number of overall hits +system.cpu1.l2cache.overall_hits::total 755998 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 474 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5861 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 72219 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 78825 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28423 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28423 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22608 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22608 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32938 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 32938 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 474 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 5861 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 105157 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 111763 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 474 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 5861 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 105157 # number of overall misses +system.cpu1.l2cache.overall_misses::total 111763 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10500499 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5483500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 182847956 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1610079123 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1808911078 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536990378 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 536990378 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 443102047 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 443102047 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 554000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 554000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1287438029 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1287438029 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10500499 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5483500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 182847956 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2897517152 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3096349107 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10500499 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5483500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 182847956 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2897517152 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3096349107 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16882 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7768 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607742 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173530 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 805922 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 116918 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 116918 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30684 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 30684 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61839 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 61839 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16882 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7768 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 607742 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 235369 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 867761 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16882 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7768 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 607742 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 235369 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 867761 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.034887 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009644 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.416176 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.097807 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000009 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000009 # miss rate for Writeback accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926313 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926313 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.964341 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.964341 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.171414 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.171414 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.021814 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020785 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212352 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.099114 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.021814 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020785 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212352 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.099114 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21297.468354 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30318.631723 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 26532.579056 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27096.694741 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 17367.506752 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 17367.506752 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20309.226494 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20309.226494 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 596000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 596000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45271.344389 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45271.344389 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 31802.455380 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 31802.455380 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 8115 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532641 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532641 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.034887 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009644 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446775 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.128795 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.034887 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009644 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446775 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.128795 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20234.317343 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31197.399079 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22294.397915 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22948.443742 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18892.811385 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18892.811385 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19599.347443 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19599.347443 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 184666.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 184666.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39086.709242 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39086.709242 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20234.317343 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31197.399079 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27554.201356 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 27704.599080 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20234.317343 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31197.399079 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27554.201356 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 27704.599080 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 23432 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 442 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 464 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 18.359729 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 108849 # number of writebacks -system.cpu1.l2cache.writebacks::total 108849 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2808 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 143 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 2953 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1573 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 1573 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2808 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1716 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 4526 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2808 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1716 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 4526 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 363 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 157 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 8553 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 60637 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 69710 # number of ReadReq MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 199848 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20588 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20588 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 13188 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 13188 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 23814 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 23814 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 363 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 157 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8553 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 84451 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 93524 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 363 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 157 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8553 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 84451 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 293372 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2254500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 234181256 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1184058953 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1426398709 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10843374528 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 344645957 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 344645957 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 188520557 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 188520557 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 996000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 996000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 690789082 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 690789082 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2254500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 234181256 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1874848035 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2117187791 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2254500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 234181256 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1874848035 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 12960562319 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4572000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 174823243259 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174827815259 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 29484635658 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 29484635658 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 4572000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 204307878917 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 204312450917 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.235326 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.082874 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.writebacks::writebacks 40723 # number of writebacks +system.cpu1.l2cache.writebacks::total 40723 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 14 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1292 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 76 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 1382 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1310 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 1310 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 14 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1292 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1386 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 2692 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 14 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1292 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1386 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 2692 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 474 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 257 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4569 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72143 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 77443 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 110035 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 110035 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28423 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28423 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22608 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22608 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31628 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 31628 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 474 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 257 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4569 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103771 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 109071 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 474 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 257 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4569 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103771 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 110035 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 219106 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3513000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 126144777 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1103468683 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1240306961 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3485961286 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3485961286 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 417373575 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 417373575 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308955268 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308955268 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 463000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 463000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 944601401 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 944601401 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3513000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 126144777 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2048070084 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2184908362 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3513000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 126144777 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2048070084 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3485961286 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 5670869648 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7061250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2181994006 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189055256 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737322501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737322501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7061250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919316507 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3926377757 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415738 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.096092 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000009 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.903101 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.903101 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.916279 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.916279 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926313 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926313 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.964341 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.964341 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.160794 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.160794 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.094539 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.511457 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.511457 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440886 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125692 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440886 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.296557 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19527.004189 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20461.895123 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 54258.108803 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16740.137799 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16740.137799 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14294.855702 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14294.855702 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 498000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 498000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29007.687999 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29007.687999 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22637.908890 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 44177.911726 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.252496 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15295.575219 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16015.740106 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31680.476994 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14684.360377 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14684.360377 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.749646 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.749646 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 154333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 154333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29865.985867 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29865.985867 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20031.982488 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25881.854664 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2990,190 +3051,191 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 381661 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.780956 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12332117 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 381992 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 32.283705 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70951149500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.780956 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940978 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940978 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.646484 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 27770563 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 27770563 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 7205629 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7205629 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4858222 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4858222 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24502 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 24502 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94117 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 94117 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93451 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 93451 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12063851 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12063851 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12088353 # number of overall hits -system.cpu1.dcache.overall_hits::total 12088353 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 362275 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 362275 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 967298 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 967298 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 47536 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 47536 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14955 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14955 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 14395 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 14395 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1329573 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1329573 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1377109 # number of overall misses -system.cpu1.dcache.overall_misses::total 1377109 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4296873688 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4296873688 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15627489636 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 15627489636 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254785499 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 254785499 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 332075324 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 332075324 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1276000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1276000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 19924363324 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 19924363324 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 19924363324 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 19924363324 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7567904 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7567904 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5825520 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5825520 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 72038 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 72038 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 109072 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 109072 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107846 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 107846 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 13393424 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 13393424 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 13465462 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 13465462 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047870 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.047870 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166045 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.166045 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.659874 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.659874 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137111 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137111 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133477 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133477 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099271 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.099271 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.102270 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.102270 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11860.806536 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 11860.806536 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16155.817169 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16155.817169 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17036.810364 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17036.810364 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23068.796388 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23068.796388 # average StoreCondReq miss latency +system.cpu1.dcache.tags.replacements 191151 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.645791 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 15740842 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 191475 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 82.208341 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 102871069000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.645791 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 32982505 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 32982505 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 9573878 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9573878 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5910219 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5910219 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49544 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49544 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79107 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79107 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70933 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70933 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15484097 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15484097 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15533641 # number of overall hits +system.cpu1.dcache.overall_hits::total 15533641 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 219762 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 219762 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 398432 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 398432 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30092 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30092 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18147 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18147 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23447 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23447 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 618194 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 618194 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 648286 # number of overall misses +system.cpu1.dcache.overall_misses::total 648286 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3451433990 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3451433990 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8738929077 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8738929077 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362617750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 362617750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 543339293 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 543339293 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 593000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 593000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12190363067 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12190363067 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12190363067 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12190363067 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793640 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9793640 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308651 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6308651 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79636 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79636 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97254 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97254 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94380 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94380 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16102291 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16102291 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16181927 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16181927 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022439 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.022439 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063156 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.063156 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377869 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377869 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186594 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186594 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248432 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248432 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038392 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038392 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040062 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.040062 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15705.326626 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15705.326626 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21933.301233 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21933.301233 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19982.242244 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19982.242244 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.083678 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.083678 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14985.535449 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14985.535449 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14468.254382 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14468.254382 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4991 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 2160220 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 228 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 94010 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 21.890351 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 22.978619 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19719.316375 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19719.316375 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18803.989392 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18803.989392 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1116254 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 47 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39673 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.191489 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.136365 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 291033 # number of writebacks -system.cpu1.dcache.writebacks::total 291033 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148293 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 148293 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 797245 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 797245 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1426 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1426 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 945538 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 945538 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 945538 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 945538 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213982 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 213982 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 170053 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 170053 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30328 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 30328 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13529 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13529 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14395 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 14395 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 384035 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 384035 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 414363 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 414363 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2231950081 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2231950081 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2569103752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2569103752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 638180745 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 638180745 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208910751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208910751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 302166676 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 302166676 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1220000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1220000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4801053833 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4801053833 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5439234578 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5439234578 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183653885735 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183653885735 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50893842775 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50893842775 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234547728510 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234547728510 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028275 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028275 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029191 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029191 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.421000 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.421000 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124037 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124037 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133477 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133477 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028673 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028673 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030772 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10430.550612 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10430.550612 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15107.664975 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15107.664975 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21042.625462 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21042.625462 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15441.699387 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15441.699387 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20991.085516 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20991.085516 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 116918 # number of writebacks +system.cpu1.dcache.writebacks::total 116918 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79804 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 79804 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306588 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 306588 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13195 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13195 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 386392 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 386392 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 386392 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 386392 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139958 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 139958 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91844 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 91844 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28639 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28639 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4952 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4952 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23447 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23447 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 231802 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 231802 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 260441 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 260441 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1829576308 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1829576308 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2203829941 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2203829941 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 493924497 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 493924497 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86545750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86545750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 495264707 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 495264707 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 567000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 567000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4033406249 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4033406249 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4527330746 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4527330746 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298504494 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298504494 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826458496 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826458496 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4124962990 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4124962990 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014291 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014291 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014558 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014558 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359624 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359624 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050918 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050918 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248432 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248432 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014396 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014396 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016095 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.016095 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13072.323897 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13072.323897 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23995.361058 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23995.361058 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17246.569259 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17246.569259 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17476.928514 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17476.928514 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21122.732418 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21122.732418 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12501.604888 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12501.604888 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13126.738097 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13126.738097 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17400.221952 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.221952 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17383.325767 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17383.325767 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -3181,34 +3243,98 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.replacements 36453 # number of replacements +system.iocache.tags.tagsinuse 14.560241 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 254140751000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.560241 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328407 # Number of tag accesses +system.iocache.tags.data_accesses 328407 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses +system.iocache.ReadReq_misses::total 247 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 21 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 21 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses +system.iocache.demand_misses::total 247 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 247 # number of overall misses +system.iocache.overall_misses::total 247 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 30846377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 30846377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 30846377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 30846377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 30846377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 30846377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36245 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36245 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000579 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000579 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124884.117409 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124884.117409 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124884.117409 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736182068909 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736182068909 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18001377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18001377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2249753293 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2249753293 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18001377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18001377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18001377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18001377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72880.068826 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42962 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50554 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2758 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal Binary files differindex 9ab4c62df..cc9c3e898 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 51ab195cc..65705e13f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain -atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename= +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 -flags_addr=268435504 -gic_cpu_addr=520093952 +flags_addr=469827632 +gic_cpu_addr=738205696 have_generic_timer=false have_large_asid_64=false have_lpae=false @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 -load_offset=0 -machine_type=RealView_PBX +load_offset=2147483648 +machine_type=VExpress_EMM mem_mode=timing -mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +mem_ranges=2147483648:2415919103 +memories=system.realview.nvmem system.physmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -53,14 +53,14 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[0] +system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=268435456:520093695 1073741824:1610612735 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -612,6 +612,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -678,7 +679,7 @@ tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.cpu.l2cache.tags] type=LRU @@ -732,15 +733,16 @@ type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 -use_default_range=false +use_default_range=true width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] type=BaseCache children=tags -addr_ranges=0:134217727 +addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain eventq_index=0 @@ -759,8 +761,8 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[26] -mem_side=system.membus.slave[2] +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] [system.iocache.tags] type=LRU @@ -783,8 +785,8 @@ system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -840,6 +842,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -849,7 +852,7 @@ mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive -range=0:134217727 +range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -878,46 +881,37 @@ tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 -port=system.membus.master[6] +port=system.membus.master[5] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=0 +pci_cfg_base=805306368 pci_cfg_gen_offsets=false pci_io_base=0 system=system -[system.realview.a9scu] -type=A9SCU -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=520093696 -pio_latency=100000 -system=system -pio=system.membus.master[4] - [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268451840 +pio_addr=470024192 pio_latency=100000 system=system -pio=system.iobus.master[21] +pio=system.iobus.master[18] [system.realview.cf_ctrl] type=IdeController -BAR0=402653184 +BAR0=471465984 BAR0LegacyIO=true -BAR0Size=16 -BAR1=402653440 +BAR0Size=256 +BAR1=471466240 BAR1LegacyIO=true -BAR1Size=1 +BAR1Size=4096 BAR2=1 BAR2LegacyIO=false BAR2Size=8 @@ -987,18 +981,18 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 -disks=system.cf0 +disks= eventq_index=0 -io_shift=1 +io_shift=2 pci_bus=2 -pci_dev=7 +pci_dev=0 pci_func=0 pio_latency=30000 platform=system.realview system=system -config=system.iobus.master[8] +config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.clcd] type=Pl111 @@ -1007,8 +1001,8 @@ clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic -int_num=55 -pio_addr=268566528 +int_num=46 +pio_addr=471793664 pio_latency=10000 pixel_clock=41667 system=system @@ -1016,51 +1010,129 @@ vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] -[system.realview.dmac_fake] -type=AmbaFake -amba_id=0 +[system.realview.energy_ctrl] +type=EnergyCtrl clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler eventq_index=0 -ignore_access=false -pio_addr=268632064 +pio_addr=470286336 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[22] -[system.realview.energy_ctrl] -type=EnergyCtrl +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler +config_latency=20000 eventq_index=0 -pio_addr=268496896 -pio_latency=100000 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] pio=system.iobus.master[25] -[system.realview.flash_fake] -type=IsaFake -clk_domain=system.clk_domain +[system.realview.generic_timer] +type=GenericTimer eventq_index=0 -fake_mem=true -pio_addr=1073741824 -pio_latency=100000 -pio_size=536870912 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 +gic=system.realview.gic +int_num=29 system=system -update_data=false -warn_access= -pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain -cpu_addr=520093952 +cpu_addr=738205696 cpu_pio_delay=10000 -dist_addr=520097792 +dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 int_latency=10000 @@ -1070,38 +1142,111 @@ platform=system.realview system=system pio=system.membus.master[2] -[system.realview.gpio0_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268513280 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.gpio1_fake] -type=AmbaFake -amba_id=0 +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 clk_domain=system.clk_domain +enable_capture=true eventq_index=0 -ignore_access=false -pio_addr=268517376 -pio_latency=100000 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 system=system -pio=system.iobus.master[17] +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] -[system.realview.gpio2_fake] -type=AmbaFake -amba_id=0 +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 eventq_index=0 -ignore_access=false -pio_addr=268521472 -pio_latency=100000 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview system=system -pio=system.iobus.master[18] +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] [system.realview.kmi0] type=Pl050 @@ -1110,13 +1255,13 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=52 +int_num=44 is_mouse=false -pio_addr=268460032 +pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.kmi1] type=Pl050 @@ -1125,20 +1270,20 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=53 +int_num=45 is_mouse=true -pio_addr=268464128 +pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false -pio_addr=520101888 +pio_addr=739246080 pio_latency=100000 pio_size=4095 ret_bad_addr=false @@ -1149,7 +1294,25 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[3] +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer @@ -1158,10 +1321,10 @@ eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 -pio_addr=520095232 +pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[3] [system.realview.mmc_fake] type=AmbaFake @@ -1169,10 +1332,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268455936 +pio_addr=470089728 pio_latency=100000 system=system -pio=system.iobus.master[22] +pio=system.iobus.master[21] [system.realview.nvmem] type=SimpleMemory @@ -1184,18 +1347,30 @@ in_addr_map=true latency=30000 latency_var=0 null=false -range=2147483648:2214592511 +range=0:67108863 port=system.membus.master[1] +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 -idreg=0 -pio_addr=268435456 +idreg=35979264 +pio_addr=469827584 pio_latency=100000 -proc_id0=201326592 -proc_id1=201327138 +proc_id0=335544320 +proc_id1=335544320 system=system pio=system.iobus.master[1] @@ -1206,34 +1381,12 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=42 -pio_addr=268529664 +int_num=36 +pio_addr=471269376 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[23] - -[system.realview.sci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268492800 -pio_latency=100000 -system=system -pio=system.iobus.master[20] - -[system.realview.smc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=269357056 -pio_latency=100000 -system=system -pio=system.iobus.master[13] +pio=system.iobus.master[10] [system.realview.sp810_fake] type=AmbaFake @@ -1241,21 +1394,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true -pio_addr=268439552 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.ssp_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268488704 +pio_addr=469893120 pio_latency=100000 system=system -pio=system.iobus.master[19] +pio=system.iobus.master[16] [system.realview.timer0] type=Sp804 @@ -1265,9 +1407,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=36 -int_num1=36 -pio_addr=268505088 +int_num0=34 +int_num1=34 +pio_addr=470876160 pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1280,9 +1422,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=37 -int_num1=37 -pio_addr=268509184 +int_num0=35 +int_num1=35 +pio_addr=470941696 pio_latency=100000 system=system pio=system.iobus.master[3] @@ -1294,8 +1436,8 @@ end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=44 -pio_addr=268472320 +int_num=37 +pio_addr=470351872 pio_latency=100000 platform=system.realview system=system @@ -1308,10 +1450,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268476416 +pio_addr=470417408 pio_latency=100000 system=system -pio=system.iobus.master[10] +pio=system.iobus.master[13] [system.realview.uart2_fake] type=AmbaFake @@ -1319,10 +1461,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268480512 +pio_addr=470482944 pio_latency=100000 system=system -pio=system.iobus.master[11] +pio=system.iobus.master[14] [system.realview.uart3_fake] type=AmbaFake @@ -1330,10 +1472,54 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268484608 +pio_addr=470548480 pio_latency=100000 system=system -pio=system.iobus.master[12] +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] [system.realview.watchdog_fake] type=AmbaFake @@ -1341,10 +1527,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268500992 +pio_addr=470745088 pio_latency=100000 system=system -pio=system.iobus.master[15] +pio=system.iobus.master[17] [system.terminal] type=Terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index 056f4dd22..bd02ea892 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -1,14 +1,39 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: LCD dual screen mode not supported +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: CP14 unimplemented crn[12], opc1[5], crm[8], opc2[0] +warn: instruction 'mcr bpiall' unimplemented +warn: instruction 'mcr dcisw' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index c786d9a25..a9f72b356 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,14 +1,31 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:22:42 -gem5 started Jun 21 2014 21:27:42 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:06:55 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu.isa: ISA system set to: 0x4e2f380 0x4e2f380 -info: Using bootloader at address 0x80000000 -info: Using kernel entry physical address at 0x8000 +info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu.isa: ISA system set to: 0x5387b00 0x5387b00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80008000 +info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2525888859000 because m5_exit instruction encountered +info: Read CNTFREQ_EL0 frequency +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +Exiting @ tick 2826845674500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index c184c0913..303143490 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,137 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542157 # Number of seconds simulated -sim_ticks 2542156879500 # Number of ticks simulated -final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826846 # Number of seconds simulated +sim_ticks 2826845674500 # Number of ticks simulated +final_tick 2826845674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53387 # Simulator instruction rate (inst/s) -host_op_rate 64319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2250271387 # Simulator tick rate (ticks/s) -host_mem_usage 465820 # Number of bytes of host memory used -host_seconds 1129.71 # Real time elapsed on the host -sim_insts 60311972 # Number of instructions simulated -sim_ops 72661518 # Number of ops (including micro ops) simulated +host_inst_rate 98010 # Simulator instruction rate (inst/s) +host_op_rate 118881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2448127815 # Simulator tick rate (ticks/s) +host_mem_usage 558668 # Number of bytes of host memory used +host_seconds 1154.70 # Real time elapsed on the host +sim_insts 113172343 # Number of instructions simulated +sim_ops 137271263 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory -system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15295608 # Number of read requests accepted -system.physmem.writeReqs 812506 # Number of write requests accepted -system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue -system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955787 # Per bank write bursts -system.physmem.perBankRdBursts::1 955478 # Per bank write bursts -system.physmem.perBankRdBursts::2 953511 # Per bank write bursts -system.physmem.perBankRdBursts::3 951566 # Per bank write bursts -system.physmem.perBankRdBursts::4 958612 # Per bank write bursts -system.physmem.perBankRdBursts::5 955530 # Per bank write bursts -system.physmem.perBankRdBursts::6 953056 # Per bank write bursts -system.physmem.perBankRdBursts::7 951020 # Per bank write bursts -system.physmem.perBankRdBursts::8 956158 # Per bank write bursts -system.physmem.perBankRdBursts::9 955874 # Per bank write bursts -system.physmem.perBankRdBursts::10 952686 # Per bank write bursts -system.physmem.perBankRdBursts::11 950200 # Per bank write bursts -system.physmem.perBankRdBursts::12 956166 # Per bank write bursts -system.physmem.perBankRdBursts::13 955918 # Per bank write bursts -system.physmem.perBankRdBursts::14 953812 # Per bank write bursts -system.physmem.perBankRdBursts::15 951254 # Per bank write bursts -system.physmem.perBankWrBursts::0 6556 # Per bank write bursts -system.physmem.perBankWrBursts::1 6344 # Per bank write bursts -system.physmem.perBankWrBursts::2 6481 # Per bank write bursts -system.physmem.perBankWrBursts::3 6512 # Per bank write bursts -system.physmem.perBankWrBursts::4 6422 # Per bank write bursts -system.physmem.perBankWrBursts::5 6709 # Per bank write bursts -system.physmem.perBankWrBursts::6 6691 # Per bank write bursts -system.physmem.perBankWrBursts::7 6631 # Per bank write bursts -system.physmem.perBankWrBursts::8 6968 # Per bank write bursts -system.physmem.perBankWrBursts::9 6764 # Per bank write bursts -system.physmem.perBankWrBursts::10 6424 # Per bank write bursts -system.physmem.perBankWrBursts::11 6068 # Per bank write bursts -system.physmem.perBankWrBursts::12 7033 # Per bank write bursts -system.physmem.perBankWrBursts::13 6638 # Per bank write bursts -system.physmem.perBankWrBursts::14 6915 # Per bank write bursts -system.physmem.perBankWrBursts::15 6799 # Per bank write bursts +system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1324880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9515236 # Number of bytes read from this memory +system.physmem.bytes_read::total 10842740 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1324880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1324880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5801024 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory +system.physmem.bytes_written::total 8136884 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22946 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 149195 # Number of read requests responded to by this memory +system.physmem.num_reads::total 172182 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 90641 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 131246 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3366026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3835632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2052119 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2878432 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2052119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3372225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6714064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 172183 # Number of read requests accepted +system.physmem.writeReqs 131246 # Number of write requests accepted +system.physmem.readBursts 172183 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 131246 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11011008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 8150720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10842804 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8136884 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10992 # Per bank write bursts +system.physmem.perBankRdBursts::1 10130 # Per bank write bursts +system.physmem.perBankRdBursts::2 11200 # Per bank write bursts +system.physmem.perBankRdBursts::3 11425 # Per bank write bursts +system.physmem.perBankRdBursts::4 13122 # Per bank write bursts +system.physmem.perBankRdBursts::5 10553 # Per bank write bursts +system.physmem.perBankRdBursts::6 11175 # Per bank write bursts +system.physmem.perBankRdBursts::7 11538 # Per bank write bursts +system.physmem.perBankRdBursts::8 10354 # Per bank write bursts +system.physmem.perBankRdBursts::9 11059 # Per bank write bursts +system.physmem.perBankRdBursts::10 10499 # Per bank write bursts +system.physmem.perBankRdBursts::11 9259 # Per bank write bursts +system.physmem.perBankRdBursts::12 10183 # Per bank write bursts +system.physmem.perBankRdBursts::13 10761 # Per bank write bursts +system.physmem.perBankRdBursts::14 10049 # Per bank write bursts +system.physmem.perBankRdBursts::15 9748 # Per bank write bursts +system.physmem.perBankWrBursts::0 8312 # Per bank write bursts +system.physmem.perBankWrBursts::1 7765 # Per bank write bursts +system.physmem.perBankWrBursts::2 8704 # Per bank write bursts +system.physmem.perBankWrBursts::3 8608 # Per bank write bursts +system.physmem.perBankWrBursts::4 7611 # Per bank write bursts +system.physmem.perBankWrBursts::5 7956 # Per bank write bursts +system.physmem.perBankWrBursts::6 8259 # Per bank write bursts +system.physmem.perBankWrBursts::7 8579 # Per bank write bursts +system.physmem.perBankWrBursts::8 7842 # Per bank write bursts +system.physmem.perBankWrBursts::9 8532 # Per bank write bursts +system.physmem.perBankWrBursts::10 7844 # Per bank write bursts +system.physmem.perBankWrBursts::11 6872 # Per bank write bursts +system.physmem.perBankWrBursts::12 7611 # Per bank write bursts +system.physmem.perBankWrBursts::13 8198 # Per bank write bursts +system.physmem.perBankWrBursts::14 7543 # Per bank write bursts +system.physmem.perBankWrBursts::15 7119 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2542155562500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 2826845408500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 18 # Read request sizes (log2) -system.physmem.readPktSize::3 15138826 # Read request sizes (log2) -system.physmem.readPktSize::4 3351 # Read request sizes (log2) +system.physmem.readPktSize::2 541 # Read request sizes (log2) +system.physmem.readPktSize::3 14 # Read request sizes (log2) +system.physmem.readPktSize::4 2993 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153413 # Read request sizes (log2) +system.physmem.readPktSize::6 168635 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 58488 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1110331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 964948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 965784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1077100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 974799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1038209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2680927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2586042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3366057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 129275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 112161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 103418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 99187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 19008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126865 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,331 +174,356 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads -system.physmem.totQLat 395458190750 # Total ticks spent queuing -system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62171 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 308.209036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.794963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.700925 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23473 37.76% 37.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14721 23.68% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6339 10.20% 71.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3681 5.92% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2625 4.22% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1528 2.46% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1121 1.80% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1145 1.84% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7538 12.12% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62171 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.780822 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.317098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.824875 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.368849 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.569917 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5609 87.31% 87.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 57 0.89% 88.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 29 0.45% 88.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 222 3.46% 92.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 216 3.36% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 23 0.36% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 19 0.30% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.19% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.22% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.06% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 154 2.40% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 11 0.17% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.16% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads +system.physmem.totQLat 2068507750 # Total ticks spent queuing +system.physmem.totMemAccLat 5294389000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 860235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12022.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30772.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.02 # Data bus utilization in percentage -system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing -system.physmem.readRowHits 14271218 # Number of row buffer hits during reads -system.physmem.writeRowHits 90719 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes -system.physmem.avgGap 157818.32 # Average gap between requests -system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states -system.physmem.memoryStateTime::REF 84888180000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.06 # Average write queue length when enqueuing +system.physmem.readRowHits 142034 # Number of row buffer hits during reads +system.physmem.writeRowHits 95196 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.74 # Row buffer hit rate for writes +system.physmem.avgGap 9316332.35 # Average gap between requests +system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2694724296750 # Time in different power states +system.physmem.memoryStateTime::REF 94394560000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states +system.physmem.memoryStateTime::ACT 37726803750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3819501000 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3820982760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2084053125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2084861625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 59549568000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 59530130400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 339202080 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 347386320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 166041280080 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 166041280080 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 145728636750 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 145839613185 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1397461683000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1397364335250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1775023924035 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1775028589620 # Total energy per rank (pJ) -system.physmem.averagePower::0 698.235540 # Core power per rank (mW) -system.physmem.averagePower::1 698.237375 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16348037 # Transaction distribution -system.membus.trans_dist::ReadResp 16348037 # Transaction distribution -system.membus.trans_dist::WriteReq 763357 # Transaction distribution -system.membus.trans_dist::WriteResp 763357 # Transaction distribution -system.membus.trans_dist::Writeback 58488 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution -system.membus.trans_dist::ReadExReq 131654 # Transaction distribution -system.membus.trans_dist::ReadExResp 131654 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 216513 # Request fanout histogram +system.physmem.actEnergy::0 245851200 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 224161560 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134145000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122310375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 703053000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 638905800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 426345120 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 398915280 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184635759360 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184635759360 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 80323317855 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 79082766720 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625647965000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1626736167750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1892116436535 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1891838986845 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.338580 # Core power per rank (mW) +system.physmem.averagePower::1 669.240432 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 67851 # Transaction distribution +system.membus.trans_dist::ReadResp 67850 # Transaction distribution +system.membus.trans_dist::WriteReq 27608 # Transaction distribution +system.membus.trans_dist::WriteResp 27608 # Transaction distribution +system.membus.trans_dist::Writeback 90641 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution +system.membus.trans_dist::ReadExReq 135128 # Transaction distribution +system.membus.trans_dist::ReadExResp 135128 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 633147 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16660328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16823793 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19143089 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 205 # Total snoops (count) +system.membus.snoop_fanout::samples 300256 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 300256 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 216513 # Request fanout histogram -system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 300256 # Request fanout histogram +system.membus.reqLayer0.occupancy 94208500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.5 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1358148499 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1678211205 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38219486 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution -system.iobus.trans_dist::WriteReq 8176 # Transaction distribution -system.iobus.trans_dist::WriteResp 8176 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 30181 # Transaction distribution +system.iobus.trans_dist::ReadResp 30181 # Transaction distribution +system.iobus.trans_dist::WriteReq 59035 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326561347 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36777514 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 13200672 # Number of BP lookups -system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits +system.cpu.branchPred.lookups 46931803 # Number of BP lookups +system.cpu.branchPred.condPredicted 24038690 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232826 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29540441 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21359776 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.306896 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11753594 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33738 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -507,25 +547,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31644036 # DTB read hits -system.cpu.dtb.read_misses 39518 # DTB read misses -system.cpu.dtb.write_hits 11381434 # DTB write hits -system.cpu.dtb.write_misses 10146 # DTB write misses -system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch +system.cpu.dtb.read_hits 25464394 # DTB read hits +system.cpu.dtb.read_misses 60419 # DTB read misses +system.cpu.dtb.write_hits 19915991 # DTB write hits +system.cpu.dtb.write_misses 9380 # DTB write misses +system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31683554 # DTB read accesses -system.cpu.dtb.write_accesses 11391580 # DTB write accesses +system.cpu.dtb.perms_faults 1298 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25524813 # DTB read accesses +system.cpu.dtb.write_accesses 19925371 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 43025470 # DTB hits -system.cpu.dtb.misses 49664 # DTB misses -system.cpu.dtb.accesses 43075134 # DTB accesses +system.cpu.dtb.hits 45380385 # DTB hits +system.cpu.dtb.misses 69799 # DTB misses +system.cpu.dtb.accesses 45450184 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -547,621 +587,632 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 24158829 # ITB inst hits -system.cpu.itb.inst_misses 10513 # ITB inst misses +system.cpu.itb.inst_hits 66292387 # ITB inst hits +system.cpu.itb.inst_misses 11931 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 24169342 # ITB inst accesses -system.cpu.itb.hits 24158829 # DTB hits -system.cpu.itb.misses 10513 # DTB misses -system.cpu.itb.accesses 24169342 # DTB accesses -system.cpu.numCycles 499362415 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66304318 # ITB inst accesses +system.cpu.itb.hits 66292387 # DTB hits +system.cpu.itb.misses 11931 # DTB misses +system.cpu.itb.accesses 66304318 # DTB accesses +system.cpu.numCycles 260551438 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104869846 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184735553 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46931803 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33113370 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145618302 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6158524 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 168617 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7866 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 338980 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 503793 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66292691 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1129489 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4986 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 254586778 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.885055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.237579 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155297274 61.00% 61.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29234666 11.48% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14075849 5.53% 78.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55978989 21.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 254586778 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180125 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.709018 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78083511 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105413176 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64659521 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3829076 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2601494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422198 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486019 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157443787 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3691480 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2601494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83923016 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10014229 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74542225 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62654018 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20851796 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146804356 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 950141 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 437053 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62758 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16395 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18089126 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150489312 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678755433 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164431250 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141833425 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8655884 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2845858 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2649612 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13844659 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26410647 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21300346 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1686617 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2194239 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143538852 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2120894 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143334300 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269212 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6251138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14652316 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125305 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 254586778 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.563008 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.882453 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166323253 65.33% 65.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45116884 17.72% 83.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32035807 12.58% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10297567 4.04% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813234 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254586778 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7369685 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5632098 24.94% 57.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9582629 42.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96007549 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113996 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26193546 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21008282 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued -system.cpu.iq.rate 0.188049 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143334300 # Type of FU issued +system.cpu.iq.rate 0.550119 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22584444 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157565 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564073322 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151915928 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140220511 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35712 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165892999 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23408 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 324281 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1489992 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 534 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18266 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701073 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88010 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6363 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2601494 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 945264 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 289569 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145860692 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26410647 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21300346 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096041 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 254692 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18266 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317528 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471649 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789177 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142391856 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25792498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872750 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 176011 # number of nop insts executed -system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed -system.cpu.iew.exec_branches 10791373 # Number of branches executed -system.cpu.iew.exec_stores 11888962 # Number of stores executed -system.cpu.iew.exec_rate 0.186737 # Inst execution rate -system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back -system.cpu.iew.wb_producers 35461894 # num instructions producing a value -system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value +system.cpu.iew.exec_nop 200946 # number of nop insts executed +system.cpu.iew.exec_refs 46671293 # number of memory reference insts executed +system.cpu.iew.exec_branches 26532601 # Number of branches executed +system.cpu.iew.exec_stores 20878795 # Number of stores executed +system.cpu.iew.exec_rate 0.546502 # Inst execution rate +system.cpu.iew.wb_sent 142004641 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140231942 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63282838 # num instructions producing a value +system.cpu.iew.wb_consumers 95859178 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back +system.cpu.iew.wb_rate 0.538212 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7590534 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995589 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755058 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251652322 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.546095 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.146746 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178202586 70.81% 70.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43292722 17.20% 88.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15476092 6.15% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4357171 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6368006 2.53% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1679722 0.67% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777425 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414219 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1084379 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60462353 # Number of instructions committed -system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251652322 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113327248 # Number of instructions committed +system.cpu.commit.committedOps 137426168 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 25244590 # Number of memory references committed -system.cpu.commit.loads 13512938 # Number of loads committed -system.cpu.commit.membars 403660 # Number of memory barriers committed -system.cpu.commit.branches 10308077 # Number of branches committed -system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 64250158 # Number of committed integer instructions. -system.cpu.commit.function_calls 991634 # Number of function calls committed. +system.cpu.commit.refs 45519928 # Number of memory references committed +system.cpu.commit.loads 24920655 # Number of loads committed +system.cpu.commit.membars 814679 # Number of memory barriers committed +system.cpu.commit.branches 26048896 # Number of branches committed +system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. +system.cpu.commit.int_insts 120245785 # Number of committed integer instructions. +system.cpu.commit.function_calls 4892513 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91784658 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112993 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24920655 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20599273 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction -system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137426168 # Class of committed instruction +system.cpu.commit.bw_lim_events 1084379 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 568215140 # The number of ROB reads -system.cpu.rob.rob_writes 154414029 # The number of ROB writes -system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60311972 # Number of Instructions Simulated -system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads -system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 109116744 # number of integer regfile reads -system.cpu.int_regfile_writes 47012206 # number of integer regfile writes -system.cpu.fp_regfile_reads 8305 # number of floating regfile reads -system.cpu.fp_regfile_writes 2780 # number of floating regfile writes -system.cpu.cc_regfile_reads 320409300 # number of cc regfile reads -system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes -system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 26770 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.rob.rob_reads 373356629 # The number of ROB reads +system.cpu.rob.rob_writes 292965429 # The number of ROB writes +system.cpu.timesIdled 892862 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5964660 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393139912 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113172343 # Number of Instructions Simulated +system.cpu.committedOps 137271263 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.302254 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.302254 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434357 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434357 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155828809 # number of integer regfile reads +system.cpu.int_regfile_writes 88634133 # number of integer regfile writes +system.cpu.fp_regfile_reads 9591 # number of floating regfile reads +system.cpu.fp_regfile_writes 2716 # number of floating regfile writes +system.cpu.cc_regfile_reads 503010933 # number of cc regfile reads +system.cpu.cc_regfile_writes 53185281 # number of cc regfile writes +system.cpu.misc_regfile_reads 444154417 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521566 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 2565070 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2565005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296628 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795251 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31166 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128727 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6450401 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121302864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98352737 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46636 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219917661 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65503 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3561986 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2266210 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3525536 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36450 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2266210 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3090363565 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3561986 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2503006527 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2849563150 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2544137605 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 17681240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1334496858 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 19512240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 51517661 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74894955 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 959838 # number of replacements -system.cpu.icache.tags.tagsinuse 511.383389 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23148830 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 960350 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 24.104576 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 11339333250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.383389 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1894110 # number of replacements +system.cpu.icache.tags.tagsinuse 511.373809 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64308148 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1894622 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.942469 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.373809 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 25114544 # Number of tag accesses -system.cpu.icache.tags.data_accesses 25114544 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23148830 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23148830 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23148830 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23148830 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23148830 # number of overall hits -system.cpu.icache.overall_hits::total 23148830 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1005344 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1005344 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1005344 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1005344 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1005344 # number of overall misses -system.cpu.icache.overall_misses::total 1005344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13667748229 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13667748229 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13667748229 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13667748229 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13667748229 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13667748229 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24154174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24154174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24154174 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24154174 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24154174 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24154174 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.096036 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13595.096036 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13595.096036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13595.096036 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1628 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68184330 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68184330 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64308148 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64308148 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64308148 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64308148 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64308148 # number of overall hits +system.cpu.icache.overall_hits::total 64308148 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1981542 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1981542 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1981542 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1981542 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1981542 # number of overall misses +system.cpu.icache.overall_misses::total 1981542 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763338374 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26763338374 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26763338374 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26763338374 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26763338374 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26763338374 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66289690 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66289690 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66289690 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66289690 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66289690 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66289690 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029892 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029892 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029892 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029892 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029892 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029892 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.319005 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13506.319005 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13506.319005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13506.319005 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2089 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 118 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 104 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 13.796610 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.086538 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44974 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 44974 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 44974 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 44974 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 44974 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 44974 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960370 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 960370 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 960370 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 960370 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 960370 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 960370 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11288731510 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11288731510 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11288731510 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11288731510 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11288731510 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11288731510 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223034500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223034500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223034500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 223034500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039760 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.039760 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.039760 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11754.564918 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11754.564918 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86900 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 86900 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 86900 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 86900 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 86900 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 86900 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894642 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1894642 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1894642 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1894642 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1894642 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1894642 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22157720096 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22157720096 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22157720096 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22157720096 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22157720096 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22157720096 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202542500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202542500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202542500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 202542500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028581 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028581 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028581 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11694.937669 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11694.937669 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 63303 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51126.923594 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1828959 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 128691 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.212019 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2530750696500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37301.769799 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.815946 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7722.177507 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.159639 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.569180 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000104 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117831 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.093020 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.780135 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65381 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3025 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6220 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997635 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18315394 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18315394 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33880 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9473 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 947730 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 377075 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1368158 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 599947 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 599947 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113210 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113210 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 33880 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 9473 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 947730 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 490285 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1481368 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 33880 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 9473 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 947730 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 490285 # number of overall hits -system.cpu.l2cache.overall_hits::total 1481368 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 11652 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10148 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 21814 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2909 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133357 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133357 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 11 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 11652 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143505 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 155171 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 11 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 11652 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143505 # number of overall misses -system.cpu.l2cache.overall_misses::total 155171 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 835556749 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 759914000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1596499749 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 349485 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 349485 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9345897297 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9345897297 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 835556749 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10105811297 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10942397046 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 835556749 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10105811297 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10942397046 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33891 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9476 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 959382 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 387223 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1389972 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 599947 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 599947 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2950 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33891 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 9476 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 959382 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 633790 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1636539 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33891 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 9476 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 959382 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 633790 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1636539 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000325 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000317 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012145 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015694 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986102 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986102 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540855 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540855 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000325 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000317 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012145 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.226424 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.094817 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000325 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000317 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012145 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.226424 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.094817 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71886.363636 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79416.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71709.298747 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74883.129681 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73186.932658 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 120.139223 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 120.139223 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70081.790210 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70081.790210 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70518.312352 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70518.312352 # average overall miss latency +system.cpu.l2cache.tags.replacements 98637 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65077.786040 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3021048 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163850 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.437888 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 49563.565409 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798460 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.530935 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5190.672892 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.756280 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157326 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.079203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.993008 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65200 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2970 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7016 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55034 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 28438268 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 28438268 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53837 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11652 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1874630 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 528067 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2468186 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 695424 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 695424 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 34 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 34 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 159691 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 159691 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 53837 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 11652 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1874630 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 687758 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2627877 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 53837 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 11652 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1874630 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 687758 # number of overall hits +system.cpu.l2cache.overall_hits::total 2627877 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 19979 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 13624 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33629 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2734 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2734 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 136937 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 136937 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 19979 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 150561 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 170566 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 19979 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 150561 # number of overall misses +system.cpu.l2cache.overall_misses::total 170566 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1661750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1496766000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1081319750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2580283750 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 582975 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 582975 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46498 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9921795191 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9921795191 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1661750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1496766000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11003114941 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12502078941 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1661750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1496766000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11003114941 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12502078941 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53856 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11659 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894609 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 541691 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2501815 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 695424 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 695424 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2768 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2768 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296628 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296628 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53856 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 11659 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1894609 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 838319 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2798443 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53856 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 11659 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1894609 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 838319 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2798443 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000353 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000600 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010545 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025151 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.013442 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987717 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987717 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461646 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.461646 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000353 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000600 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010545 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.179599 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060950 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000353 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000600 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010545 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.179599 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060950 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87460.526316 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76607.142857 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74916.962811 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79368.742660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76727.935710 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.231529 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.231529 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23249 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72455.181514 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72455.181514 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73297.602928 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73297.602928 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1170,104 +1221,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58488 # number of writebacks -system.cpu.l2cache.writebacks::total 58488 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11638 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10108 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 21759 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133357 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133357 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 11638 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143465 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 155116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 11638 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143465 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 155116 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 596250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 201250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 688774749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 631278500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1320850749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29121909 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29121909 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7684221703 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7684221703 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 596250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 201250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 688774749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8315500203 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9005072452 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 596250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 201250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 688774749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8315500203 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9005072452 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174356000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167012344750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167186700750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17146783596 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17146783596 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174356000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184159128346 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184333484346 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026104 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015654 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540855 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540855 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.094783 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.094783 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59183.257347 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62453.353779 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60703.651317 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.969062 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.969062 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57621.434968 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57621.434968 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 90641 # number of writebacks +system.cpu.l2cache.writebacks::total 90641 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 19 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19954 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13512 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33492 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2734 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2734 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136937 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 136937 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 19954 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 150449 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 170429 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19954 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 150449 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 170429 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1426250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1244689750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 905485750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152053000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27405734 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27405734 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8208319809 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8208319809 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1426250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1244689750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9113805559 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10360372809 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1426250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1244689750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9113805559 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10360372809 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157860000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387400000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545260000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107351500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107351500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157860000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494751500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652611500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024944 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013387 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987717 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987717 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461646 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461646 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060901 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060901 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62377.956801 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67013.451007 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64255.732712 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.043160 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.043160 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59942.307842 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59942.307842 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1277,184 +1333,184 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 633278 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.949941 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19068568 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 633790 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.086571 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.949941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 837784 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958472 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40159350 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838296 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.905931 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 244993250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958472 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 91796938 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 91796938 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11311263 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11311263 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7209463 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7209463 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60828 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60828 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236419 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236419 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18520726 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18520726 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18581554 # number of overall hits -system.cpu.dcache.overall_hits::total 18581554 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 573243 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 573243 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3012489 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3012489 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 126499 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 126499 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 12987 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 12987 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3585732 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3585732 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3712231 # number of overall misses -system.cpu.dcache.overall_misses::total 3712231 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7223298916 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7223298916 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126143348315 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126143348315 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 177246500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 177246500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133366647231 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133366647231 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133366647231 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133366647231 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 11884506 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 11884506 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10221952 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10221952 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 187327 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 187327 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249406 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 249406 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 22106458 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22106458 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 22293785 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22293785 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048234 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.048234 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675284 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.675284 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.162203 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.162203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166514 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166514 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12600.762532 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12600.762532 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41873.463543 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41873.463543 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13647.994148 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13647.994148 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37193.701936 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37193.701936 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35926.279165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35926.279165 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17394 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 459 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1226 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.187602 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 459 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 179375223 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179375223 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23322313 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23322313 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15585229 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15585229 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346650 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346650 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441994 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441994 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460302 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460302 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38907542 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38907542 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39254192 # number of overall hits +system.cpu.dcache.overall_hits::total 39254192 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 700487 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 700487 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3573434 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3573434 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177076 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177076 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26736 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26736 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 4273921 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4273921 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4450997 # number of overall misses +system.cpu.dcache.overall_misses::total 4450997 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9902093641 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9902093641 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 135168862785 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 135168862785 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356751499 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 356751499 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145070956426 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145070956426 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145070956426 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145070956426 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24022800 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24022800 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19158663 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19158663 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523726 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523726 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468730 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468730 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460307 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460307 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43181463 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43181463 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43705189 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43705189 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029159 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029159 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186518 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186518 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.098976 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.098976 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.101841 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.101841 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14136.013432 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14136.013432 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37826.041501 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37826.041501 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13343.488143 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13343.488143 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33943.293857 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33943.293857 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.912650 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32592.912650 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 507999 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6927 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 73.336076 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 599947 # number of writebacks -system.cpu.dcache.writebacks::total 599947 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271762 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 271762 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3034890 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3034890 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3034890 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3034890 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301481 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 301481 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249361 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249361 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74144 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 74144 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11754 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11754 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 550842 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 695424 # number of writebacks +system.cpu.dcache.writebacks::total 695424 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286296 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 286296 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274169 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3274169 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3560465 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3560465 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3560465 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3560465 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414191 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414191 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299265 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299265 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8325 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8325 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 713456 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713456 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 832762 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 832762 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5344701667 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5344701667 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11882128205 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11882128205 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479845001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479845001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110272000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110272000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17226829872 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17226829872 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18706674873 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18706674873 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792653500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792653500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440471453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440471453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233124953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233124953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227802 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227802 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017761 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017761 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016522 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016522 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019054 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019054 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12903.954135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12903.954135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39704.369722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39704.369722 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.776851 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.776851 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.885886 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.885886 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.609361 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.609361 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22463.410762 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22463.410762 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1462,32 +1518,96 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.replacements 36410 # number of replacements +system.iocache.tags.tagsinuse 0.999683 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.999683 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328020 # Number of tag accesses +system.iocache.tags.data_accesses 328020 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses +system.iocache.ReadReq_misses::total 220 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses +system.iocache.demand_misses::total 220 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 220 # number of overall misses +system.iocache.overall_misses::total 220 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 26405377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 26405377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 26405377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 26405377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 26405377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 26405377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36227 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36227 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000083 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000083 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 120024.440909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120024.440909 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120024.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120024.440909 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 14964377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14964377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2231467484 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2231467484 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 14964377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14964377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 14964377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14964377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68019.895455 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68019.895455 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal Binary files differindex 69a162eed..b3be0ec54 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index 8a89971a1..b371e25ee 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename= +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 -flags_addr=268435504 -gic_cpu_addr=520093952 +flags_addr=469827632 +gic_cpu_addr=738205696 have_generic_timer=false have_large_asid_64=false have_lpae=false @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 -load_offset=0 -machine_type=RealView_PBX +load_offset=2147483648 +machine_type=VExpress_EMM mem_mode=atomic -mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -53,14 +53,14 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[0] +system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=268435456:520093695 1073741824:1610612735 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -278,6 +278,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu0.istage2_mmu] @@ -424,6 +425,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu1.istage2_mmu] @@ -948,6 +950,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu2.istage2_mmu] @@ -1019,15 +1022,16 @@ type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 -use_default_range=false +use_default_range=true width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] type=BaseCache children=tags -addr_ranges=0:134217727 +addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain eventq_index=0 @@ -1046,8 +1050,8 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[26] -mem_side=system.membus.slave[2] +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] [system.iocache.tags] type=LRU @@ -1082,7 +1086,7 @@ tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c.tags] type=LRU @@ -1105,8 +1109,8 @@ system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -1162,6 +1166,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -1171,7 +1176,7 @@ mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive -range=0:134217727 +range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1200,46 +1205,37 @@ tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 -port=system.membus.master[6] +port=system.membus.master[5] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=0 +pci_cfg_base=805306368 pci_cfg_gen_offsets=false pci_io_base=0 system=system -[system.realview.a9scu] -type=A9SCU -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=520093696 -pio_latency=100000 -system=system -pio=system.membus.master[4] - [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268451840 +pio_addr=470024192 pio_latency=100000 system=system -pio=system.iobus.master[21] +pio=system.iobus.master[18] [system.realview.cf_ctrl] type=IdeController -BAR0=402653184 +BAR0=471465984 BAR0LegacyIO=true -BAR0Size=16 -BAR1=402653440 +BAR0Size=256 +BAR1=471466240 BAR1LegacyIO=true -BAR1Size=1 +BAR1Size=4096 BAR2=1 BAR2LegacyIO=false BAR2Size=8 @@ -1309,18 +1305,18 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 -disks=system.cf0 +disks= eventq_index=0 -io_shift=1 +io_shift=2 pci_bus=2 -pci_dev=7 +pci_dev=0 pci_func=0 pio_latency=30000 platform=system.realview system=system -config=system.iobus.master[8] +config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.clcd] type=Pl111 @@ -1329,8 +1325,8 @@ clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic -int_num=55 -pio_addr=268566528 +int_num=46 +pio_addr=471793664 pio_latency=10000 pixel_clock=41667 system=system @@ -1338,51 +1334,129 @@ vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] -[system.realview.dmac_fake] -type=AmbaFake -amba_id=0 +[system.realview.energy_ctrl] +type=EnergyCtrl clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler eventq_index=0 -ignore_access=false -pio_addr=268632064 +pio_addr=470286336 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[22] -[system.realview.energy_ctrl] -type=EnergyCtrl +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler +config_latency=20000 eventq_index=0 -pio_addr=268496896 -pio_latency=100000 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] pio=system.iobus.master[25] -[system.realview.flash_fake] -type=IsaFake -clk_domain=system.clk_domain +[system.realview.generic_timer] +type=GenericTimer eventq_index=0 -fake_mem=true -pio_addr=1073741824 -pio_latency=100000 -pio_size=536870912 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 +gic=system.realview.gic +int_num=29 system=system -update_data=false -warn_access= -pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain -cpu_addr=520093952 +cpu_addr=738205696 cpu_pio_delay=10000 -dist_addr=520097792 +dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 int_latency=10000 @@ -1392,38 +1466,111 @@ platform=system.realview system=system pio=system.membus.master[2] -[system.realview.gpio0_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268513280 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.gpio1_fake] -type=AmbaFake -amba_id=0 +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 clk_domain=system.clk_domain +enable_capture=true eventq_index=0 -ignore_access=false -pio_addr=268517376 -pio_latency=100000 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 system=system -pio=system.iobus.master[17] +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] -[system.realview.gpio2_fake] -type=AmbaFake -amba_id=0 +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 eventq_index=0 -ignore_access=false -pio_addr=268521472 -pio_latency=100000 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview system=system -pio=system.iobus.master[18] +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] [system.realview.kmi0] type=Pl050 @@ -1432,13 +1579,13 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=52 +int_num=44 is_mouse=false -pio_addr=268460032 +pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.kmi1] type=Pl050 @@ -1447,20 +1594,20 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=53 +int_num=45 is_mouse=true -pio_addr=268464128 +pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false -pio_addr=520101888 +pio_addr=739246080 pio_latency=100000 pio_size=4095 ret_bad_addr=false @@ -1471,7 +1618,25 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[3] +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer @@ -1480,10 +1645,10 @@ eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 -pio_addr=520095232 +pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[3] [system.realview.mmc_fake] type=AmbaFake @@ -1491,10 +1656,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268455936 +pio_addr=470089728 pio_latency=100000 system=system -pio=system.iobus.master[22] +pio=system.iobus.master[21] [system.realview.nvmem] type=SimpleMemory @@ -1506,18 +1671,30 @@ in_addr_map=true latency=30000 latency_var=0 null=false -range=2147483648:2214592511 +range=0:67108863 port=system.membus.master[1] +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 -idreg=0 -pio_addr=268435456 +idreg=35979264 +pio_addr=469827584 pio_latency=100000 -proc_id0=201326592 -proc_id1=201327138 +proc_id0=335544320 +proc_id1=335544320 system=system pio=system.iobus.master[1] @@ -1528,34 +1705,12 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=42 -pio_addr=268529664 +int_num=36 +pio_addr=471269376 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[23] - -[system.realview.sci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268492800 -pio_latency=100000 -system=system -pio=system.iobus.master[20] - -[system.realview.smc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=269357056 -pio_latency=100000 -system=system -pio=system.iobus.master[13] +pio=system.iobus.master[10] [system.realview.sp810_fake] type=AmbaFake @@ -1563,21 +1718,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true -pio_addr=268439552 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.ssp_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268488704 +pio_addr=469893120 pio_latency=100000 system=system -pio=system.iobus.master[19] +pio=system.iobus.master[16] [system.realview.timer0] type=Sp804 @@ -1587,9 +1731,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=36 -int_num1=36 -pio_addr=268505088 +int_num0=34 +int_num1=34 +pio_addr=470876160 pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1602,9 +1746,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=37 -int_num1=37 -pio_addr=268509184 +int_num0=35 +int_num1=35 +pio_addr=470941696 pio_latency=100000 system=system pio=system.iobus.master[3] @@ -1616,8 +1760,8 @@ end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=44 -pio_addr=268472320 +int_num=37 +pio_addr=470351872 pio_latency=100000 platform=system.realview system=system @@ -1630,10 +1774,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268476416 +pio_addr=470417408 pio_latency=100000 system=system -pio=system.iobus.master[10] +pio=system.iobus.master[13] [system.realview.uart2_fake] type=AmbaFake @@ -1641,10 +1785,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268480512 +pio_addr=470482944 pio_latency=100000 system=system -pio=system.iobus.master[11] +pio=system.iobus.master[14] [system.realview.uart3_fake] type=AmbaFake @@ -1652,10 +1796,54 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268484608 +pio_addr=470548480 pio_latency=100000 system=system -pio=system.iobus.master[12] +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] [system.realview.watchdog_fake] type=AmbaFake @@ -1663,10 +1851,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268500992 +pio_addr=470745088 pio_latency=100000 system=system -pio=system.iobus.master[15] +pio=system.iobus.master[17] [system.terminal] type=Terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index 41d09e09d..40aa358a7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -1,36 +1,55 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: LCD dual screen mode not supported -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] +warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3] +warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3] +warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1] +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2] +warn: instruction 'mcr bpiall' unimplemented +warn: instruction 'mcr dcisw' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0] +warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7] warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index bb9bfcfdd..6a3bc0040 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:22:42 -gem5 started Jun 21 2014 21:27:42 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:14:55 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 - 0: system.cpu1.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 - 0: system.cpu2.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 + 0: system.cpu0.isa: ISA system set to: 0x5395b00 0x5395b00 + 0: system.cpu1.isa: ISA system set to: 0x5395b00 0x5395b00 + 0: system.cpu2.isa: ISA system set to: 0x5395b00 0x5395b00 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 8dbd1b2bc..3943053d7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.400978 # Number of seconds simulated -sim_ticks 2400977890000 # Number of ticks simulated -final_tick 2400977890000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.817969 # Number of seconds simulated +sim_ticks 2817968959500 # Number of ticks simulated +final_tick 2817968959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187249 # Simulator instruction rate (inst/s) -host_op_rate 225312 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7454963168 # Simulator tick rate (ticks/s) -host_mem_usage 414124 # Number of bytes of host memory used -host_seconds 322.06 # Real time elapsed on the host -sim_insts 60306316 # Number of instructions simulated -sim_ops 72565030 # Number of ops (including micro ops) simulated +host_inst_rate 310224 # Simulator instruction rate (inst/s) +host_op_rate 376688 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6925358539 # Simulator tick rate (ticks/s) +host_mem_usage 560716 # Number of bytes of host memory used +host_seconds 406.91 # Real time elapsed on the host +sim_insts 126231917 # Number of instructions simulated +sim_ops 153276568 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 489736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6827544 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 652900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4386464 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 79168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 799488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 187904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1451008 # Number of bytes read from this memory -system.physmem.bytes_read::total 124654688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 489736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 79168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 187904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 756808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3741376 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1144160 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159264 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1712392 # Number of bytes written to this memory -system.physmem.bytes_written::total 6757192 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13864 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 106706 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 130944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1051396 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 6080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 516160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 4232384 # Number of bytes read from this memory +system.physmem.bytes_read::total 10977672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 652900 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 130944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 516160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1300004 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5945344 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory +system.physmem.bytes_written::total 8281204 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 18655 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 69057 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1237 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 22672 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512303 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58459 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 286040 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39816 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 428098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812413 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47821795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 203974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2843651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 332984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 78261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 604340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51918299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 203974 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 78261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1558272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 476539 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66333 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 713206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2814350 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1558272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47821795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 203974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3320191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 399317 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 78261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1317546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54732649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13446786 # Number of read requests accepted -system.physmem.writeReqs 485691 # Number of write requests accepted -system.physmem.readBursts 13446786 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 485691 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860594304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 3023744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109777664 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3009384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 438423 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2870 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835534 # Per bank write bursts -system.physmem.perBankRdBursts::1 835708 # Per bank write bursts -system.physmem.perBankRdBursts::2 835573 # Per bank write bursts -system.physmem.perBankRdBursts::3 835895 # Per bank write bursts -system.physmem.perBankRdBursts::4 836820 # Per bank write bursts -system.physmem.perBankRdBursts::5 838059 # Per bank write bursts -system.physmem.perBankRdBursts::6 838590 # Per bank write bursts -system.physmem.perBankRdBursts::7 839423 # Per bank write bursts -system.physmem.perBankRdBursts::8 841113 # Per bank write bursts -system.physmem.perBankRdBursts::9 843484 # Per bank write bursts -system.physmem.perBankRdBursts::10 843775 # Per bank write bursts -system.physmem.perBankRdBursts::11 843709 # Per bank write bursts -system.physmem.perBankRdBursts::12 845212 # Per bank write bursts -system.physmem.perBankRdBursts::13 845578 # Per bank write bursts -system.physmem.perBankRdBursts::14 844651 # Per bank write bursts -system.physmem.perBankRdBursts::15 843662 # Per bank write bursts -system.physmem.perBankWrBursts::0 2614 # Per bank write bursts -system.physmem.perBankWrBursts::1 2619 # Per bank write bursts -system.physmem.perBankWrBursts::2 2845 # Per bank write bursts -system.physmem.perBankWrBursts::3 3084 # Per bank write bursts -system.physmem.perBankWrBursts::4 3522 # Per bank write bursts -system.physmem.perBankWrBursts::5 3545 # Per bank write bursts -system.physmem.perBankWrBursts::6 2950 # Per bank write bursts -system.physmem.perBankWrBursts::7 2539 # Per bank write bursts -system.physmem.perBankWrBursts::8 2638 # Per bank write bursts -system.physmem.perBankWrBursts::9 2619 # Per bank write bursts -system.physmem.perBankWrBursts::10 2391 # Per bank write bursts -system.physmem.perBankWrBursts::11 2507 # Per bank write bursts -system.physmem.perBankWrBursts::12 3740 # Per bank write bursts -system.physmem.perBankWrBursts::13 3837 # Per bank write bursts -system.physmem.perBankWrBursts::14 3267 # Per bank write bursts -system.physmem.perBankWrBursts::15 2529 # Per bank write bursts +system.physmem.num_reads::cpu1.inst 2046 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 95 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 8065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 66131 # Number of read requests responded to by this memory +system.physmem.num_reads::total 180499 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 92896 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133501 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 231692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1556605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 46468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 373104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 2158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 183167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1501927 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3895597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 231692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 46468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 183167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 461327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2109798 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 822697 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2938714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2109798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 823038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 231692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1562821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 46468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 373107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 2158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 183167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1501927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6834311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 92768 # Number of read requests accepted +system.physmem.writeReqs 67796 # Number of write requests accepted +system.physmem.readBursts 92768 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 67796 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5932800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4352 # Total number of bytes read from write queue +system.physmem.bytesWritten 4337152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5937092 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4338824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 68 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2466 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6044 # Per bank write bursts +system.physmem.perBankRdBursts::1 5813 # Per bank write bursts +system.physmem.perBankRdBursts::2 5577 # Per bank write bursts +system.physmem.perBankRdBursts::3 6085 # Per bank write bursts +system.physmem.perBankRdBursts::4 5556 # Per bank write bursts +system.physmem.perBankRdBursts::5 5466 # Per bank write bursts +system.physmem.perBankRdBursts::6 6173 # Per bank write bursts +system.physmem.perBankRdBursts::7 6793 # Per bank write bursts +system.physmem.perBankRdBursts::8 6458 # Per bank write bursts +system.physmem.perBankRdBursts::9 6393 # Per bank write bursts +system.physmem.perBankRdBursts::10 5737 # Per bank write bursts +system.physmem.perBankRdBursts::11 5119 # Per bank write bursts +system.physmem.perBankRdBursts::12 5308 # Per bank write bursts +system.physmem.perBankRdBursts::13 5463 # Per bank write bursts +system.physmem.perBankRdBursts::14 5329 # Per bank write bursts +system.physmem.perBankRdBursts::15 5386 # Per bank write bursts +system.physmem.perBankWrBursts::0 4258 # Per bank write bursts +system.physmem.perBankWrBursts::1 3939 # Per bank write bursts +system.physmem.perBankWrBursts::2 4228 # Per bank write bursts +system.physmem.perBankWrBursts::3 4685 # Per bank write bursts +system.physmem.perBankWrBursts::4 4137 # Per bank write bursts +system.physmem.perBankWrBursts::5 4140 # Per bank write bursts +system.physmem.perBankWrBursts::6 4393 # Per bank write bursts +system.physmem.perBankWrBursts::7 4905 # Per bank write bursts +system.physmem.perBankWrBursts::8 4554 # Per bank write bursts +system.physmem.perBankWrBursts::9 4640 # Per bank write bursts +system.physmem.perBankWrBursts::10 4209 # Per bank write bursts +system.physmem.perBankWrBursts::11 3550 # Per bank write bursts +system.physmem.perBankWrBursts::12 4025 # Per bank write bursts +system.physmem.perBankWrBursts::13 4273 # Per bank write bursts +system.physmem.perBankWrBursts::14 3934 # Per bank write bursts +system.physmem.perBankWrBursts::15 3898 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2398976781000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 2816402816000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 13407440 # Read request sizes (log2) +system.physmem.readPktSize::2 1 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 39346 # Read request sizes (log2) +system.physmem.readPktSize::6 92767 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 467914 # Write request sizes (log2) +system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17777 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 878947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 855123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 852879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 944479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 861163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 917283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2393694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2315582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3029092 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 97091 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 88809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 83328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 80474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 16044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 30 # What read queue length does an incoming req see +system.physmem.writePktSize::6 67794 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 61106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,505 +178,520 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 866162 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 997.062961 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 964.716097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 145.162362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8098 0.93% 0.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8963 1.03% 1.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6105 0.70% 2.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 860 0.10% 2.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 965 0.11% 2.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 764 0.09% 2.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7665 0.88% 3.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 291 0.03% 3.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 832451 96.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 866162 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 5195.817620 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 249325.060826 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 2587 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2588 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2588 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.255796 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.093626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.104963 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 2 0.08% 0.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 1 0.04% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 3 0.12% 0.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.04% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 2 0.08% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 3 0.12% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 2 0.08% 0.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 2 0.08% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 3 0.12% 0.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 555 21.45% 22.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.23% 22.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 738 28.52% 50.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1040 40.19% 91.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 103 3.98% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 50 1.93% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.54% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.43% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.50% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.19% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.27% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 6 0.23% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 5 0.19% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.23% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.15% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 5 0.19% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2588 # Writes before turning the bus around for reads -system.physmem.totQLat 347055171000 # Total ticks spent queuing -system.physmem.totMemAccLat 599182408500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67233930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25809.53 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 32855 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.580247 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.443796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.847473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12759 38.83% 38.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7721 23.50% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2992 9.11% 71.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1702 5.18% 76.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1346 4.10% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 768 2.34% 83.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 529 1.61% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 557 1.70% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4481 13.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32855 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3254 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.483712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 540.107069 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3253 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3254 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3254 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.826060 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.875262 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.591008 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 2 0.06% 0.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 2712 83.34% 83.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 41 1.26% 84.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 34 1.04% 85.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 139 4.27% 90.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 131 4.03% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 8 0.25% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 4 0.12% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.28% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 18 0.55% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.09% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.22% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.12% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 99 3.04% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.06% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.12% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.09% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.09% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.03% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.09% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.06% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.06% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.28% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3254 # Writes before turning the bus around for reads +system.physmem.totQLat 1185317250 # Total ticks spent queuing +system.physmem.totMemAccLat 2923442250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 463500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12786.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44559.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.72 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.25 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31536.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.81 # Data bus utilization in percentage -system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 2.52 # Average write queue length when enqueuing -system.physmem.readRowHits 12587076 # Number of row buffer hits during reads -system.physmem.writeRowHits 40794 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.30 # Row buffer hit rate for writes -system.physmem.avgGap 172185.95 # Average gap between requests -system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2165163855000 # Time in different power states -system.physmem.memoryStateTime::REF 80173860000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.01 # Average write queue length when enqueuing +system.physmem.readRowHits 76736 # Number of row buffer hits during reads +system.physmem.writeRowHits 50876 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes +system.physmem.avgGap 17540686.68 # Average gap between requests +system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2704844342250 # Time in different power states +system.physmem.memoryStateTime::REF 94098160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 155638381250 # Time in different power states +system.physmem.memoryStateTime::ACT 19026363250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3260847240 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3287337480 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1779232125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1793686125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 52225695600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 52659235200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 153692640 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 152461440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 156820070160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 156820070160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 104351437575 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 103839738030 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1349049300750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1349498160000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1667640276090 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1668050688435 # Total energy per rank (pJ) -system.physmem.averagePower::0 694.567634 # Core power per rank (mW) -system.physmem.averagePower::1 694.738569 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 15564561 # Transaction distribution -system.membus.trans_dist::ReadResp 15564561 # Transaction distribution -system.membus.trans_dist::WriteReq 763190 # Transaction distribution -system.membus.trans_dist::WriteResp 763190 # Transaction distribution -system.membus.trans_dist::Writeback 58459 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4572 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4572 # Transaction distribution -system.membus.trans_dist::ReadExReq 131741 # Transaction distribution -system.membus.trans_dist::ReadExResp 131741 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1895349 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4281819 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 28704768 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 28704768 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32986587 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390317 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7020 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16592808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18990169 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 114819072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 114819072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 133809241 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 216296 # Request fanout histogram +system.physmem.actEnergy::0 129865680 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 118518120 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 70859250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 64667625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 370554600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 352489800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 224758800 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 214377840 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184056000960 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184056000960 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 70810444215 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 69981019830 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1628666804250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1629394369500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1884329287755 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1884181443675 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.683537 # Core power per rank (mW) +system.physmem.averagePower::1 668.631072 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 74237 # Transaction distribution +system.membus.trans_dist::ReadResp 74236 # Transaction distribution +system.membus.trans_dist::WriteReq 27571 # Transaction distribution +system.membus.trans_dist::WriteResp 27571 # Transaction distribution +system.membus.trans_dist::Writeback 92896 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4548 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4551 # Transaction distribution +system.membus.trans_dist::ReadExReq 137042 # Transaction distribution +system.membus.trans_dist::ReadExResp 137042 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 579193 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 652020 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16939580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17102703 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19429167 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125 # Total snoops (count) +system.membus.snoop_fanout::samples 304844 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 216296 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 304844 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 216296 # Request fanout histogram -system.membus.reqLayer0.occupancy 410119000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 304844 # Request fanout histogram +system.membus.reqLayer0.occupancy 40698500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 415500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 463500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14677410500 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1676192784 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 33189927250 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.4 # Layer utilization (%) +system.membus.reqLayer5.occupancy 735391250 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 906935534 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 23918727 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63154 # number of replacements -system.l2c.tags.tagsinuse 50400.562310 # Cycle average of tags in use -system.l2c.tags.total_refs 1759923 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128542 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.691424 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2389821916000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36854.968320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000123 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4866.476746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3677.784289 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993335 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 799.149653 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 805.381857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.908524 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1731.923626 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1656.975819 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562362 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.replacements 100821 # number of replacements +system.l2c.tags.tagsinuse 65118.790978 # Cycle average of tags in use +system.l2c.tags.total_refs 2895106 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166061 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.433991 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 49797.187016 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939323 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5291.837037 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2854.503749 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969196 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1121.421966 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 949.242692 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.966166 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 3505.210474 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1537.513263 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.759845 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074257 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.056119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080747 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043556 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.012194 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012289 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000105 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.026427 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.025283 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.769052 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3042 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6071 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55876 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17767412 # Number of tag accesses -system.l2c.tags.data_accesses 17767412 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8212 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2860 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 436288 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 179343 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2016 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 871 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 118139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 58618 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 19846 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 6099 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 333250 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 135884 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1301426 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 598065 # number of Writeback hits -system.l2c.Writeback_hits::total 598065 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 9 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.017112 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.014484 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000900 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.053485 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.023461 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993634 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65193 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3115 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8083 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53656 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27447983 # Number of tag accesses +system.l2c.tags.data_accesses 27447983 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2545 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 856871 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 242835 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1453 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 744 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 248099 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 77823 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 27437 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 6484 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 674506 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 203103 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2346863 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 692569 # number of Writeback hits +system.l2c.Writeback_hits::total 692569 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 52319 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 17211 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 44017 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113547 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8212 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2860 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 436288 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 231662 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2016 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 871 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 118139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 75829 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 19846 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 6099 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 333250 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 179901 # number of demand (read+write) hits -system.l2c.demand_hits::total 1414973 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8212 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2860 # number of overall hits -system.l2c.overall_hits::cpu0.inst 436288 # number of overall hits -system.l2c.overall_hits::cpu0.data 231662 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2016 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 871 # number of overall hits -system.l2c.overall_hits::cpu1.inst 118139 # number of overall hits -system.l2c.overall_hits::cpu1.data 75829 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 19846 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 6099 # number of overall hits -system.l2c.overall_hits::cpu2.inst 333250 # number of overall hits -system.l2c.overall_hits::cpu2.data 179901 # number of overall hits -system.l2c.overall_hits::total 1414973 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7238 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6279 # number of ReadReq misses +system.l2c.UpgradeReq_hits::cpu2.data 40 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 54 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 12 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 81755 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 19470 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 56351 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 157576 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2545 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 856871 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 324590 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 1453 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 744 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 248099 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 97293 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 27437 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 6484 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 674506 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 259454 # number of demand (read+write) hits +system.l2c.demand_hits::total 2504439 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4963 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2545 # number of overall hits +system.l2c.overall_hits::cpu0.inst 856871 # number of overall hits +system.l2c.overall_hits::cpu0.data 324590 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 1453 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 744 # number of overall hits +system.l2c.overall_hits::cpu1.inst 248099 # number of overall hits +system.l2c.overall_hits::cpu1.data 97293 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 27437 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 6484 # number of overall hits +system.l2c.overall_hits::cpu2.inst 674506 # number of overall hits +system.l2c.overall_hits::cpu2.data 259454 # number of overall hits +system.l2c.overall_hits::total 2504439 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 9638 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6914 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1237 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1211 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2939 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2619 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21535 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1091 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 479 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 1337 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2907 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 101010 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 11535 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 20861 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133406 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7238 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 107289 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.inst 2046 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2575 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 95 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 8072 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 4575 # number of ReadReq misses +system.l2c.ReadReq_misses::total 33921 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1285 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 366 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 1066 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2717 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 62387 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 14112 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 62374 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 138873 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 9638 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69301 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1237 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12746 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2939 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 23480 # number of demand (read+write) misses -system.l2c.demand_misses::total 154941 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7238 # number of overall misses -system.l2c.overall_misses::cpu0.data 107289 # number of overall misses +system.l2c.demand_misses::cpu1.inst 2046 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16687 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 95 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 8072 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 66949 # number of demand (read+write) misses +system.l2c.demand_misses::total 172794 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 9638 # number of overall misses +system.l2c.overall_misses::cpu0.data 69301 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1237 # number of overall misses -system.l2c.overall_misses::cpu1.data 12746 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 8 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2939 # number of overall misses -system.l2c.overall_misses::cpu2.data 23480 # number of overall misses -system.l2c.overall_misses::total 154941 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2046 # number of overall misses +system.l2c.overall_misses::cpu1.data 16687 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 95 # number of overall misses +system.l2c.overall_misses::cpu2.inst 8072 # number of overall misses +system.l2c.overall_misses::cpu2.data 66949 # number of overall misses +system.l2c.overall_misses::total 172794 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 87455000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 91702500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 793250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 215412250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 203455994 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 598893494 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 68997 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 185992 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 254989 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 818099996 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1544671950 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2362771946 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 148548750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 192290250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7339250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 615969000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 366986496 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1331208246 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 22999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 325486 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 994399991 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 4662408726 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5656808717 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 87455000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 909802496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 793250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 215412250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1748127944 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2961665440 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 148548750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1186690241 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 7339250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 615969000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 5029395222 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6988016963 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 87455000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 909802496 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 793250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 215412250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1748127944 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2961665440 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8213 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2862 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 443526 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 185622 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2017 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 871 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 119376 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 59829 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 19854 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 6099 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 336189 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 138503 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1322961 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 598065 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 598065 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1100 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 483 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1350 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 153329 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 28746 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 64878 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246953 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8213 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2862 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 443526 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 338951 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2017 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 871 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 119376 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 88575 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 19854 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 6099 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 336189 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 203381 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1569914 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8213 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2862 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 443526 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 338951 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2017 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 871 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 119376 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 88575 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 19854 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 6099 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 336189 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 203381 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1569914 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000122 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000699 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016319 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.033827 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000496 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010362 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020241 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000403 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.008742 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.018909 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016278 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991818 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991718 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.990370 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991135 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.658779 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.401273 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.321542 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.540208 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000122 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000699 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016319 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.316532 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000496 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010362 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.143901 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000403 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.008742 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.115448 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098694 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000122 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000699 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016319 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.316532 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000496 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010362 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.143901 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000403 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.008742 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.115448 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098694 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu1.inst 148548750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1186690241 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 7339250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 615969000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 5029395222 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6988016963 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4967 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2546 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 866509 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 249749 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 1454 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 744 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 250145 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 80398 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 27532 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 6484 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 682578 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 207678 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2380784 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 692569 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 692569 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1295 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 370 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 1106 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2771 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 13 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 15 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 144142 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 33582 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 118725 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296449 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4967 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2546 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 866509 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 393891 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 1454 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 744 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 250145 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 113980 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 27532 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 6484 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 682578 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 326403 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2677233 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4967 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2546 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 866509 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 393891 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 1454 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 744 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 250145 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 113980 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 27532 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 6484 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 682578 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 326403 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2677233 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000805 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000393 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.011123 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.027684 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008179 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.032028 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003451 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.011826 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.022029 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.014248 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992278 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989189 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.963834 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.980512 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.076923 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.432816 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.420225 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.525365 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.468455 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000805 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000393 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.011123 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.175940 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008179 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.146403 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003451 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.011826 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.205111 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.064542 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000805 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000393 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.011123 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.175940 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008179 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.146403 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003451 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.011826 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.205111 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.064542 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70699.272433 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75724.607762 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 99156.250000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 73294.402858 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 77684.610157 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 27810.238867 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 144.043841 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 139.111444 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 87.715514 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70923.276636 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74045.920617 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 17711.137025 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72604.472141 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 74675.825243 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 77255.263158 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76309.340932 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 80215.627541 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 39244.369152 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 62.838798 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 305.333959 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 128.260950 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70464.851970 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74749.234072 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 40733.682696 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 70699.272433 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 71379.452063 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 99156.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 73294.402858 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 74451.786371 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 19114.794922 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 72604.472141 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71114.654581 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 77255.263158 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 76309.340932 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75122.783343 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 40441.317193 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 70699.272433 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 71379.452063 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 99156.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 73294.402858 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 74451.786371 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 19114.794922 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 72604.472141 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71114.654581 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 77255.263158 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 76309.340932 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75122.783343 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 40441.317193 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,134 +700,142 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58459 # number of writebacks -system.l2c.writebacks::total 58459 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits +system.l2c.writebacks::writebacks 92896 # number of writebacks +system.l2c.writebacks::total 92896 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.inst 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.data 44 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 44 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 44 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 50 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1237 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1211 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 8 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2936 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2611 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 8004 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 479 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 1337 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1816 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 11535 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 20861 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 32396 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 2046 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 2575 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 95 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 8066 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 4531 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 17314 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 366 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 1066 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1432 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 14112 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 62374 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 76486 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1237 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 12746 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 8 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2936 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 23472 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40400 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2046 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 16687 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 95 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 8066 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 66905 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 93800 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1237 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 12746 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 8 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2936 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 23472 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40400 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2046 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 16687 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 95 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 8066 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 66905 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 93800 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 71795000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 76590000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 694750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 178440250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 170505244 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 498087744 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4790479 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 13376836 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 18167315 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 671834504 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1285363050 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1957197554 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122695750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 160078750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 514237000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 307639996 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1110877246 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3660366 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10666566 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14326932 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 813880009 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3892439774 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4706319783 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 71795000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 748424504 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 694750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 178440250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1455868294 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 2455285298 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 122695750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 973958759 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 514237000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 4200079770 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5817197029 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 71795000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 748424504 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 694750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 178440250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1455868294 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 2455285298 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 24982050000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 25464087500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 50446137500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 975342097 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9141414000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 10116756097 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25957392097 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34605501500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 60562893597 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000496 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010362 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020241 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000403 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.008733 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018852 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.006050 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991718 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.990370 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.619161 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.401273 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.321542 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.131183 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000496 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010362 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.143901 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000403 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.008733 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.115409 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.025734 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000496 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010362 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.143901 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000403 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.008733 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.115409 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.025734 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 122695750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 973958759 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 514237000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 4200079770 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5817197029 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 943995500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1580248500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 2524244000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 723617500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1233115000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1956732500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1667613000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2813363500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4480976500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.032028 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021817 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.007272 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989189 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.963834 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.516781 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.076923 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.066667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420225 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.525365 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.258007 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.146403 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.035036 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.146403 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035036 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63245.251858 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65302.659517 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62229.853073 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62166.504854 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67896.710660 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64160.635671 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10005.112939 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.028084 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58243.129952 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61615.600882 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60414.790530 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.159475 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.840782 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57672.903132 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62404.844551 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61531.780757 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58718.382551 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62025.745314 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 60774.388564 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58718.382551 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62025.745314 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60774.388564 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -823,167 +846,184 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2539315 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2539315 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763190 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763190 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 598065 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246953 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246953 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1813392 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5760169 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 30385 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 80672 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7684618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 57608092 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84067517 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 138604 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 141862677 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 18229 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2196613 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 2443721 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2443718 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 692569 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 22776 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2771 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296449 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296449 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3616609 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484136 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29317 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88397 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6218459 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115187260 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97908723 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49396 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 156136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213301515 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 51755 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3431770 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.010631 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.102558 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 2196613 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3395286 98.94% 98.94% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36484 1.06% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2196613 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2287106157 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3431770 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2368040184 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2054352798 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 553500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 4200557665 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1912625851 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2014921824 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13149443 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11880425 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 33486737 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 39622630 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 15535704 # Transaction distribution -system.iobus.trans_dist::ReadResp 15535704 # Transaction distribution -system.iobus.trans_dist::WriteReq 8154 # Transaction distribution -system.iobus.trans_dist::WriteResp 8154 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 492 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1000 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 30188 # Transaction distribution +system.iobus.trans_dist::ReadResp 30188 # Transaction distribution +system.iobus.trans_dist::WriteReq 59010 # Transaction distribution +system.iobus.trans_dist::WriteResp 45563 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 9 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 13456 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 28704768 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 28704768 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 31087716 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39305 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 984 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2000 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2390317 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 114819072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 114819072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 117209389 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 8534000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1569000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 352708000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 2719000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 13407440000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 717460000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 205242577 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 39802000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33785464750 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) +system.iobus.respLayer3.occupancy 23020273 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1007,25 +1047,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6552093 # DTB read hits -system.cpu0.dtb.read_misses 5443 # DTB read misses -system.cpu0.dtb.write_hits 6067983 # DTB write hits -system.cpu0.dtb.write_misses 1816 # DTB write misses -system.cpu0.dtb.flush_tlb 554 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 496 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5219 # Number of entries that have been flushed from TLB +system.cpu0.dtb.read_hits 14476225 # DTB read hits +system.cpu0.dtb.read_misses 4878 # DTB read misses +system.cpu0.dtb.write_hits 11074159 # DTB write hits +system.cpu0.dtb.write_misses 931 # DTB write misses +system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 3272 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 108 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 947 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 162 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6557536 # DTB read accesses -system.cpu0.dtb.write_accesses 6069799 # DTB write accesses +system.cpu0.dtb.perms_faults 215 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14481103 # DTB read accesses +system.cpu0.dtb.write_accesses 11075090 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12620076 # DTB hits -system.cpu0.dtb.misses 7259 # DTB misses -system.cpu0.dtb.accesses 12627335 # DTB accesses +system.cpu0.dtb.hits 25550384 # DTB hits +system.cpu0.dtb.misses 5809 # DTB misses +system.cpu0.dtb.accesses 25556193 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1047,486 +1087,503 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30154576 # ITB inst hits -system.cpu0.itb.inst_misses 2994 # ITB inst misses +system.cpu0.itb.inst_hits 67954631 # ITB inst hits +system.cpu0.itb.inst_misses 2810 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 554 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 496 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2367 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2005 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30157570 # ITB inst accesses -system.cpu0.itb.hits 30154576 # DTB hits -system.cpu0.itb.misses 2994 # DTB misses -system.cpu0.itb.accesses 30157570 # DTB accesses -system.cpu0.numCycles 109411317 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 67957441 # ITB inst accesses +system.cpu0.itb.hits 67954631 # DTB hits +system.cpu0.itb.misses 2810 # DTB misses +system.cpu0.itb.accesses 67957441 # DTB accesses +system.cpu0.numCycles 82556870 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29741333 # Number of instructions committed -system.cpu0.committedOps 36475405 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 32123717 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4289 # Number of float alu accesses -system.cpu0.num_func_calls 1120042 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3813280 # number of instructions that are conditional controls -system.cpu0.num_int_insts 32123717 # number of integer instructions -system.cpu0.num_fp_insts 4289 # number of float instructions -system.cpu0.num_int_register_reads 59486063 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21170898 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3327 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 964 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 109224829 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 14221647 # number of times the CC registers were written -system.cpu0.num_mem_refs 13081203 # number of memory refs -system.cpu0.num_load_insts 6727170 # Number of load instructions -system.cpu0.num_store_insts 6354033 # Number of store instructions -system.cpu0.num_idle_cycles 107121976.742744 # Number of idle cycles -system.cpu0.num_busy_cycles 2289340.257256 # Number of busy cycles -system.cpu0.not_idle_fraction 0.020924 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.979076 # Percentage of idle cycles -system.cpu0.Branches 5305474 # Number of branches fetched -system.cpu0.op_class::No_OpClass 11839 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 23401650 64.04% 64.07% # Class of executed instruction -system.cpu0.op_class::IntMult 45463 0.12% 64.20% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1432 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::MemRead 6727170 18.41% 82.61% # Class of executed instruction -system.cpu0.op_class::MemWrite 6354033 17.39% 100.00% # Class of executed instruction +system.cpu0.committedInsts 66160123 # Number of instructions committed +system.cpu0.committedOps 80652277 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 70891568 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5582 # Number of float alu accesses +system.cpu0.num_func_calls 7292026 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 8778447 # number of instructions that are conditional controls +system.cpu0.num_int_insts 70891568 # number of integer instructions +system.cpu0.num_fp_insts 5582 # number of float instructions +system.cpu0.num_int_register_reads 131506227 # number of times the integer registers were read +system.cpu0.num_int_register_writes 49334420 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4358 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 245867738 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 29383073 # number of times the CC registers were written +system.cpu0.num_mem_refs 26220754 # number of memory refs +system.cpu0.num_load_insts 14652166 # Number of load instructions +system.cpu0.num_store_insts 11568588 # Number of store instructions +system.cpu0.num_idle_cycles 77950731.061702 # Number of idle cycles +system.cpu0.num_busy_cycles 4606138.938298 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055794 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944206 # Percentage of idle cycles +system.cpu0.Branches 16465385 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 55784741 67.97% 67.97% # Class of executed instruction +system.cpu0.op_class::IntMult 58719 0.07% 68.05% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4540 0.01% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::MemRead 14652166 17.85% 85.90% # Class of executed instruction +system.cpu0.op_class::MemWrite 11568588 14.10% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 36541587 # Class of executed instruction +system.cpu0.op_class::total 82070947 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82908 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 899905 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.617888 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41210869 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 900417 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.768648 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7755633000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.394938 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.639138 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.583812 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967568 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.011014 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020672 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999254 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43039595 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43039595 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29712798 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7804770 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3693301 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41210869 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29712798 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7804770 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3693301 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41210869 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29712798 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7804770 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3693301 # number of overall hits -system.cpu0.icache.overall_hits::total 41210869 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 444147 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 119626 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 364535 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 928308 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 444147 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 119626 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 364535 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 928308 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 444147 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 119626 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 364535 # number of overall misses -system.cpu0.icache.overall_misses::total 928308 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1633550000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4883016924 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6516566924 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1633550000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4883016924 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6516566924 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1633550000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4883016924 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6516566924 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30156945 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7924396 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4057836 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42139177 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30156945 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7924396 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4057836 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42139177 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30156945 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7924396 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4057836 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42139177 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014728 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015096 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.089835 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022030 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014728 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015096 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089835 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022030 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014728 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015096 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089835 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022030 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13655.476234 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13395.193669 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7019.832775 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13655.476234 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13395.193669 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7019.832775 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13655.476234 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13395.193669 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7019.832775 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3227 # number of cycles access was blocked +system.cpu0.kern.inst.quiesce 3056 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 1798781 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.545341 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 100889008 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1799292 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 56.071504 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10926866250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.678395 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.508688 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.358258 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.932966 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.042009 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.024137 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999112 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 104537930 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 104537930 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 67090157 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 21677955 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 12120896 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 100889008 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 67090157 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 21677955 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 12120896 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 100889008 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 67090157 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 21677955 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 12120896 # number of overall hits +system.cpu0.icache.overall_hits::total 100889008 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 866515 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 250147 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 732935 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1849597 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 866515 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 250147 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 732935 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1849597 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 866515 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 250147 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 732935 # number of overall misses +system.cpu0.icache.overall_misses::total 1849597 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3389079250 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10061046680 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13450125930 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 3389079250 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 10061046680 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13450125930 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 3389079250 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 10061046680 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13450125930 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 67956672 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 21928102 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 12853831 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 102738605 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 67956672 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 21928102 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 12853831 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 102738605 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 67956672 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 21928102 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 12853831 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 102738605 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012751 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011408 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057021 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.018003 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012751 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011408 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057021 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.018003 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012751 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011408 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057021 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.018003 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13548.350570 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13727.065401 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7271.922440 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13548.350570 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13727.065401 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7271.922440 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13548.350570 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13727.065401 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7271.922440 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5408 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 341 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.896552 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.859238 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 27890 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 27890 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 27890 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 27890 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 27890 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 27890 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 119626 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 336645 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 456271 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 119626 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 336645 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 456271 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 119626 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 336645 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 456271 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1393831000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3968205684 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5362036684 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1393831000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3968205684 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5362036684 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1393831000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3968205684 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5362036684 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015096 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.082962 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010828 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015096 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.082962 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010828 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015096 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.082962 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010828 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11651.572401 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11787.508158 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11751.868263 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11651.572401 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11787.508158 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11751.868263 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11651.572401 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11787.508158 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11751.868263 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50271 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 50271 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 50271 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 50271 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 50271 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 50271 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 250147 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 682664 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 932811 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 250147 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 682664 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 932811 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 250147 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 682664 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 932811 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2888042750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8209155812 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11097198562 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2888042750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8209155812 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11097198562 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2888042750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8209155812 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11097198562 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009079 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009079 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009079 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11896.513401 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11896.513401 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11896.513401 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 630395 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997117 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21342587 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630907 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.828420 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.646695 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 7.878290 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.472132 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971966 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015387 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012641 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 833731 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996800 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 47004235 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 834243 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.343577 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.853552 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.631337 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.511911 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948933 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032483 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018578 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 92223227 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 92223227 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5368302 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1446025 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4735634 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11549961 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5498373 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1267433 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2446281 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9212087 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 53662 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 14249 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 23655 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 91566 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 122592 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 31381 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 84607 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238580 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 128647 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 32825 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 85920 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247392 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10866675 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 2713458 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7181915 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 20762048 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10920337 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 2727707 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7205570 # number of overall hits -system.cpu0.dcache.overall_hits::total 20853614 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 142563 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 45260 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 257630 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 445453 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 154429 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29884 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 820485 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1004798 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 37003 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 17467 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 41789 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 96259 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6056 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1445 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 4483 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11984 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 296992 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 75144 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1078115 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1450251 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 333995 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 92611 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1119904 # number of overall misses -system.cpu0.dcache.overall_misses::total 1546510 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 611214249 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3612191655 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4223405904 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1124082233 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 26974160361 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 28098242594 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 19515250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 65554993 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 85070243 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1735296482 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 30586352016 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 32321648498 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1735296482 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 30586352016 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32321648498 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5510865 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1491285 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4993264 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 11995414 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5652802 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1297317 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3266766 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216885 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 90665 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 31716 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 65444 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 187825 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 128648 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 32826 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 89090 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250564 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 128647 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 32825 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 85920 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247392 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11163667 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2788602 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 8260030 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 22212299 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11254332 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2820318 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8325474 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 22400124 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025869 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030350 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.051596 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037135 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027319 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023035 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.251161 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.098347 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.408129 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.550731 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.638546 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.512493 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047074 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044020 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050320 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047828 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026603 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026947 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.130522 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.065290 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029677 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032837 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.134515 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.069040 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13504.512793 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14020.850270 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9481.148188 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37614.851861 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32875.872638 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 27964.070981 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13505.363322 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14623.018737 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7098.651786 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23092.947967 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28370.212840 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22286.934122 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18737.476995 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27311.583864 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 20899.734562 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 35984 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 7309 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 5054 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 190 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.119905 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 38.468421 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 198572858 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 198572858 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 13788624 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 4405133 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 8515109 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 26708866 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10680775 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3155078 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 5164116 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18999969 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190600 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60611 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130493 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 381704 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235254 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80501 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 135396 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 451151 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236603 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 83020 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140074 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459697 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 24469399 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 7560211 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 13679225 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 45708835 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 24659999 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 7620822 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 13809718 # number of overall hits +system.cpu0.dcache.overall_hits::total 46090539 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 190274 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 59406 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 316505 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 566185 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 145437 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 33952 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 1529558 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1708947 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 55030 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 20141 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 65518 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 140689 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4445 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3284 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9694 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 17423 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 13 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 335711 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 93358 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1846063 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2275132 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 390741 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 113499 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1911581 # number of overall misses +system.cpu0.dcache.overall_misses::total 2415821 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 905009250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 5267719081 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6172728331 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1312526367 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70730774620 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 72043300987 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 46439000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 132211248 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 178650248 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 181001 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 181001 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 2217535617 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 75998493701 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 78216029318 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 2217535617 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 75998493701 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 78216029318 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 13978898 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 4464539 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 8831614 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 27275051 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 10826212 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 3189030 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 6693674 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 20708916 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 245630 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 80752 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 196011 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 522393 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239699 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83785 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 145090 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 468574 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236605 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 83020 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 140087 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 459712 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 24805110 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 7653569 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 15525288 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 47983967 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 25050740 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 7734321 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 15721299 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 48506360 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013612 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013306 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035838 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020758 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013434 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.010646 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228508 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.082522 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224036 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.249418 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.334257 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269316 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018544 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039196 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066814 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037183 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000093 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000033 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013534 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012198 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118907 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.047414 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015598 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014675 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.121592 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.049804 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15234.307141 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16643.399254 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10902.316965 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38658.293090 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46242.623438 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42156.544929 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14140.986602 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13638.461729 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10253.701888 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13923.153846 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12066.733333 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23753.032595 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41167.876557 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34378.677509 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19537.930880 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39756.878574 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32376.583082 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 377833 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 25059 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 25141 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 516 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.028559 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 48.563953 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 598065 # number of writebacks -system.cpu0.dcache.writebacks::total 598065 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 80 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146918 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 146998 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 655 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 754285 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 754940 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 469 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 469 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 735 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 901203 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 901938 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 735 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 901203 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 901938 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 45180 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 110712 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 155892 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29229 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 66200 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 95429 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 13204 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 23805 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 37009 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1445 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 4014 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5459 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 74409 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 176912 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 251321 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 87613 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 200717 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 288330 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 520028500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1350346488 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1870374988 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1032772017 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2131682211 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3164454228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 203990750 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 439543502 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 643534252 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 16622750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 51408007 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68030757 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1552800517 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3482028699 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5034829216 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1756791267 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3921572201 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5678363468 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27292544500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 27798821000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55091365500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1484661903 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14572262972 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 16056924875 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28777206403 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42371083972 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71148290375 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030296 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.022172 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.012996 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.022530 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.020265 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009340 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.416320 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.363746 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.197040 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044020 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045056 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.021787 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026683 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.021418 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011314 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031065 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024109 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.012872 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11510.148296 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12196.929764 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11997.889488 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35333.812891 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32200.637628 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33160.299574 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15449.163132 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18464.335308 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17388.587965 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11503.633218 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12807.176632 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12462.128045 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20868.450282 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19682.264058 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20033.460061 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20051.719117 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19537.817928 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19693.973808 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 692569 # number of writebacks +system.cpu0.dcache.writebacks::total 692569 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 109 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 155609 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 155718 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1409743 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1409743 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1933 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6811 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8744 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 109 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 1565352 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1565461 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 109 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 1565352 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1565461 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 59297 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 160896 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 220193 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 33952 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 119815 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 153767 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19750 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 43915 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 63665 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1351 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2883 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4234 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 13 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 93249 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 280711 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 373960 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 112999 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 324626 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 437625 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 783780250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2132755212 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2916535462 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238573617 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5438601702 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6677175319 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 253255500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 658822506 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 912078006 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 21611000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 35809251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57420251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 154999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 154999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022353867 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7571356914 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9593710781 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2275609367 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8230179420 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10505788787 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1019366000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1693120500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2712486500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 777844500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1314970500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092815000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1797210500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3008091000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4805301500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013282 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018218 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008073 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010646 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017900 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007425 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244576 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224044 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121872 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016125 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019870 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.009036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000093 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012184 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018081 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.007793 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014610 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020649 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.009022 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13217.873586 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13255.489335 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13245.359580 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36480.137164 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45391.659659 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43423.981212 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12823.063291 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15002.220335 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14326.207587 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15996.299038 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12420.829344 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13561.703118 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11923 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21687.673509 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26972.070614 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25654.376888 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20138.314206 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25352.804212 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24006.372550 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1560,25 +1617,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 1733555 # DTB read hits -system.cpu1.dtb.read_misses 1889 # DTB read misses -system.cpu1.dtb.write_hits 1370998 # DTB write hits -system.cpu1.dtb.write_misses 367 # DTB write misses -system.cpu1.dtb.flush_tlb 552 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 248 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1592 # Number of entries that have been flushed from TLB +system.cpu1.dtb.read_hits 4634872 # DTB read hits +system.cpu1.dtb.read_misses 1584 # DTB read misses +system.cpu1.dtb.write_hits 3276619 # DTB write hits +system.cpu1.dtb.write_misses 228 # DTB write misses +system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1208 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 28 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 77 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 1735444 # DTB read accesses -system.cpu1.dtb.write_accesses 1371365 # DTB write accesses +system.cpu1.dtb.perms_faults 51 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4636456 # DTB read accesses +system.cpu1.dtb.write_accesses 3276847 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3104553 # DTB hits -system.cpu1.dtb.misses 2256 # DTB misses -system.cpu1.dtb.accesses 3106809 # DTB accesses +system.cpu1.dtb.hits 7911491 # DTB hits +system.cpu1.dtb.misses 1812 # DTB misses +system.cpu1.dtb.accesses 7913303 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1600,98 +1657,98 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7924396 # ITB inst hits -system.cpu1.itb.inst_misses 1030 # ITB inst misses +system.cpu1.itb.inst_hits 21928102 # ITB inst hits +system.cpu1.itb.inst_misses 848 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 552 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 248 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 806 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 700 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7925426 # ITB inst accesses -system.cpu1.itb.hits 7924396 # DTB hits -system.cpu1.itb.misses 1030 # DTB misses -system.cpu1.itb.accesses 7925426 # DTB accesses -system.cpu1.numCycles 582686408 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 21928950 # ITB inst accesses +system.cpu1.itb.hits 21928102 # DTB hits +system.cpu1.itb.misses 848 # DTB misses +system.cpu1.itb.accesses 21928950 # DTB accesses +system.cpu1.numCycles 158012618 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7745878 # Number of instructions committed -system.cpu1.committedOps 9129746 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 8166989 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1689 # Number of float alu accesses -system.cpu1.num_func_calls 287006 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 983778 # number of instructions that are conditional controls -system.cpu1.num_int_insts 8166989 # number of integer instructions -system.cpu1.num_fp_insts 1689 # number of float instructions -system.cpu1.num_int_register_reads 14466592 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5466665 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1177 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 512 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 32997995 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 3759402 # number of times the CC registers were written -system.cpu1.num_mem_refs 3229777 # number of memory refs -system.cpu1.num_load_insts 1791377 # Number of load instructions -system.cpu1.num_store_insts 1438400 # Number of store instructions -system.cpu1.num_idle_cycles 548052403.807954 # Number of idle cycles -system.cpu1.num_busy_cycles 34634004.192046 # Number of busy cycles -system.cpu1.not_idle_fraction 0.059438 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.940562 # Percentage of idle cycles -system.cpu1.Branches 1348409 # Number of branches fetched -system.cpu1.op_class::No_OpClass 4600 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 6037827 65.04% 65.09% # Class of executed instruction -system.cpu1.op_class::IntMult 10088 0.11% 65.20% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 273 0.00% 65.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.21% # Class of executed instruction -system.cpu1.op_class::MemRead 1791377 19.30% 84.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 1438400 15.50% 100.00% # Class of executed instruction +system.cpu1.committedInsts 21219740 # Number of instructions committed +system.cpu1.committedOps 25418010 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22602371 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1626 # Number of float alu accesses +system.cpu1.num_func_calls 2405283 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2700826 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22602371 # number of integer instructions +system.cpu1.num_fp_insts 1626 # number of float instructions +system.cpu1.num_int_register_reads 41665137 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15857681 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1178 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 92378686 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9370916 # number of times the CC registers were written +system.cpu1.num_mem_refs 8126078 # number of memory refs +system.cpu1.num_load_insts 4682102 # Number of load instructions +system.cpu1.num_store_insts 3443976 # Number of store instructions +system.cpu1.num_idle_cycles 151526719.153884 # Number of idle cycles +system.cpu1.num_busy_cycles 6485898.846116 # Number of busy cycles +system.cpu1.not_idle_fraction 0.041047 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.958953 # Percentage of idle cycles +system.cpu1.Branches 5257577 # Number of branches fetched +system.cpu1.op_class::No_OpClass 36 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 17988056 68.83% 68.83% # Class of executed instruction +system.cpu1.op_class::IntMult 19009 0.07% 68.90% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1153 0.00% 68.91% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.91% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.91% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.91% # Class of executed instruction +system.cpu1.op_class::MemRead 4682102 17.92% 86.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 3443976 13.18% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 9282565 # Class of executed instruction +system.cpu1.op_class::total 26134332 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 5846326 # Number of BP lookups -system.cpu2.branchPred.condPredicted 4388844 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 249586 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3633950 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2855743 # Number of BTB hits +system.cpu2.branchPred.lookups 17411527 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9465637 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 400782 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 10870560 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 8144126 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 78.585093 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 589622 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15464 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 74.919103 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4071344 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21284 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1715,25 +1772,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 13911313 # DTB read hits -system.cpu2.dtb.read_misses 27890 # DTB read misses -system.cpu2.dtb.write_hits 3983127 # DTB write hits -system.cpu2.dtb.write_misses 9793 # DTB write misses -system.cpu2.dtb.flush_tlb 550 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2737 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 484 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch +system.cpu2.dtb.read_hits 9691496 # DTB read hits +system.cpu2.dtb.read_misses 37543 # DTB read misses +system.cpu2.dtb.write_hits 7160478 # DTB write hits +system.cpu2.dtb.write_misses 5658 # DTB write misses +system.cpu2.dtb.flush_tlb 181 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 2438 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 958 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 13939203 # DTB read accesses -system.cpu2.dtb.write_accesses 3992920 # DTB write accesses +system.cpu2.dtb.perms_faults 432 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 9729039 # DTB read accesses +system.cpu2.dtb.write_accesses 7166136 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 17894440 # DTB hits -system.cpu2.dtb.misses 37683 # DTB misses -system.cpu2.dtb.accesses 17932123 # DTB accesses +system.cpu2.dtb.hits 16851974 # DTB hits +system.cpu2.dtb.misses 43201 # DTB misses +system.cpu2.dtb.accesses 16895175 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1755,353 +1812,417 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4060759 # ITB inst hits -system.cpu2.itb.inst_misses 6577 # ITB inst misses +system.cpu2.itb.inst_hits 12855360 # ITB inst hits +system.cpu2.itb.inst_misses 6344 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 550 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 2055 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb 181 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 1760 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 2376 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1117 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4067336 # ITB inst accesses -system.cpu2.itb.hits 4060759 # DTB hits -system.cpu2.itb.misses 6577 # DTB misses -system.cpu2.itb.accesses 4067336 # DTB accesses -system.cpu2.numCycles 88050542 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 12861704 # ITB inst accesses +system.cpu2.itb.hits 12855360 # DTB hits +system.cpu2.itb.misses 6344 # DTB misses +system.cpu2.itb.accesses 12861704 # DTB accesses +system.cpu2.numCycles 69831868 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10519234 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32939379 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 5846326 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 3445365 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 74770225 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 681136 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 80231 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 505 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 954 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 72091 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 1265694 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 337 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4057838 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 153485 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2814 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 87049769 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 0.444404 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 1.631683 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 26744179 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 69131561 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 17411527 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12215470 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 39628211 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2071717 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 92420 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 271 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 329715 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 101746 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 12853833 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 270796 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2796 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 67933721 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.223102 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.347801 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 79735168 91.60% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 627849 0.72% 92.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 697488 0.80% 93.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 764418 0.88% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 855506 0.98% 94.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 578096 0.66% 95.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 986877 1.13% 96.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 299514 0.34% 97.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2504853 2.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49353657 72.65% 72.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 2396253 3.53% 76.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 1562027 2.30% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4874890 7.18% 85.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1103608 1.62% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 705498 1.04% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 3873607 5.70% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 752096 1.11% 95.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3312085 4.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 87049769 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.066397 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.374096 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8593092 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 72401111 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 4830102 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 941679 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 282689 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 738219 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 58888 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34839136 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 197306 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 282689 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9053752 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 19270728 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13147343 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5254066 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 40040151 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33787886 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 74120 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 29496747 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 37523489 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1004110 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 36611560 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 154353600 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41662755 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4122 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 28819307 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 7792237 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 344984 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 287406 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 5085187 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6095255 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 4404078 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 715172 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1132058 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32032092 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 661150 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 38610720 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 45237 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 5536917 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12037471 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 230168 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 87049769 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.443548 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.240485 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 67933721 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.249335 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.989972 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 18652988 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36886196 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 10385899 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1080677 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 927745 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 1311847 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 109670 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 59354899 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 355527 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 927745 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 19278335 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4338170 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 27085326 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 10827974 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5475942 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 56886251 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2445 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 940623 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 160571 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 3871890 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 58826776 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 261240527 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 63795075 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4266 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 48699577 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10127183 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 954335 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 890664 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 6273875 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 10281967 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 7932177 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 1385446 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1932065 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 54651944 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 672234 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 52014227 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 68047 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7311472 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18464419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 69301 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 67933721 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.765661 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.467889 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73601742 84.55% 84.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 4103417 4.71% 89.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2329810 2.68% 91.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2044829 2.35% 94.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2965004 3.41% 97.70% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 800473 0.92% 98.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 744836 0.86% 99.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 295465 0.34% 99.81% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 164193 0.19% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 47467313 69.87% 69.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6842474 10.07% 79.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 5093799 7.50% 87.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4189990 6.17% 93.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1618046 2.38% 95.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1073354 1.58% 97.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1126537 1.66% 99.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 361655 0.53% 99.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 160553 0.24% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 87049769 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 67933721 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 123164 5.43% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 2 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1963174 86.51% 91.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 182867 8.06% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 78426 9.72% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 375416 46.53% 56.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 353014 43.75% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 12079 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 20212271 52.35% 52.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 34343 0.09% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 410 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.47% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 14161220 36.68% 89.15% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 4190397 10.85% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 108 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 34458488 66.25% 66.25% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 39234 0.08% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 2870 0.01% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 9974787 19.18% 85.51% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 7538730 14.49% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 38610720 # Type of FU issued -system.cpu2.iq.rate 0.438506 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2269207 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.058771 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 166576049 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 38242231 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29605417 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9604 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 5150 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 4304 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 40862730 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5118 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 177793 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 52014227 # Type of FU issued +system.cpu2.iq.rate 0.744849 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 806857 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.015512 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 172827620 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 62668492 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 50413992 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9459 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4970 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4171 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 52815881 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5095 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 266821 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1108149 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 17977 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 469749 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1614154 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1912 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 38579 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 795080 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5186465 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 3515984 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 131168 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 122536 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 282689 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 17818885 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 827114 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32812972 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 58820 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6095255 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 4404078 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 482366 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 63304 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 726253 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 17977 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 122015 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 106758 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 228773 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 38292590 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 14036165 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 280577 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 927745 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3243473 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 928988 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 55431586 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 93653 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 10281967 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 7932177 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 359829 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 34343 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 885724 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 38579 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 184691 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 163240 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 347931 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 51578613 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 9798052 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 392517 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 119730 # number of nop insts executed -system.cpu2.iew.exec_refs 18176329 # number of memory reference insts executed -system.cpu2.iew.exec_branches 4221740 # Number of branches executed -system.cpu2.iew.exec_stores 4140164 # Number of stores executed -system.cpu2.iew.exec_rate 0.434893 # Inst execution rate -system.cpu2.iew.wb_sent 34848706 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29609721 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17270580 # num instructions producing a value -system.cpu2.iew.wb_consumers 30711387 # num instructions consuming a value +system.cpu2.iew.exec_nop 107408 # number of nop insts executed +system.cpu2.iew.exec_refs 17263080 # number of memory reference insts executed +system.cpu2.iew.exec_branches 9489180 # Number of branches executed +system.cpu2.iew.exec_stores 7465028 # Number of stores executed +system.cpu2.iew.exec_rate 0.738611 # Inst execution rate +system.cpu2.iew.wb_sent 51120326 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 50418163 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 26486298 # num instructions producing a value +system.cpu2.iew.wb_consumers 46021805 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.336281 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.562351 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.721994 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575516 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 5477647 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 430982 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 191637 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 86152512 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.313795 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.238508 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8152826 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 602933 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 292644 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 66207639 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.713967 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.618930 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 77159399 89.56% 89.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4186602 4.86% 94.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1295333 1.50% 95.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 754876 0.88% 96.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 491618 0.57% 97.37% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 381305 0.44% 97.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 375733 0.44% 98.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 196216 0.23% 98.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1311430 1.52% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 48127363 72.69% 72.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 8089014 12.22% 84.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 3990999 6.03% 90.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 1725382 2.61% 93.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 875466 1.32% 94.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 621285 0.94% 95.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 1255109 1.90% 97.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 300211 0.45% 98.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1222810 1.85% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 86152512 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 22893469 # Number of instructions committed -system.cpu2.commit.committedOps 27034243 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 66207639 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 38915831 # Number of instructions committed +system.cpu2.commit.committedOps 47270058 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8921435 # Number of memory references committed -system.cpu2.commit.loads 4987106 # Number of loads committed -system.cpu2.commit.membars 117312 # Number of memory barriers committed -system.cpu2.commit.branches 3648396 # Number of branches committed -system.cpu2.commit.fp_insts 4270 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 23927319 # Number of committed integer instructions. -system.cpu2.commit.function_calls 341825 # Number of function calls committed. +system.cpu2.commit.refs 15804910 # Number of memory references committed +system.cpu2.commit.loads 8667813 # Number of loads committed +system.cpu2.commit.membars 226604 # Number of memory barriers committed +system.cpu2.commit.branches 8912074 # Number of branches committed +system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 41368724 # Number of committed integer instructions. +system.cpu2.commit.function_calls 1635579 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 18080099 66.88% 66.88% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 32299 0.12% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 410 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 4987106 18.45% 85.45% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3934329 14.55% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 31424362 66.48% 66.48% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 37916 0.08% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 2870 0.01% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 8667813 18.34% 84.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 7137097 15.10% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 27034243 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1311430 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 47270058 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1222810 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 116684345 # The number of ROB reads -system.cpu2.rob.rob_writes 65897015 # The number of ROB writes -system.cpu2.timesIdled 179321 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1000773 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3544672545 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 22819105 # Number of Instructions Simulated -system.cpu2.committedOps 26959879 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 3.858633 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 3.858633 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.259159 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.259159 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 45005013 # number of integer regfile reads -system.cpu2.int_regfile_writes 19153075 # number of integer regfile writes -system.cpu2.fp_regfile_reads 47120 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45464 # number of floating regfile writes -system.cpu2.cc_regfile_reads 130804455 # number of cc regfile reads -system.cpu2.cc_regfile_writes 12559622 # number of cc regfile writes -system.cpu2.misc_regfile_reads 122469878 # number of misc regfile reads -system.cpu2.misc_regfile_writes 350259 # number of misc regfile writes -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.cpu2.rob.rob_reads 113043839 # The number of ROB reads +system.cpu2.rob.rob_writes 112575250 # The number of ROB writes +system.cpu2.timesIdled 280666 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1898147 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 5250079706 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 38852054 # Number of Instructions Simulated +system.cpu2.committedOps 47206281 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.797379 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.797379 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.556366 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.556366 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 56467494 # number of integer regfile reads +system.cpu2.int_regfile_writes 31953659 # number of integer regfile writes +system.cpu2.fp_regfile_reads 15852 # number of floating regfile reads +system.cpu2.fp_regfile_writes 13698 # number of floating regfile writes +system.cpu2.cc_regfile_reads 182453688 # number of cc regfile reads +system.cpu2.cc_regfile_writes 19285573 # number of cc regfile writes +system.cpu2.misc_regfile_reads 124185765 # number of misc regfile reads +system.cpu2.misc_regfile_writes 483246 # number of misc regfile writes +system.iocache.tags.replacements 36442 # number of replacements +system.iocache.tags.tagsinuse 0.992778 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.992778 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062049 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062049 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328356 # Number of tag accesses +system.iocache.tags.data_accesses 328356 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses +system.iocache.ReadReq_misses::total 252 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 9 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 9 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses +system.iocache.demand_misses::total 252 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 252 # number of overall misses +system.iocache.overall_misses::total 252 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 14192930 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 14192930 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 14192930 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14192930 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 14192930 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14192930 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36233 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36233 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000248 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000248 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 56321.150794 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 56321.150794 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 56321.150794 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 56321.150794 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1536462300750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1536462300750 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 125 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 125 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 125 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 125 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 7692930 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 7692930 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 1401235920 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1401235920 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 7692930 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7692930 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 7692930 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7692930 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.496032 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.496032 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.496032 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61543.440000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 61543.440000 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal Binary files differindex f40477dbc..b3be0ec54 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 5d2c59c2a..9bcc8ea41 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename= +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 -flags_addr=268435504 -gic_cpu_addr=520093952 +flags_addr=469827632 +gic_cpu_addr=738205696 have_generic_timer=false have_large_asid_64=false have_lpae=false @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 -load_offset=0 -machine_type=RealView_PBX +load_offset=2147483648 +machine_type=VExpress_EMM mem_mode=timing -mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -53,14 +53,14 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[0] +system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=268435456:520093695 1073741824:1610612735 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -654,6 +654,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu0.istage2_mmu] @@ -1180,6 +1181,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu1.istage2_mmu] @@ -1251,15 +1253,16 @@ type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 -use_default_range=false +use_default_range=true width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] type=BaseCache children=tags -addr_ranges=0:134217727 +addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain eventq_index=0 @@ -1278,8 +1281,8 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[26] -mem_side=system.membus.slave[2] +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] [system.iocache.tags] type=LRU @@ -1314,7 +1317,7 @@ tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c.tags] type=LRU @@ -1337,8 +1340,8 @@ system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -1394,6 +1397,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -1403,7 +1407,7 @@ mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive -range=0:134217727 +range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1432,46 +1436,37 @@ tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 -port=system.membus.master[6] +port=system.membus.master[5] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=0 +pci_cfg_base=805306368 pci_cfg_gen_offsets=false pci_io_base=0 system=system -[system.realview.a9scu] -type=A9SCU -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=520093696 -pio_latency=100000 -system=system -pio=system.membus.master[4] - [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268451840 +pio_addr=470024192 pio_latency=100000 system=system -pio=system.iobus.master[21] +pio=system.iobus.master[18] [system.realview.cf_ctrl] type=IdeController -BAR0=402653184 +BAR0=471465984 BAR0LegacyIO=true -BAR0Size=16 -BAR1=402653440 +BAR0Size=256 +BAR1=471466240 BAR1LegacyIO=true -BAR1Size=1 +BAR1Size=4096 BAR2=1 BAR2LegacyIO=false BAR2Size=8 @@ -1541,18 +1536,18 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 -disks=system.cf0 +disks= eventq_index=0 -io_shift=1 +io_shift=2 pci_bus=2 -pci_dev=7 +pci_dev=0 pci_func=0 pio_latency=30000 platform=system.realview system=system -config=system.iobus.master[8] +config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.clcd] type=Pl111 @@ -1561,8 +1556,8 @@ clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic -int_num=55 -pio_addr=268566528 +int_num=46 +pio_addr=471793664 pio_latency=10000 pixel_clock=41667 system=system @@ -1570,51 +1565,129 @@ vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] -[system.realview.dmac_fake] -type=AmbaFake -amba_id=0 +[system.realview.energy_ctrl] +type=EnergyCtrl clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler eventq_index=0 -ignore_access=false -pio_addr=268632064 +pio_addr=470286336 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[22] -[system.realview.energy_ctrl] -type=EnergyCtrl +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler +config_latency=20000 eventq_index=0 -pio_addr=268496896 -pio_latency=100000 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] pio=system.iobus.master[25] -[system.realview.flash_fake] -type=IsaFake -clk_domain=system.clk_domain +[system.realview.generic_timer] +type=GenericTimer eventq_index=0 -fake_mem=true -pio_addr=1073741824 -pio_latency=100000 -pio_size=536870912 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 +gic=system.realview.gic +int_num=29 system=system -update_data=false -warn_access= -pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain -cpu_addr=520093952 +cpu_addr=738205696 cpu_pio_delay=10000 -dist_addr=520097792 +dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 int_latency=10000 @@ -1624,38 +1697,111 @@ platform=system.realview system=system pio=system.membus.master[2] -[system.realview.gpio0_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268513280 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.gpio1_fake] -type=AmbaFake -amba_id=0 +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 clk_domain=system.clk_domain +enable_capture=true eventq_index=0 -ignore_access=false -pio_addr=268517376 -pio_latency=100000 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 system=system -pio=system.iobus.master[17] +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] -[system.realview.gpio2_fake] -type=AmbaFake -amba_id=0 +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 eventq_index=0 -ignore_access=false -pio_addr=268521472 -pio_latency=100000 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview system=system -pio=system.iobus.master[18] +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] [system.realview.kmi0] type=Pl050 @@ -1664,13 +1810,13 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=52 +int_num=44 is_mouse=false -pio_addr=268460032 +pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.kmi1] type=Pl050 @@ -1679,20 +1825,20 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=53 +int_num=45 is_mouse=true -pio_addr=268464128 +pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false -pio_addr=520101888 +pio_addr=739246080 pio_latency=100000 pio_size=4095 ret_bad_addr=false @@ -1703,7 +1849,25 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[3] +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer @@ -1712,10 +1876,10 @@ eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 -pio_addr=520095232 +pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[3] [system.realview.mmc_fake] type=AmbaFake @@ -1723,10 +1887,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268455936 +pio_addr=470089728 pio_latency=100000 system=system -pio=system.iobus.master[22] +pio=system.iobus.master[21] [system.realview.nvmem] type=SimpleMemory @@ -1738,18 +1902,30 @@ in_addr_map=true latency=30000 latency_var=0 null=false -range=2147483648:2214592511 +range=0:67108863 port=system.membus.master[1] +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 -idreg=0 -pio_addr=268435456 +idreg=35979264 +pio_addr=469827584 pio_latency=100000 -proc_id0=201326592 -proc_id1=201327138 +proc_id0=335544320 +proc_id1=335544320 system=system pio=system.iobus.master[1] @@ -1760,34 +1936,12 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=42 -pio_addr=268529664 +int_num=36 +pio_addr=471269376 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[23] - -[system.realview.sci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268492800 -pio_latency=100000 -system=system -pio=system.iobus.master[20] - -[system.realview.smc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=269357056 -pio_latency=100000 -system=system -pio=system.iobus.master[13] +pio=system.iobus.master[10] [system.realview.sp810_fake] type=AmbaFake @@ -1795,21 +1949,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true -pio_addr=268439552 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.ssp_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268488704 +pio_addr=469893120 pio_latency=100000 system=system -pio=system.iobus.master[19] +pio=system.iobus.master[16] [system.realview.timer0] type=Sp804 @@ -1819,9 +1962,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=36 -int_num1=36 -pio_addr=268505088 +int_num0=34 +int_num1=34 +pio_addr=470876160 pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1834,9 +1977,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=37 -int_num1=37 -pio_addr=268509184 +int_num0=35 +int_num1=35 +pio_addr=470941696 pio_latency=100000 system=system pio=system.iobus.master[3] @@ -1848,8 +1991,8 @@ end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=44 -pio_addr=268472320 +int_num=37 +pio_addr=470351872 pio_latency=100000 platform=system.realview system=system @@ -1862,10 +2005,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268476416 +pio_addr=470417408 pio_latency=100000 system=system -pio=system.iobus.master[10] +pio=system.iobus.master[13] [system.realview.uart2_fake] type=AmbaFake @@ -1873,10 +2016,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268480512 +pio_addr=470482944 pio_latency=100000 system=system -pio=system.iobus.master[11] +pio=system.iobus.master[14] [system.realview.uart3_fake] type=AmbaFake @@ -1884,10 +2027,54 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268484608 +pio_addr=470548480 pio_latency=100000 system=system -pio=system.iobus.master[12] +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] [system.realview.watchdog_fake] type=AmbaFake @@ -1895,10 +2082,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268500992 +pio_addr=470745088 pio_latency=100000 system=system -pio=system.iobus.master[15] +pio=system.iobus.master[17] [system.terminal] type=Terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index 5150881aa..adbb69884 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -1,24 +1,54 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: LCD dual screen mode not supported -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4] +warn: CP14 unimplemented crn[8], opc1[4], crm[12], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1] +warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[5] +warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1] +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr +warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[6] +warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] +warn: CP14 unimplemented crn[4], opc1[5], crm[12], opc2[1] +warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0] +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: instruction 'mcr bpiall' unimplemented warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index 74b77ce44..4796b8caa 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:22:42 -gem5 started Jun 21 2014 21:27:42 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:21:54 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x60c5390 0x60c5390 - 0: system.cpu1.isa: ISA system set to: 0x60c5390 0x60c5390 + 0: system.cpu0.isa: ISA system set to: 0x422cb00 0x422cb00 + 0: system.cpu1.isa: ISA system set to: 0x422cb00 0x422cb00 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 6d01b379d..9eb62fabd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,154 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.539695 # Number of seconds simulated -sim_ticks 2539695141000 # Number of ticks simulated -final_tick 2539695141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804329 # Number of seconds simulated +sim_ticks 2804328920000 # Number of ticks simulated +final_tick 2804328920000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66572 # Simulator instruction rate (inst/s) -host_op_rate 80202 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2802822069 # Simulator tick rate (ticks/s) -host_mem_usage 418352 # Number of bytes of host memory used -host_seconds 906.12 # Real time elapsed on the host -sim_insts 60322278 # Number of instructions simulated -sim_ops 72673006 # Number of ops (including micro ops) simulated +host_inst_rate 115537 # Simulator instruction rate (inst/s) +host_op_rate 140231 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2770199215 # Simulator tick rate (ticks/s) +host_mem_usage 563788 # Number of bytes of host memory used +host_seconds 1012.32 # Real time elapsed on the host +sim_insts 116960928 # Number of instructions simulated +sim_ops 141958852 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 4992 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 471296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3922776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 314048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5167104 # Number of bytes read from this memory -system.physmem.bytes_read::total 130987352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 471296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 314048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 785344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3775232 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1328636 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1687436 # Number of bytes written to this memory -system.physmem.bytes_written::total 6791304 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 739456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5170528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 635584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4648772 # Number of bytes read from this memory +system.physmem.bytes_read::total 11204324 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 739456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 635584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1375040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6110656 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory +system.physmem.bytes_written::total 8446516 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 78 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7364 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 61319 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 80736 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293167 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58988 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 332159 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 421859 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813006 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47687034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 185572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1544585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 123656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2034537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51576014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 185572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 123656 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 309228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1486490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 523148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 664425 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2674063 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1486490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47687034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 185572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2067733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 123656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2698962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54250077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293167 # Number of read requests accepted -system.physmem.writeReqs 813006 # Number of write requests accepted -system.physmem.readBursts 15293167 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813006 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 975220032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3542656 # Total number of bytes read from write queue -system.physmem.bytesWritten 6827904 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130987352 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6791304 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 55354 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706297 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4647 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 954783 # Per bank write bursts -system.physmem.perBankRdBursts::1 950591 # Per bank write bursts -system.physmem.perBankRdBursts::2 950729 # Per bank write bursts -system.physmem.perBankRdBursts::3 950904 # Per bank write bursts -system.physmem.perBankRdBursts::4 954888 # Per bank write bursts -system.physmem.perBankRdBursts::5 951868 # Per bank write bursts -system.physmem.perBankRdBursts::6 951800 # Per bank write bursts -system.physmem.perBankRdBursts::7 951730 # Per bank write bursts -system.physmem.perBankRdBursts::8 955391 # Per bank write bursts -system.physmem.perBankRdBursts::9 951917 # Per bank write bursts -system.physmem.perBankRdBursts::10 951458 # Per bank write bursts -system.physmem.perBankRdBursts::11 951066 # Per bank write bursts -system.physmem.perBankRdBursts::12 955340 # Per bank write bursts -system.physmem.perBankRdBursts::13 951888 # Per bank write bursts -system.physmem.perBankRdBursts::14 951979 # Per bank write bursts -system.physmem.perBankRdBursts::15 951481 # Per bank write bursts -system.physmem.perBankWrBursts::0 6606 # Per bank write bursts -system.physmem.perBankWrBursts::1 6389 # Per bank write bursts -system.physmem.perBankWrBursts::2 6527 # Per bank write bursts -system.physmem.perBankWrBursts::3 6560 # Per bank write bursts -system.physmem.perBankWrBursts::4 6487 # Per bank write bursts -system.physmem.perBankWrBursts::5 6764 # Per bank write bursts -system.physmem.perBankWrBursts::6 6744 # Per bank write bursts -system.physmem.perBankWrBursts::7 6672 # Per bank write bursts -system.physmem.perBankWrBursts::8 7003 # Per bank write bursts -system.physmem.perBankWrBursts::9 6796 # Per bank write bursts -system.physmem.perBankWrBursts::10 6466 # Per bank write bursts -system.physmem.perBankWrBursts::11 6118 # Per bank write bursts -system.physmem.perBankWrBursts::12 7066 # Per bank write bursts -system.physmem.perBankWrBursts::13 6690 # Per bank write bursts -system.physmem.perBankWrBursts::14 6968 # Per bank write bursts -system.physmem.perBankWrBursts::15 6830 # Per bank write bursts +system.physmem.num_reads::cpu0.inst 11554 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 81308 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 72638 # Number of read requests responded to by this memory +system.physmem.num_reads::total 175587 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 95479 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136084 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 1780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 263684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1843767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 226644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1657713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3995367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 263684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 226644 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 490328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2179008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 826699 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3011956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2179008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 827041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 263684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1850013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1415 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 226644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1657716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7007324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175588 # Number of read requests accepted +system.physmem.writeReqs 136084 # Number of write requests accepted +system.physmem.readBursts 175588 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 136084 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11230016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 8460224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11204388 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8446516 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3871 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4656 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11119 # Per bank write bursts +system.physmem.perBankRdBursts::1 11133 # Per bank write bursts +system.physmem.perBankRdBursts::2 11709 # Per bank write bursts +system.physmem.perBankRdBursts::3 11218 # Per bank write bursts +system.physmem.perBankRdBursts::4 11369 # Per bank write bursts +system.physmem.perBankRdBursts::5 11386 # Per bank write bursts +system.physmem.perBankRdBursts::6 11957 # Per bank write bursts +system.physmem.perBankRdBursts::7 11810 # Per bank write bursts +system.physmem.perBankRdBursts::8 10209 # Per bank write bursts +system.physmem.perBankRdBursts::9 10442 # Per bank write bursts +system.physmem.perBankRdBursts::10 10595 # Per bank write bursts +system.physmem.perBankRdBursts::11 9762 # Per bank write bursts +system.physmem.perBankRdBursts::12 10419 # Per bank write bursts +system.physmem.perBankRdBursts::13 11416 # Per bank write bursts +system.physmem.perBankRdBursts::14 10636 # Per bank write bursts +system.physmem.perBankRdBursts::15 10289 # Per bank write bursts +system.physmem.perBankWrBursts::0 8317 # Per bank write bursts +system.physmem.perBankWrBursts::1 8433 # Per bank write bursts +system.physmem.perBankWrBursts::2 9040 # Per bank write bursts +system.physmem.perBankWrBursts::3 8546 # Per bank write bursts +system.physmem.perBankWrBursts::4 8342 # Per bank write bursts +system.physmem.perBankWrBursts::5 8537 # Per bank write bursts +system.physmem.perBankWrBursts::6 8976 # Per bank write bursts +system.physmem.perBankWrBursts::7 8813 # Per bank write bursts +system.physmem.perBankWrBursts::8 7760 # Per bank write bursts +system.physmem.perBankWrBursts::9 7806 # Per bank write bursts +system.physmem.perBankWrBursts::10 7935 # Per bank write bursts +system.physmem.perBankWrBursts::11 7392 # Per bank write bursts +system.physmem.perBankWrBursts::12 7884 # Per bank write bursts +system.physmem.perBankWrBursts::13 8744 # Per bank write bursts +system.physmem.perBankWrBursts::14 8047 # Per bank write bursts +system.physmem.perBankWrBursts::15 7619 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2539694027000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2804328669500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 18 # Read request sizes (log2) -system.physmem.readPktSize::3 15138826 # Read request sizes (log2) +system.physmem.readPktSize::2 541 # Read request sizes (log2) +system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154323 # Read request sizes (log2) +system.physmem.readPktSize::6 175033 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 58988 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1062880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1005296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1064387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 969141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1032129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2687855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2599195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3397795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 102458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 95445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 91862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 18918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131703 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 104493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,477 +164,480 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1008813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.468756 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 909.284641 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.732372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22320 2.21% 2.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20114 1.99% 4.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8797 0.87% 5.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2199 0.22% 5.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2055 0.20% 5.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1694 0.17% 5.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9190 0.91% 6.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 817 0.08% 6.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 941627 93.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1008813 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6078 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2507.042448 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 47447.723031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6050 99.54% 99.54% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 3 0.05% 99.59% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 5 0.08% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.84% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6078 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.552813 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.369881 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.322612 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 5 0.08% 0.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 4 0.07% 0.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 4 0.07% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 3 0.05% 0.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 1 0.02% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 6 0.10% 0.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.05% 0.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 2 0.03% 0.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 3 0.05% 0.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 3 0.05% 0.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 2 0.03% 0.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 13 0.21% 0.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2782 45.77% 46.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 46 0.76% 47.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1401 23.05% 70.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1370 22.54% 93.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 152 2.50% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 75 1.23% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 36 0.59% 97.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 22 0.36% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 24 0.39% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 25 0.41% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 13 0.21% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 15 0.25% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 16 0.26% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 12 0.20% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 9 0.15% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 11 0.18% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6078 # Writes before turning the bus around for reads -system.physmem.totQLat 392436805250 # Total ticks spent queuing -system.physmem.totMemAccLat 678145799000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76189065000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25754.14 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.565754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.964808 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.021120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24334 37.64% 37.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15675 24.25% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6689 10.35% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3630 5.61% 77.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2748 4.25% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1525 2.36% 84.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1125 1.74% 86.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1111 1.72% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7813 12.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64650 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6707 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.160877 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 477.303834 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6704 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6707 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.709408 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.238406 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.151792 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 14 0.21% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 6 0.09% 0.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.06% 0.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 11 0.16% 0.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5779 86.16% 86.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 101 1.51% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 51 0.76% 88.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 232 3.46% 92.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 200 2.98% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.31% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.33% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.18% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 28 0.42% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.12% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.07% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 157 2.34% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 11 0.16% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 5 0.07% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.06% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6707 # Writes before turning the bus around for reads +system.physmem.totQLat 2725885000 # Total ticks spent queuing +system.physmem.totMemAccLat 6015928750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 877345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15534.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44504.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.69 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34284.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.02 # Data bus utilization in percentage -system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.40 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.87 # Average write queue length when enqueuing -system.physmem.readRowHits 14244486 # Number of row buffer hits during reads -system.physmem.writeRowHits 91200 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.47 # Row buffer hit rate for writes -system.physmem.avgGap 157684.51 # Average gap between requests -system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2193361967750 # Time in different power states -system.physmem.memoryStateTime::REF 84805760000 # Time in different power states +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.75 # Average write queue length when enqueuing +system.physmem.readRowHits 145120 # Number of row buffer hits during reads +system.physmem.writeRowHits 97889 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.04 # Row buffer hit rate for writes +system.physmem.avgGap 8997692.03 # Average gap between requests +system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2678489596250 # Time in different power states +system.physmem.memoryStateTime::REF 93642640000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 261520412250 # Time in different power states +system.physmem.memoryStateTime::ACT 32196672750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3810769200 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3815857080 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2079288750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2082064875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 59414885400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 59440056000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 341813520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 349511760 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 165880066560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 165880066560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 143884087110 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 144952782390 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1397598764250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1396661312250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1773009674790 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1773181650915 # Total energy per rank (pJ) -system.physmem.averagePower::0 698.121024 # Core power per rank (mW) -system.physmem.averagePower::1 698.188739 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16345693 # Transaction distribution -system.membus.trans_dist::ReadResp 16345693 # Transaction distribution -system.membus.trans_dist::WriteReq 763357 # Transaction distribution -system.membus.trans_dist::WriteResp 763357 # Transaction distribution -system.membus.trans_dist::Writeback 58988 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4647 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4647 # Transaction distribution -system.membus.trans_dist::ReadExReq 131549 # Transaction distribution -system.membus.trans_dist::ReadExResp 131549 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885020 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4271848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34549480 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16668128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19066210 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 140176738 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 217843 # Request fanout histogram +system.physmem.actEnergy::0 258567120 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 230186880 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 141083250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 125598000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 715260000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 653390400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 447145920 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 409451760 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 183165003840 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 183165003840 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 77778018765 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 76614000390 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1614369982500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1615391051250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1876875061395 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1876588682520 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.278202 # Core power per rank (mW) +system.physmem.averagePower::1 669.176082 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 251 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 251 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 251 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 251 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 251 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 251 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 67981 # Transaction distribution +system.membus.trans_dist::ReadResp 67980 # Transaction distribution +system.membus.trans_dist::WriteReq 27608 # Transaction distribution +system.membus.trans_dist::WriteResp 27608 # Transaction distribution +system.membus.trans_dist::Writeback 95479 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4633 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 23 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4656 # Transaction distribution +system.membus.trans_dist::ReadExReq 138435 # Transaction distribution +system.membus.trans_dist::ReadExResp 138435 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464698 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 572340 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645052 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17331544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17495585 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19814881 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 234 # Total snoops (count) +system.membus.snoop_fanout::samples 310978 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 217843 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 310978 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 217843 # Request fanout histogram -system.membus.reqLayer0.occupancy 1488348000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 310978 # Request fanout histogram +system.membus.reqLayer0.occupancy 81489000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 16812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3508000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1718500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17564779000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4755343440 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37440252152 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.5 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1433405250 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 1729661846 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38504711 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64097 # number of replacements -system.l2c.tags.tagsinuse 51403.492359 # Cycle average of tags in use -system.l2c.tags.total_refs 1900046 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129489 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.673416 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2528369126500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37092.927950 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.579992 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5418.531577 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3300.356905 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.423602 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2630.879076 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2944.793006 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.565993 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000146 # Average percentage of cache occupancy +system.l2c.tags.replacements 104201 # number of replacements +system.l2c.tags.tagsinuse 65131.975269 # Cycle average of tags in use +system.l2c.tags.total_refs 3107275 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169441 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 18.338389 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48640.203385 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 54.461812 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000235 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5568.717985 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2872.344417 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 41.548233 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4966.062481 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2988.636721 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.742191 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000831 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.082680 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050359 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040144 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044934 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784355 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 434 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3142 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5950 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55813 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18888451 # Number of tag accesses -system.l2c.tags.data_accesses 18888451 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 27538 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7475 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 477559 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 174980 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30012 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 8090 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 496617 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 210611 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1432882 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 606482 # number of Writeback hits -system.l2c.Writeback_hits::total 606482 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55610 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57109 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112719 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 27538 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7475 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 477559 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 230590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30012 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 8090 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 496617 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 267720 # number of demand (read+write) hits -system.l2c.demand_hits::total 1545601 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 27538 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7475 # number of overall hits -system.l2c.overall_hits::cpu0.inst 477559 # number of overall hits -system.l2c.overall_hits::cpu0.data 230590 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30012 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 8090 # number of overall hits -system.l2c.overall_hits::cpu1.inst 496617 # number of overall hits -system.l2c.overall_hits::cpu1.data 267720 # number of overall hits -system.l2c.overall_hits::total 1545601 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 15 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.084972 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000634 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.075776 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.045603 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993835 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65170 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 70 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3222 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8954 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52610 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.001068 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994415 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 29225778 # Number of tag accesses +system.l2c.tags.data_accesses 29225778 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 36725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 8774 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 958768 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 271288 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 36918 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 8011 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 964418 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 269869 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2554771 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 703572 # number of Writeback hits +system.l2c.Writeback_hits::total 703572 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 47 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 58 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 105 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 15 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 45 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 77545 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 79094 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 156639 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 36725 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 8774 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 958768 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 348833 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 36918 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 8011 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 964418 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 348963 # number of demand (read+write) hits +system.l2c.demand_hits::total 2711410 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 36725 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 8774 # number of overall hits +system.l2c.overall_hits::cpu0.inst 958768 # number of overall hits +system.l2c.overall_hits::cpu0.data 348833 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 36918 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 8011 # number of overall hits +system.l2c.overall_hits::cpu1.inst 964418 # number of overall hits +system.l2c.overall_hits::cpu1.data 348963 # number of overall hits +system.l2c.overall_hits::total 2711410 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 78 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7255 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6034 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4911 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4500 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22725 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1367 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1537 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 56126 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77166 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133292 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 15 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 10910 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7138 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 62 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 9936 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 7955 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36080 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1305 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1437 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2742 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 6 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 17 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 23 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 74623 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 65703 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140326 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 78 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7255 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 62160 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4911 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 81666 # number of demand (read+write) misses -system.l2c.demand_misses::total 156017 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 15 # number of overall misses +system.l2c.demand_misses::cpu0.inst 10910 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 81761 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 62 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 9936 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 73658 # number of demand (read+write) misses +system.l2c.demand_misses::total 176406 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 78 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7255 # number of overall misses -system.l2c.overall_misses::cpu0.data 62160 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4911 # number of overall misses -system.l2c.overall_misses::cpu1.data 81666 # number of overall misses -system.l2c.overall_misses::total 156017 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1563750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 521104500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 442572744 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 713750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 356046000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 335278744 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1657361488 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 185992 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 279488 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4022661419 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5771447585 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9794109004 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1563750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 82000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 521104500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4465234163 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 713750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 356046000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6106726329 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11451470492 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1563750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 82000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 521104500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4465234163 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 713750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 356046000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6106726329 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11451470492 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 27553 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7476 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 484814 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 181014 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30021 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 8090 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 501528 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 215111 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1455607 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 606482 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 606482 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1384 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1553 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111736 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 134275 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246011 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 27553 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7476 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 484814 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 292750 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30021 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 8090 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 501528 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 349386 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1701618 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 27553 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7476 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 484814 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 292750 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30021 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 8090 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 501528 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 349386 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1701618 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000134 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014965 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.033334 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000300 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009792 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020919 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015612 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987717 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989697 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.988764 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.502309 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.574686 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541813 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000134 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014965 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.212331 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000300 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009792 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.233741 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091687 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000134 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014965 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.212331 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000300 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009792 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.233741 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091687 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 104250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71826.946933 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73346.493868 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79305.555556 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72499.694563 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 74506.387556 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 72931.198592 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 136.058522 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 181.839948 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 160.289256 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71671.977675 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74792.623500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73478.595895 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 104250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 71826.946933 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 71834.526432 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79305.555556 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72499.694563 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74776.851187 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 73398.863534 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 104250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 71826.946933 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 71834.526432 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79305.555556 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72499.694563 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74776.851187 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 73398.863534 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 10910 # number of overall misses +system.l2c.overall_misses::cpu0.data 81761 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 62 # number of overall misses +system.l2c.overall_misses::cpu1.inst 9936 # number of overall misses +system.l2c.overall_misses::cpu1.data 73658 # number of overall misses +system.l2c.overall_misses::total 176406 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 6586000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 832891250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 575497992 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5167000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 747110750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 644595992 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2811923484 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 329986 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 419482 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 749468 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 92496 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162493 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 254989 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5741186064 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5103227796 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10844413860 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 6586000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 74500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 832891250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 6316684056 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 5167000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 747110750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 5747823788 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 13656337344 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 6586000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 74500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 832891250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 6316684056 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 5167000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 747110750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 5747823788 # number of overall miss cycles +system.l2c.overall_miss_latency::total 13656337344 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 36803 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 8775 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 969678 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 278426 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 36980 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 8011 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 974354 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 277824 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2590851 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 703572 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 703572 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1352 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1495 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2847 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 21 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 47 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 68 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 152168 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 144797 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296965 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 36803 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 8775 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 969678 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 430594 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 36980 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 8011 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 974354 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 422621 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2887816 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 36803 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 8775 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 969678 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 430594 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 36980 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 8011 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 974354 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 422621 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2887816 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002119 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000114 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.011251 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.025637 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001677 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010198 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.028633 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.965237 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.961204 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.963119 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.285714 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.361702 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.338235 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.490399 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.453759 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.472534 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002119 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000114 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.011251 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.189880 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001677 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010198 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.174289 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.061086 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002119 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000114 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.011251 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.189880 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001677 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010198 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.174289 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.061086 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 84435.897436 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76342.002750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 80624.543570 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83338.709677 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75192.305757 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 81030.294406 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 77935.795011 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 252.862835 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 291.915101 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 273.328957 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15416 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9558.411765 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 11086.478261 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76935.878536 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77671.153463 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 77280.146658 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 84435.897436 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 76342.002750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 77257.910936 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83338.709677 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75192.305757 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 78033.937766 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 77414.245230 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 84435.897436 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 76342.002750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 77257.910936 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83338.709677 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75192.305757 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 78033.937766 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 77414.245230 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,154 +646,166 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58988 # number of writebacks -system.l2c.writebacks::total 58988 # number of writebacks +system.l2c.writebacks::writebacks 95479 # number of writebacks +system.l2c.writebacks::total 95479 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 71 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 66 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 148 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 71 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 66 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 148 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 66 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 15 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::cpu0.data 71 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 66 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 148 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 78 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7249 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5996 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4907 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4482 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22659 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1367 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1537 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2904 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 56126 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 77166 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133292 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 15 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 10904 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 7067 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 62 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 9931 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 7889 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 35932 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1305 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1437 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 6 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 17 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 23 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 74623 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 65703 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140326 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 78 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7249 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 62122 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4907 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 81648 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 155951 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 15 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 10904 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 81690 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 62 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 9931 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 73592 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176258 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 78 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7249 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 62122 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4907 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 81648 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 155951 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1379250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 429544750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 365182494 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 294088000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 278470744 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1369338988 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13675367 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15376536 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29051903 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3321727581 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4810247909 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8131975490 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1379250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 429544750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3686910075 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 603750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 294088000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5088718653 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9501314478 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1379250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 429544750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3686910075 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 603750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 294088000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5088718653 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9501314478 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6123500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83706366250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83236564000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166949053750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 7705500500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 9339419914 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17044920414 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6123500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91411866750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92575983914 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183993974164 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033125 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020836 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015567 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987717 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989697 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.988764 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502309 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.574686 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541813 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.212202 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.233690 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091649 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.212202 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.233690 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091649 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60904.351901 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62130.911200 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60432.454566 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.926116 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.252440 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.098829 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59183.401294 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62336.364578 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61008.728881 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59349.507018 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62325.086383 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 60924.998737 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59349.507018 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62325.086383 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60924.998737 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 10904 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 81690 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 62 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 9931 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 73592 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176258 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5619000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 695263500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 482934742 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4398500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 621792250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 542490992 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2352561484 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13058305 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14434936 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 27493241 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 60006 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 170017 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 230023 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4809749936 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4286056704 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9095806640 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 5619000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 695263500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5292684678 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4398500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 621792250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4828547696 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 11448368124 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5619000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 695263500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5292684678 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4398500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 621792250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4828547696 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 11448368124 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 36174500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2949055750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2430218500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5415448750 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2226044000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1876060498 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4102104498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 36174500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5175099750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4306278998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 9517553248 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002119 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000114 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.011245 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.025382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001677 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010192 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.028396 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013869 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.965237 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.961204 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.963119 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.361702 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.338235 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.490399 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.453759 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.472534 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002119 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000114 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.011245 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.189715 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001677 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010192 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.174132 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061035 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002119 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000114 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.011245 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.189715 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001677 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010192 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.174132 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061035 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68336.598557 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68765.495247 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 65472.600579 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.363985 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10045.188587 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.710795 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64453.987859 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65233.805214 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64819.111498 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64789.872420 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65612.399391 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64952.331945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72038.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63762.243213 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64789.872420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70943.548387 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62611.242574 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65612.399391 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64952.331945 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -800,177 +818,203 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2673184 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2673184 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 606482 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2937 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2940 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246011 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246011 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1973853 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5791552 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42247 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136455 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7944107 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63133312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85325794 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 148751666 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 33359 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2344441 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 2655300 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2655214 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 703572 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2847 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 68 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2915 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296965 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296965 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3889644 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533488 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43405 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169876 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6636413 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124460352 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99828001 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 67144 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 295132 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224650629 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 69040 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3663181 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.009957 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.099289 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 2344441 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3626705 99.00% 99.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36476 1.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2344441 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4954098182 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3663181 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4671577230 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4446552172 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4477877910 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26748853 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 8759110629 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 3910283961 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 26690343 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 79493732 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96888385 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 16322162 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322162 # Transaction distribution -system.iobus.trans_dist::WriteReq 8176 # Transaction distribution -system.iobus.trans_dist::WriteResp 8176 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 30210 # Transaction distribution +system.iobus.trans_dist::ReadResp 30210 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660676 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 123500982 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480421 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3969000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38127481848 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7736387 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5741528 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 324689 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4736478 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3796485 # Number of BTB hits +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326614549 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36835289 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 26968745 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14109241 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 549589 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 16704483 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12571056 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 80.154178 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 808967 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 22406 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 75.255583 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6684107 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29871 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -994,25 +1038,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 27184101 # DTB read hits -system.cpu0.dtb.read_misses 37692 # DTB read misses -system.cpu0.dtb.write_hits 5601213 # DTB write hits -system.cpu0.dtb.write_misses 10069 # DTB write misses -system.cpu0.dtb.flush_tlb 510 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5493 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 558 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch +system.cpu0.dtb.read_hits 14281958 # DTB read hits +system.cpu0.dtb.read_misses 49036 # DTB read misses +system.cpu0.dtb.write_hits 10331652 # DTB write hits +system.cpu0.dtb.write_misses 7432 # DTB write misses +system.cpu0.dtb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 474 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 3418 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 971 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1307 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 698 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 27221793 # DTB read accesses -system.cpu0.dtb.write_accesses 5611282 # DTB write accesses +system.cpu0.dtb.perms_faults 583 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14330994 # DTB read accesses +system.cpu0.dtb.write_accesses 10339084 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32785314 # DTB hits -system.cpu0.dtb.misses 47761 # DTB misses -system.cpu0.dtb.accesses 32833075 # DTB accesses +system.cpu0.dtb.hits 24613610 # DTB hits +system.cpu0.dtb.misses 56468 # DTB misses +system.cpu0.dtb.accesses 24670078 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1034,720 +1078,720 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5349776 # ITB inst hits -system.cpu0.itb.inst_misses 7612 # ITB inst misses +system.cpu0.itb.inst_hits 20359986 # ITB inst hits +system.cpu0.itb.inst_misses 8688 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 510 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2622 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 474 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2307 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2424 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1454 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5357388 # ITB inst accesses -system.cpu0.itb.hits 5349776 # DTB hits -system.cpu0.itb.misses 7612 # DTB misses -system.cpu0.itb.accesses 5357388 # DTB accesses -system.cpu0.numCycles 234157878 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20368674 # ITB inst accesses +system.cpu0.itb.hits 20359986 # DTB hits +system.cpu0.itb.misses 8688 # DTB misses +system.cpu0.itb.accesses 20368674 # DTB accesses +system.cpu0.numCycles 107845593 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 14748705 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 42201957 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7736387 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4605452 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 215146781 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 898208 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 106243 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 1405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1864 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 95051 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1850622 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5346983 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 204760 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2833 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 232399808 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.216000 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.156571 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 40386810 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 105587816 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26968745 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19255163 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 62197124 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3245751 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 127625 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 7153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 414 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 560512 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 142803 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20358682 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 375797 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3540 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 105045556 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.208380 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.316447 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 222777653 95.86% 95.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 886693 0.38% 96.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 957710 0.41% 96.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1031526 0.44% 97.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1201262 0.52% 97.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 716459 0.31% 97.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1131800 0.49% 98.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 450199 0.19% 98.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3246506 1.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 76194887 72.54% 72.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3754274 3.57% 76.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2490616 2.37% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 7859227 7.48% 85.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1696652 1.62% 87.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1110270 1.06% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6030562 5.74% 94.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1172073 1.12% 95.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4736995 4.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 232399808 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.033039 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.180229 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12178110 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 212389955 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6147086 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1310186 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 372224 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 973042 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 78155 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 44916036 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 260169 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 372224 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12790792 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 53545394 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 30504571 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6768689 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 128415973 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 43504199 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1378 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 95402427 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 124537502 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1839930 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 46109442 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 200228601 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 53009049 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5261 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36340147 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 9769295 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 578634 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 493652 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 7443860 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7970278 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6245265 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1090249 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1688574 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 41187030 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 989826 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 58971927 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 58739 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7127220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 15644672 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 268943 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 232399808 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.253752 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.958915 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 105045556 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.250068 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.979065 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27992831 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58288752 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15795686 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1494186 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1473806 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1905882 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 151125 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 87429633 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 488960 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1473806 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28854522 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7825241 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 44530433 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16415738 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 5945509 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 83590953 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2363 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1232745 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 241627 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3747183 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 86230749 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 384928079 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 93177414 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5669 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 72449468 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13781265 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1547727 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1453455 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8907873 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 15026911 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11459129 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1951942 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2729865 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 80431590 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1054195 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 77118742 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 91388 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10043438 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24751793 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 115145 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 105045556 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.734146 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.428326 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 212110796 91.27% 91.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6244814 2.69% 93.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2921782 1.26% 95.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2401444 1.03% 96.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6174292 2.66% 98.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1067597 0.46% 99.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 901998 0.39% 99.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 384604 0.17% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 192481 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74311546 70.74% 70.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10189117 9.70% 80.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7864547 7.49% 87.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6570455 6.25% 94.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2322662 2.21% 96.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1491632 1.42% 97.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1567348 1.49% 99.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 489722 0.47% 99.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 238527 0.23% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 232399808 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 105045556 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 115073 2.28% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4670641 92.37% 94.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 270791 5.36% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 112665 9.94% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 535473 47.24% 57.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 485278 42.82% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15020 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 25465355 43.18% 43.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47791 0.08% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 896 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 27510585 46.65% 89.94% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5932280 10.06% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2200 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 51451834 66.72% 66.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57694 0.07% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 2 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4462 0.01% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.80% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14684703 19.04% 85.84% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10917839 14.16% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 58971927 # Type of FU issued -system.cpu0.iq.rate 0.251847 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 5056507 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.085744 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 355447115 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 49321417 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 38218166 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11793 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6394 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5095 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 64007055 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6359 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 225424 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 77118742 # Type of FU issued +system.cpu0.iq.rate 0.715085 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1133419 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014697 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 260495273 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 91574151 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 74667012 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12574 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6644 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5487 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 78243199 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6762 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 345945 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1448099 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2516 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 24796 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 671952 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2206741 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2565 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 52530 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1128151 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17102895 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 3149110 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 207860 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 209627 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 372224 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 50935329 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1903194 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 42289333 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 78950 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7970278 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6245265 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 710795 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 138182 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1696089 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 24796 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 159500 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 133057 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 292557 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 58565137 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 27348453 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 359214 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1473806 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5382891 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 2162428 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 81613092 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 131628 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 15026911 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11459129 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 550936 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 43632 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2106388 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 52530 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 254626 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 219922 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 474548 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 76513772 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14449148 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 548624 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 112477 # number of nop insts executed -system.cpu0.iew.exec_refs 33216509 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5651382 # Number of branches executed -system.cpu0.iew.exec_stores 5868056 # Number of stores executed -system.cpu0.iew.exec_rate 0.250110 # Inst execution rate -system.cpu0.iew.wb_sent 55395790 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 38223261 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 21614386 # num instructions producing a value -system.cpu0.iew.wb_consumers 38462259 # num instructions consuming a value +system.cpu0.iew.exec_nop 127307 # number of nop insts executed +system.cpu0.iew.exec_refs 25261391 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14437195 # Number of branches executed +system.cpu0.iew.exec_stores 10812243 # Number of stores executed +system.cpu0.iew.exec_rate 0.709475 # Inst execution rate +system.cpu0.iew.wb_sent 75851893 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 74672499 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 39010696 # num instructions producing a value +system.cpu0.iew.wb_consumers 67649101 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.163237 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.561964 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.692402 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.576662 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7051288 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 720883 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 247682 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 231240606 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.150761 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 0.850016 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11320580 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 939050 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 400483 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 102489063 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.685035 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.574738 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 218744105 94.60% 94.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6302358 2.73% 97.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1708730 0.74% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1054896 0.46% 98.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 648771 0.28% 98.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 578680 0.25% 99.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 445136 0.19% 99.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 245162 0.11% 99.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1512768 0.65% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 75163014 73.34% 73.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12241374 11.94% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6264234 6.11% 91.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2647997 2.58% 93.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1295474 1.26% 95.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 837997 0.82% 96.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1889450 1.84% 97.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 409985 0.40% 98.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1739538 1.70% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 231240606 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29065490 # Number of instructions committed -system.cpu0.commit.committedOps 34862084 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 102489063 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 57892234 # Number of instructions committed +system.cpu0.commit.committedOps 70208613 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12095492 # Number of memory references committed -system.cpu0.commit.loads 6522179 # Number of loads committed -system.cpu0.commit.membars 193065 # Number of memory barriers committed -system.cpu0.commit.branches 4958543 # Number of branches committed -system.cpu0.commit.fp_insts 5094 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 30770331 # Number of committed integer instructions. -system.cpu0.commit.function_calls 472637 # Number of function calls committed. +system.cpu0.commit.refs 23151148 # Number of memory references committed +system.cpu0.commit.loads 12820170 # Number of loads committed +system.cpu0.commit.membars 372459 # Number of memory barriers committed +system.cpu0.commit.branches 13651808 # Number of branches committed +system.cpu0.commit.fp_insts 5463 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 61466111 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2656847 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 22721291 65.17% 65.17% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 44405 0.13% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 896 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.30% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 6522179 18.71% 84.01% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5573313 15.99% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 46997024 66.94% 66.94% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55979 0.08% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4462 0.01% 67.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12820170 18.26% 85.29% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10330978 14.71% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 34862084 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1512768 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 70208613 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1739538 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 270737391 # The number of ROB reads -system.cpu0.rob.rob_writes 84952654 # The number of ROB writes -system.cpu0.timesIdled 265059 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 1758070 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2270312982 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 28998871 # Number of Instructions Simulated -system.cpu0.committedOps 34795465 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 8.074724 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.074724 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.123843 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.123843 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66418764 # number of integer regfile reads -system.cpu0.int_regfile_writes 24158486 # number of integer regfile writes -system.cpu0.fp_regfile_reads 44743 # number of floating regfile reads -system.cpu0.fp_regfile_writes 41780 # number of floating regfile writes -system.cpu0.cc_regfile_reads 196661933 # number of cc regfile reads -system.cpu0.cc_regfile_writes 15655112 # number of cc regfile writes -system.cpu0.misc_regfile_reads 292292897 # number of misc regfile reads -system.cpu0.misc_regfile_writes 565980 # number of misc regfile writes -system.cpu0.icache.tags.replacements 986757 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.592826 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 9965260 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 987269 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.093764 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6651821250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 184.507996 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 327.084830 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.360367 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.638838 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999205 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 169616941 # The number of ROB reads +system.cpu0.rob.rob_writes 165619058 # The number of ROB writes +system.cpu0.timesIdled 398870 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2800037 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2442123265 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 57820351 # Number of Instructions Simulated +system.cpu0.committedOps 70136730 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.865184 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.865184 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.536140 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.536140 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 83228446 # number of integer regfile reads +system.cpu0.int_regfile_writes 47576245 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16184 # number of floating regfile reads +system.cpu0.fp_regfile_writes 12998 # number of floating regfile writes +system.cpu0.cc_regfile_reads 270476207 # number of cc regfile reads +system.cpu0.cc_regfile_writes 28213628 # number of cc regfile writes +system.cpu0.misc_regfile_reads 191272649 # number of misc regfile reads +system.cpu0.misc_regfile_writes 720305 # number of misc regfile writes +system.cpu0.icache.tags.replacements 1943673 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.578352 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 38923517 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1944185 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.020480 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9481344250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.782570 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 236.795782 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.536685 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.462492 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999176 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12017349 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12017349 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 4823854 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5141406 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 9965260 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 4823854 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5141406 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 9965260 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 4823854 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5141406 # number of overall hits -system.cpu0.icache.overall_hits::total 9965260 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 523011 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 541799 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1064810 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 523011 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 541799 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1064810 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 523011 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 541799 # number of overall misses -system.cpu0.icache.overall_misses::total 1064810 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7244933790 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7308182079 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14553115869 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7244933790 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7308182079 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14553115869 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7244933790 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7308182079 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14553115869 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5346865 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5683205 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11030070 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5346865 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5683205 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11030070 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5346865 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5683205 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11030070 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097816 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.095333 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.096537 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097816 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.095333 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.096537 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097816 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.095333 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.096537 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.354520 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13488.733052 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13667.335834 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.354520 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13488.733052 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13667.335834 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.354520 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13488.733052 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13667.335834 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4607 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 42951658 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42951658 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 19318996 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19604521 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 38923517 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19318996 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19604521 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 38923517 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19318996 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19604521 # number of overall hits +system.cpu0.icache.overall_hits::total 38923517 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1039021 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1044832 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2083853 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1039021 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1044832 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2083853 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1039021 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 1044832 # number of overall misses +system.cpu0.icache.overall_misses::total 2083853 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14217432245 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14193731102 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28411163347 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14217432245 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 14193731102 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28411163347 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14217432245 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14193731102 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28411163347 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 20358017 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20649353 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 41007370 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 20358017 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20649353 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 41007370 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 20358017 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20649353 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 41007370 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051037 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050599 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050817 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051037 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050599 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050817 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051037 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050599 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050817 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13683.488827 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13584.701753 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13633.957552 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13683.488827 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13584.701753 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13633.957552 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13683.488827 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13584.701753 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13633.957552 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8339 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 283 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 489 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.279152 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.053170 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37777 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39754 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 77531 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 37777 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39754 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 77531 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 37777 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39754 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 77531 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 485234 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 502045 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 987279 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 485234 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 502045 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 987279 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 485234 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 502045 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 987279 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5896477037 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5947728017 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11844205054 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5896477037 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5947728017 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11844205054 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5896477037 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5947728017 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11844205054 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8530500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8530500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8530500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8530500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089508 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.089508 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.089508 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11996.816557 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11996.816557 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11996.816557 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 69244 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 70320 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 139564 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 69244 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 70320 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 139564 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 69244 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 70320 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 139564 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 969777 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 974512 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1944289 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 969777 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 974512 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1944289 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 969777 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 974512 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1944289 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11614628478 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11591128360 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 23205756838 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11614628478 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11591128360 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 23205756838 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11614628478 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11591128360 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 23205756838 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 49940000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 49940000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49940000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 49940000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047636 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047193 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047413 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047636 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047193 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047413 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047636 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047193 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047413 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11976.597174 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.290024 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11935.343376 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11976.597174 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.290024 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11935.343376 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11976.597174 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.290024 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11935.343376 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 641624 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993418 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19749835 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 642136 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.756467 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 42094250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 133.332182 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 378.661236 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.260414 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.739573 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 852682 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.984423 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42512914 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 853194 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.827957 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 91705250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 329.938362 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 182.046061 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.644411 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.355559 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 95284916 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 95284916 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5852905 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6194424 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 12047329 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3505923 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3637478 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7143401 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 35429 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 29531 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 64960 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 110357 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 133056 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243413 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112492 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 135154 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247646 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9358828 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 9831902 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19190730 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9394257 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 9861433 # number of overall hits -system.cpu0.dcache.overall_hits::total 19255690 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 296259 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 395495 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 691754 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1362667 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1717725 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3080392 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 74316 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 54156 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 128472 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6370 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6955 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13325 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1658926 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2113220 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3772146 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1733242 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2167376 # number of overall misses -system.cpu0.dcache.overall_misses::total 3900618 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4388776307 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5728170629 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 10116946936 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57800783004 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 86624659870 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 144425442874 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92286740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 93793740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 186080480 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 13000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 62189559311 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 92352830499 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 154542389810 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 62189559311 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 92352830499 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 154542389810 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6149164 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6589919 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12739083 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4868590 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5355203 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223793 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 109745 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 83687 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 193432 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 116727 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 140011 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256738 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 112494 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 135155 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247649 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11017754 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11945122 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 22962876 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11127499 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12028809 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23156308 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048179 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060015 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.054302 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.279889 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.320758 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.301296 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.677170 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.647126 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.664171 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054572 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049675 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.051901 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000018 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000007 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150568 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.176911 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.164271 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.155762 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.180182 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.168447 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14813.984746 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14483.547527 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14625.064598 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42417.393981 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50429.876651 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 46885.410322 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14487.714286 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13485.800144 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13964.763977 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37487.844130 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 43702.421186 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 40969.355325 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35880.482536 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42610.433307 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39619.975555 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 200600 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 41919 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 27184 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 783 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.379341 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 53.536398 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 189863403 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189863403 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12602173 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12737013 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25339186 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7727036 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 8174827 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15901863 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180867 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 181606 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 362473 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 207945 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 238852 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 446797 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 213795 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 245624 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459419 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20329209 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20911840 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41241049 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20510076 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21093446 # number of overall hits +system.cpu0.dcache.overall_hits::total 41603522 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 421777 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 407630 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 829407 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1909127 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1794923 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 3704050 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 96495 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 85144 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 181639 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13429 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14216 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 27645 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 47 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 68 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2330904 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 2202553 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4533457 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2427399 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 2287697 # number of overall misses +system.cpu0.dcache.overall_misses::total 4715096 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7013958136 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6635684452 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13649642588 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84643454348 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 74838228910 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 159481683258 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 181700494 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 211428245 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 393128739 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 350006 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 828017 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 1178023 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 91657412484 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 81473913362 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 173131325846 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 91657412484 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 81473913362 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 173131325846 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 13023950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 13144643 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26168593 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9636163 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9969750 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19605913 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 277362 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 266750 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 544112 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 221374 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 253068 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 474442 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 213816 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 245671 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 459487 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 22660113 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 23114393 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 45774506 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 22937475 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 23381143 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 46318618 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032385 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031011 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031695 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.198121 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.180037 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.188925 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.347903 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.319190 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.333826 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060662 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056175 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058268 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000098 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000191 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000148 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.102864 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.095289 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.099039 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.105827 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.097844 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.101797 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16629.541525 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16278.695022 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16457.110427 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44336.209350 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41694.395197 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43056.028741 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13530.456028 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14872.555219 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14220.609116 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16666.952381 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17617.382979 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17323.867647 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39322.688744 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 36990.670990 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 38189.691850 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37759.516455 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35613.944225 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36718.515561 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1117471 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 160932 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 70035 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 2415 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.955893 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 66.638509 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 606482 # number of writebacks -system.cpu0.dcache.writebacks::total 606482 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 164188 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 218355 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 382543 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1249592 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1581925 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2831517 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 626 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 765 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1391 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1413780 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1800280 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3214060 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1413780 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1800280 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3214060 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 132071 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 177140 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 309211 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 113075 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 135800 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248875 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 43244 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 31809 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 75053 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5744 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6190 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11934 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 245146 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 312940 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 558086 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 288390 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 344749 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 633139 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1730710058 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2210787235 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3941497293 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4783325934 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6576818347 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11360144281 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 814553760 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 636336252 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1450890012 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72971510 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72018008 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 144989518 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6514035992 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8787605582 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15301641574 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7328589752 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9423941834 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16752531586 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91416176750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90920349500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336526250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 11961680895 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14731919998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26693600893 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103377857645 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105652269498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030127143 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021478 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026880 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024273 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023225 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025359 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.394041 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.380095 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.388007 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049209 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044211 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046483 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000018 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000007 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.022250 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026198 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024304 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028660 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027342 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13104.391259 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12480.451818 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12746.950442 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42302.241291 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48430.179286 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45645.984052 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18836.226066 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20004.912195 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19331.539206 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12703.953691 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11634.573183 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12149.280878 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26572.067225 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 28080.800096 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27418.071003 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25412.080003 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27335.661116 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26459.484546 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 703572 # number of writebacks +system.cpu0.dcache.writebacks::total 703572 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 210384 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 193413 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 403797 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1755618 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1648654 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3404272 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9415 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8951 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18366 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1966002 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1842067 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3808069 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1966002 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1842067 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3808069 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 211393 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 214217 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 425610 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 153509 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 146269 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 299778 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 63030 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58365 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 121395 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4014 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5265 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9279 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 47 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 68 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 364902 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 360486 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 725388 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 427932 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 418851 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 846783 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2857072417 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2926033619 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5783106036 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6788582559 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6159862377 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12948444936 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 975244760 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 899933504 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1875178264 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 46933501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81366752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 128300253 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 307994 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 733983 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1041977 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9645654976 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9085895996 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 18731550972 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10620899736 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9985829500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 20606729236 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3170906750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2613622501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784529251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2427957377 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2008001500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4435958877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5598864127 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4621624001 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220488128 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016231 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016297 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016264 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015931 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014671 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015290 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227248 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.218800 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223107 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018132 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020805 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019558 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000098 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000191 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000148 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016103 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015596 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015847 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018656 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017914 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018282 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13515.454235 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13659.203607 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.805822 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44222.700682 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42113.245985 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43193.446270 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15472.707600 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15419.061150 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15446.915145 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11692.451669 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15454.273884 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13826.948270 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14666.380952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15616.659574 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15323.191176 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26433.549216 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25204.573814 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25822.802379 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24819.129525 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23841.006706 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24335.312868 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1758,15 +1802,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8293404 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6173471 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 340831 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5168505 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4065400 # Number of BTB hits +system.cpu1.branchPred.lookups 27347291 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14229080 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 552926 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17264130 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 12844736 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 78.657175 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 881063 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 23561 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 74.401293 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6762355 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29663 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1790,25 +1834,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 28281448 # DTB read hits -system.cpu1.dtb.read_misses 40913 # DTB read misses -system.cpu1.dtb.write_hits 6183126 # DTB write hits -system.cpu1.dtb.write_misses 14267 # DTB write misses -system.cpu1.dtb.flush_tlb 506 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5407 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 858 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch +system.cpu1.dtb.read_hits 14380313 # DTB read hits +system.cpu1.dtb.read_misses 50338 # DTB read misses +system.cpu1.dtb.write_hits 10697385 # DTB write hits +system.cpu1.dtb.write_misses 9618 # DTB write misses +system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 443 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 785 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1275 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 709 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 28322361 # DTB read accesses -system.cpu1.dtb.write_accesses 6197393 # DTB write accesses +system.cpu1.dtb.perms_faults 552 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14430651 # DTB read accesses +system.cpu1.dtb.write_accesses 10707003 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 34464574 # DTB hits -system.cpu1.dtb.misses 55180 # DTB misses -system.cpu1.dtb.accesses 34519754 # DTB accesses +system.cpu1.dtb.hits 25077698 # DTB hits +system.cpu1.dtb.misses 59956 # DTB misses +system.cpu1.dtb.accesses 25137654 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1830,356 +1874,416 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5686404 # ITB inst hits -system.cpu1.itb.inst_misses 8235 # ITB inst misses +system.cpu1.itb.inst_hits 20651138 # ITB inst hits +system.cpu1.itb.inst_misses 8123 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 506 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 443 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2271 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2705 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1349 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5694639 # ITB inst accesses -system.cpu1.itb.hits 5686404 # DTB hits -system.cpu1.itb.misses 8235 # DTB misses -system.cpu1.itb.accesses 5694639 # DTB accesses -system.cpu1.numCycles 237046957 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20659261 # ITB inst accesses +system.cpu1.itb.hits 20651138 # DTB hits +system.cpu1.itb.misses 8123 # DTB misses +system.cpu1.itb.accesses 20659261 # DTB accesses +system.cpu1.numCycles 107249974 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15347817 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 44890949 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8293404 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4946463 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 217272167 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 945647 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 107708 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 1915 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1869 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 102411 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 2087291 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5683206 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 214159 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3400 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 235393992 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.228723 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.188286 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40725468 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 106761765 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27347291 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19607091 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 61565472 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3230729 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 119361 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 4162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 473 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 476136 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 133238 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20649355 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 381272 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3428 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104639861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.227831 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.325701 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 225080067 95.62% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 947919 0.40% 96.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1046635 0.44% 96.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1047767 0.45% 96.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1244626 0.53% 97.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 829831 0.35% 97.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1297650 0.55% 98.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 454057 0.19% 98.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3445440 1.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 75287195 71.95% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3919090 3.75% 75.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2500009 2.39% 78.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8110720 7.75% 85.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1591501 1.52% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1177075 1.12% 88.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6154172 5.88% 94.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1148436 1.10% 95.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4751663 4.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 235393992 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.034986 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.189376 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 12555511 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 214484659 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 6498538 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1464859 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 388308 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1045918 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85921 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 48232824 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 288029 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 388308 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 13237235 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 54097542 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 31323893 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 7199069 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 129145928 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 46754074 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 1435 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 95558668 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 124530529 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 2374363 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 49626992 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 215510826 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 57366811 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 4976 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39600958 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 10026026 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 608668 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 515191 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8234978 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 8452340 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6808261 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1032874 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1526046 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 44303656 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1049317 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62721282 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 61124 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 7218810 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 16029580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 286052 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 235393992 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.266452 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.981415 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 104639861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.254986 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.995448 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27852312 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 57848791 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15754577 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1718968 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1464898 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1977106 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 152502 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 89215039 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 494329 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1464898 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28797360 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 6699621 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 45356537 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16519675 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 5801450 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 85333745 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2191 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1572004 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 242988 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 3188310 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 88168045 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 393456751 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 95320905 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6151 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 74288331 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13879714 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1591572 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1490290 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10044487 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15194391 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11866887 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2182296 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2756146 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 82055126 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1162203 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 78681977 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 95018 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10109005 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25435903 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 107068 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104639861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.751931 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.430939 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 213794873 90.82% 90.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6639662 2.82% 93.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3193505 1.36% 95.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2580445 1.10% 96.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6412648 2.72% 98.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1155018 0.49% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1003845 0.43% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 407445 0.17% 99.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 206551 0.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72959997 69.72% 69.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10709404 10.23% 79.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8056823 7.70% 87.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6679323 6.38% 94.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2498342 2.39% 96.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1545149 1.48% 97.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1464114 1.40% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 496511 0.47% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 230198 0.22% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 235393992 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104639861 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 146677 2.81% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4785763 91.77% 94.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 282272 5.41% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 103205 8.90% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 5 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 536017 46.20% 55.10% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 520896 44.90% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 13498 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 27514443 43.87% 43.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46382 0.07% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.96% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1213 0.00% 43.97% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.97% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.97% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.97% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 28642016 45.67% 89.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6503730 10.37% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 137 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 52524607 66.76% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 58923 0.07% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4123 0.01% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14785011 18.79% 85.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11309172 14.37% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62721282 # Type of FU issued -system.cpu1.iq.rate 0.264594 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 5214715 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.083141 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 366100496 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 52588764 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41277568 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11899 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6202 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5156 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 67916046 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 226153 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 78681977 # Type of FU issued +system.cpu1.iq.rate 0.733632 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1160123 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014744 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 263245129 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 93371477 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 76291260 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 13827 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7286 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6040 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 79834510 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7453 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 367216 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1459547 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2673 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 24270 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 647934 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2201674 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2649 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 53639 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1152377 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17097171 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3878321 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 193043 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 153958 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 388308 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 50150951 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 3201381 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 45487056 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 83691 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 8452340 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6808261 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 746320 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 150012 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2969807 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 24270 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 165680 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 138748 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 304428 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 62296746 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 28474223 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 369499 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1464898 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4313031 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2150253 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 83357725 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 132748 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15194391 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11866887 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 585663 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 47230 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2090333 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 53639 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 255743 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 221088 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 476831 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 78071744 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14543565 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 550444 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 134083 # number of nop insts executed -system.cpu1.iew.exec_refs 34908741 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6065757 # Number of branches executed -system.cpu1.iew.exec_stores 6434518 # Number of stores executed -system.cpu1.iew.exec_rate 0.262803 # Inst execution rate -system.cpu1.iew.wb_sent 58446379 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41282724 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23334628 # num instructions producing a value -system.cpu1.iew.wb_consumers 41837805 # num instructions consuming a value +system.cpu1.iew.exec_nop 140396 # number of nop insts executed +system.cpu1.iew.exec_refs 25744293 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14514927 # Number of branches executed +system.cpu1.iew.exec_stores 11200728 # Number of stores executed +system.cpu1.iew.exec_rate 0.727942 # Inst execution rate +system.cpu1.iew.wb_sent 77444184 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 76297300 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 39931831 # num instructions producing a value +system.cpu1.iew.wb_consumers 69996884 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.174154 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.557740 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.711397 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.570480 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 7166738 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 763265 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 256189 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 234203986 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.162086 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 0.884581 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11439631 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1055135 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 402423 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 102076918 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.704421 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.588048 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 220778060 94.27% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6743716 2.88% 97.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1772623 0.76% 97.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1087484 0.46% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 731864 0.31% 98.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 647370 0.28% 98.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 507514 0.22% 99.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 282341 0.12% 99.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1653014 0.71% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 73994277 72.49% 72.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12594887 12.34% 84.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6447399 6.32% 91.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2674121 2.62% 93.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1416644 1.39% 95.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 932745 0.91% 96.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1821915 1.78% 97.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 428135 0.42% 98.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1766795 1.73% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 234203986 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31407169 # Number of instructions committed -system.cpu1.commit.committedOps 37961303 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 102076918 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 59223599 # Number of instructions committed +system.cpu1.commit.committedOps 71905144 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13153120 # Number of memory references committed -system.cpu1.commit.loads 6992793 # Number of loads committed -system.cpu1.commit.membars 210663 # Number of memory barriers committed -system.cpu1.commit.branches 5351172 # Number of branches committed -system.cpu1.commit.fp_insts 5118 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33489601 # Number of committed integer instructions. -system.cpu1.commit.function_calls 519360 # Number of function calls committed. +system.cpu1.commit.refs 23707227 # Number of memory references committed +system.cpu1.commit.loads 12992717 # Number of loads committed +system.cpu1.commit.membars 441930 # Number of memory barriers committed +system.cpu1.commit.branches 13739507 # Number of branches committed +system.cpu1.commit.fp_insts 5965 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 63021848 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2684059 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 24763487 65.23% 65.23% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 43483 0.11% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 1213 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 6992793 18.42% 83.77% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6160327 16.23% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 48136675 66.94% 66.94% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57123 0.08% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4119 0.01% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 12992717 18.07% 85.10% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10714510 14.90% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 37961303 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1653014 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 71905144 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1766795 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 276729293 # The number of ROB reads -system.cpu1.rob.rob_writes 91408516 # The number of ROB writes -system.cpu1.timesIdled 270232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1652965 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2279190242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31323407 # Number of Instructions Simulated -system.cpu1.committedOps 37877541 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 7.567726 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.567726 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.132140 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.132140 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 71111518 # number of integer regfile reads -system.cpu1.int_regfile_writes 26004877 # number of integer regfile writes -system.cpu1.fp_regfile_reads 44415 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42120 # number of floating regfile writes -system.cpu1.cc_regfile_reads 209232786 # number of cc regfile reads -system.cpu1.cc_regfile_writes 17062784 # number of cc regfile writes -system.cpu1.misc_regfile_reads 298304880 # number of misc regfile reads -system.cpu1.misc_regfile_writes 608841 # number of misc regfile writes -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.cpu1.rob.rob_reads 171176371 # The number of ROB reads +system.cpu1.rob.rob_writes 169257009 # The number of ROB writes +system.cpu1.timesIdled 392905 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2610113 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2951402872 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 59140577 # Number of Instructions Simulated +system.cpu1.committedOps 71822122 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.813475 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.813475 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.551427 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.551427 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 84961864 # number of integer regfile reads +system.cpu1.int_regfile_writes 48575931 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16615 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13105 # number of floating regfile writes +system.cpu1.cc_regfile_reads 275730923 # number of cc regfile reads +system.cpu1.cc_regfile_writes 28983730 # number of cc regfile writes +system.cpu1.misc_regfile_reads 192710320 # number of misc regfile reads +system.cpu1.misc_regfile_writes 799493 # number of misc regfile writes +system.iocache.tags.replacements 36423 # number of replacements +system.iocache.tags.tagsinuse 0.982033 # Cycle average of tags in use +system.iocache.tags.total_refs 16 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 234020639000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.982033 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061377 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061377 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328241 # Number of tag accesses +system.iocache.tags.data_accesses 328241 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses +system.iocache.ReadReq_misses::total 249 # number of ReadReq misses +system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses +system.iocache.demand_misses::total 249 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 249 # number of overall misses +system.iocache.overall_misses::total 249 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 29659377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29659377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29659377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29659377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29659377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29659377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 119113.963855 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119113.963855 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119113.963855 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119113.963855 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119113.963855 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1732753268848 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1732753268848 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16710377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16710377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2222587461 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2222587461 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16710377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16710377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16710377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16710377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67109.947791 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67109.947791 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83356 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal Binary files differindex 46f8f01b2..b3be0ec54 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 8b812b09c..be576cc47 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -11,18 +11,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +atags_addr=134217728 +boot_loader=/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename= +dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 -flags_addr=268435504 -gic_cpu_addr=520093952 +flags_addr=469827632 +gic_cpu_addr=738205696 have_generic_timer=false have_large_asid_64=false have_lpae=false @@ -30,20 +30,20 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 -load_offset=0 -machine_type=RealView_PBX +load_offset=2147483648 +machine_type=VExpress_EMM mem_mode=timing -mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +mem_ranges=2147483648:2415919103 +memories=system.physmem system.realview.nvmem system.realview.vram multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -53,14 +53,14 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.slave[0] +system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=268435456:520093695 1073741824:1610612735 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -86,7 +86,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -274,6 +274,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu0.istage2_mmu] @@ -420,6 +421,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu1.istage2_mmu] @@ -491,15 +493,16 @@ type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 -use_default_range=false +use_default_range=true width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] type=BaseCache children=tags -addr_ranges=0:134217727 +addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain eventq_index=0 @@ -518,8 +521,8 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[26] -mem_side=system.membus.slave[2] +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] [system.iocache.tags] type=LRU @@ -554,7 +557,7 @@ tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c.tags] type=LRU @@ -577,8 +580,8 @@ system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -634,6 +637,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -643,7 +647,7 @@ mem_sched_policy=frfcfs min_writes_per_switch=16 null=false page_policy=open_adaptive -range=0:134217727 +range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -672,46 +676,37 @@ tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 -port=system.membus.master[6] +port=system.membus.master[5] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=0 +pci_cfg_base=805306368 pci_cfg_gen_offsets=false pci_io_base=0 system=system -[system.realview.a9scu] -type=A9SCU -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=520093696 -pio_latency=100000 -system=system -pio=system.membus.master[4] - [system.realview.aaci_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268451840 +pio_addr=470024192 pio_latency=100000 system=system -pio=system.iobus.master[21] +pio=system.iobus.master[18] [system.realview.cf_ctrl] type=IdeController -BAR0=402653184 +BAR0=471465984 BAR0LegacyIO=true -BAR0Size=16 -BAR1=402653440 +BAR0Size=256 +BAR1=471466240 BAR1LegacyIO=true -BAR1Size=1 +BAR1Size=4096 BAR2=1 BAR2LegacyIO=false BAR2Size=8 @@ -781,18 +776,18 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 -disks=system.cf0 +disks= eventq_index=0 -io_shift=1 +io_shift=2 pci_bus=2 -pci_dev=7 +pci_dev=0 pci_func=0 pio_latency=30000 platform=system.realview system=system -config=system.iobus.master[8] +config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.clcd] type=Pl111 @@ -801,8 +796,8 @@ clk_domain=system.clk_domain enable_capture=true eventq_index=0 gic=system.realview.gic -int_num=55 -pio_addr=268566528 +int_num=46 +pio_addr=471793664 pio_latency=10000 pixel_clock=41667 system=system @@ -810,51 +805,129 @@ vnc=system.vncserver dma=system.iobus.slave[1] pio=system.iobus.master[4] -[system.realview.dmac_fake] -type=AmbaFake -amba_id=0 +[system.realview.energy_ctrl] +type=EnergyCtrl clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler eventq_index=0 -ignore_access=false -pio_addr=268632064 +pio_addr=470286336 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[22] -[system.realview.energy_ctrl] -type=EnergyCtrl +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 clk_domain=system.clk_domain -dvfs_handler=system.dvfs_handler +config_latency=20000 eventq_index=0 -pio_addr=268496896 -pio_latency=100000 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] pio=system.iobus.master[25] -[system.realview.flash_fake] -type=IsaFake -clk_domain=system.clk_domain +[system.realview.generic_timer] +type=GenericTimer eventq_index=0 -fake_mem=true -pio_addr=1073741824 -pio_latency=100000 -pio_size=536870912 -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 +gic=system.realview.gic +int_num=29 system=system -update_data=false -warn_access= -pio=system.iobus.master[24] [system.realview.gic] type=Pl390 clk_domain=system.clk_domain -cpu_addr=520093952 +cpu_addr=738205696 cpu_pio_delay=10000 -dist_addr=520097792 +dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 int_latency=10000 @@ -864,38 +937,111 @@ platform=system.realview system=system pio=system.membus.master[2] -[system.realview.gpio0_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268513280 -pio_latency=100000 -system=system -pio=system.iobus.master[16] - -[system.realview.gpio1_fake] -type=AmbaFake -amba_id=0 +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 clk_domain=system.clk_domain +enable_capture=true eventq_index=0 -ignore_access=false -pio_addr=268517376 -pio_latency=100000 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 system=system -pio=system.iobus.master[17] +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] -[system.realview.gpio2_fake] -type=AmbaFake -amba_id=0 +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 eventq_index=0 -ignore_access=false -pio_addr=268521472 -pio_latency=100000 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview system=system -pio=system.iobus.master[18] +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] [system.realview.kmi0] type=Pl050 @@ -904,13 +1050,13 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=52 +int_num=44 is_mouse=false -pio_addr=268460032 +pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.kmi1] type=Pl050 @@ -919,20 +1065,20 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=1000000 -int_num=53 +int_num=45 is_mouse=true -pio_addr=268464128 +pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain eventq_index=0 fake_mem=false -pio_addr=520101888 +pio_addr=739246080 pio_latency=100000 pio_size=4095 ret_bad_addr=false @@ -943,7 +1089,25 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.membus.master[3] +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer @@ -952,10 +1116,10 @@ eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 -pio_addr=520095232 +pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[5] +pio=system.membus.master[3] [system.realview.mmc_fake] type=AmbaFake @@ -963,10 +1127,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268455936 +pio_addr=470089728 pio_latency=100000 system=system -pio=system.iobus.master[22] +pio=system.iobus.master[21] [system.realview.nvmem] type=SimpleMemory @@ -978,18 +1142,30 @@ in_addr_map=true latency=30000 latency_var=0 null=false -range=2147483648:2214592511 +range=0:67108863 port=system.membus.master[1] +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain eventq_index=0 -idreg=0 -pio_addr=268435456 +idreg=35979264 +pio_addr=469827584 pio_latency=100000 -proc_id0=201326592 -proc_id1=201327138 +proc_id0=335544320 +proc_id1=335544320 system=system pio=system.iobus.master[1] @@ -1000,34 +1176,12 @@ clk_domain=system.clk_domain eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=42 -pio_addr=268529664 +int_num=36 +pio_addr=471269376 pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[23] - -[system.realview.sci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268492800 -pio_latency=100000 -system=system -pio=system.iobus.master[20] - -[system.realview.smc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=269357056 -pio_latency=100000 -system=system -pio=system.iobus.master[13] +pio=system.iobus.master[10] [system.realview.sp810_fake] type=AmbaFake @@ -1035,21 +1189,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=true -pio_addr=268439552 -pio_latency=100000 -system=system -pio=system.iobus.master[14] - -[system.realview.ssp_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -eventq_index=0 -ignore_access=false -pio_addr=268488704 +pio_addr=469893120 pio_latency=100000 system=system -pio=system.iobus.master[19] +pio=system.iobus.master[16] [system.realview.timer0] type=Sp804 @@ -1059,9 +1202,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=36 -int_num1=36 -pio_addr=268505088 +int_num0=34 +int_num1=34 +pio_addr=470876160 pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1074,9 +1217,9 @@ clock0=1000000 clock1=1000000 eventq_index=0 gic=system.realview.gic -int_num0=37 -int_num1=37 -pio_addr=268509184 +int_num0=35 +int_num1=35 +pio_addr=470941696 pio_latency=100000 system=system pio=system.iobus.master[3] @@ -1088,8 +1231,8 @@ end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 -int_num=44 -pio_addr=268472320 +int_num=37 +pio_addr=470351872 pio_latency=100000 platform=system.realview system=system @@ -1102,10 +1245,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268476416 +pio_addr=470417408 pio_latency=100000 system=system -pio=system.iobus.master[10] +pio=system.iobus.master[13] [system.realview.uart2_fake] type=AmbaFake @@ -1113,10 +1256,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268480512 +pio_addr=470482944 pio_latency=100000 system=system -pio=system.iobus.master[11] +pio=system.iobus.master[14] [system.realview.uart3_fake] type=AmbaFake @@ -1124,10 +1267,54 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268484608 +pio_addr=470548480 pio_latency=100000 system=system -pio=system.iobus.master[12] +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] [system.realview.watchdog_fake] type=AmbaFake @@ -1135,10 +1322,10 @@ amba_id=0 clk_domain=system.clk_domain eventq_index=0 ignore_access=false -pio_addr=268500992 +pio_addr=470745088 pio_latency=100000 system=system -pio=system.iobus.master[15] +pio=system.iobus.master[17] [system.terminal] type=Terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr index 86ac9e4e4..067647ddd 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr @@ -1,20 +1,36 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: Not doing anything for miscreg ACTLR +warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: LCD dual screen mode not supported -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] +warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] +warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] +warn: Returning zero for read from miscreg pmcr +warn: Ignoring write to miscreg pmcntenclr +warn: Ignoring write to miscreg pmintenclr +warn: Ignoring write to miscreg pmovsr +warn: Ignoring write to miscreg pmcr warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout index 16dc9f3ee..787f38780 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 19:11:44 +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:26:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x6f57400 0x6f57400 - 0: system.cpu1.isa: ISA system set to: 0x6f57400 0x6f57400 + 0: system.cpu0.isa: ISA system set to: 0x3fa4b00 0x3fa4b00 + 0: system.cpu1.isa: ISA system set to: 0x3fa4b00 0x3fa4b00 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 3aad6c8ee..e78ea31b3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,148 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.627904 # Number of seconds simulated -sim_ticks 2627903712000 # Number of ticks simulated -final_tick 2627903712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.904683 # Number of seconds simulated +sim_ticks 2904682547500 # Number of ticks simulated +final_tick 2904682547500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 449186 # Simulator instruction rate (inst/s) -host_op_rate 536465 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19602826894 # Simulator tick rate (ticks/s) -host_mem_usage 462988 # Number of bytes of host memory used -host_seconds 134.06 # Real time elapsed on the host -sim_insts 60216663 # Number of instructions simulated -sim_ops 71917112 # Number of ops (including micro ops) simulated +host_inst_rate 708228 # Simulator instruction rate (inst/s) +host_op_rate 853902 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18288406087 # Simulator tick rate (ticks/s) +host_mem_usage 555560 # Number of bytes of host memory used +host_seconds 158.83 # Real time elapsed on the host +sim_insts 112485368 # Number of instructions simulated +sim_ops 135622164 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 306056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4559448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 399872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4486720 # Number of bytes read from this memory -system.physmem.bytes_read::total 134008544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 306056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 399872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3673856 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1536536 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1479536 # Number of bytes written to this memory -system.physmem.bytes_written::total 6689928 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 71267 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6248 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 70105 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690649 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57404 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 384134 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 369884 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811422 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47283413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 116464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1735013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 152164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1707338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50994465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 116464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 152164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268628 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1398018 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 584700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 563010 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2545728 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1398018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47283413 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 116464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2319714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 152164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2270348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53540193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690649 # Number of read requests accepted -system.physmem.writeReqs 811422 # Number of write requests accepted -system.physmem.readBursts 15690649 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811422 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004200960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 6711168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134008544 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6689928 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706554 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 980414 # Per bank write bursts -system.physmem.perBankRdBursts::1 980044 # Per bank write bursts -system.physmem.perBankRdBursts::2 979984 # Per bank write bursts -system.physmem.perBankRdBursts::3 980262 # Per bank write bursts -system.physmem.perBankRdBursts::4 986671 # Per bank write bursts -system.physmem.perBankRdBursts::5 980424 # Per bank write bursts -system.physmem.perBankRdBursts::6 980555 # Per bank write bursts -system.physmem.perBankRdBursts::7 980428 # Per bank write bursts -system.physmem.perBankRdBursts::8 980781 # Per bank write bursts -system.physmem.perBankRdBursts::9 980432 # Per bank write bursts -system.physmem.perBankRdBursts::10 979731 # Per bank write bursts -system.physmem.perBankRdBursts::11 979566 # Per bank write bursts -system.physmem.perBankRdBursts::12 980337 # Per bank write bursts -system.physmem.perBankRdBursts::13 980248 # Per bank write bursts -system.physmem.perBankRdBursts::14 980396 # Per bank write bursts -system.physmem.perBankRdBursts::15 980367 # Per bank write bursts -system.physmem.perBankWrBursts::0 6669 # Per bank write bursts -system.physmem.perBankWrBursts::1 6337 # Per bank write bursts -system.physmem.perBankWrBursts::2 6309 # Per bank write bursts -system.physmem.perBankWrBursts::3 6427 # Per bank write bursts -system.physmem.perBankWrBursts::4 6393 # Per bank write bursts -system.physmem.perBankWrBursts::5 6675 # Per bank write bursts -system.physmem.perBankWrBursts::6 6845 # Per bank write bursts -system.physmem.perBankWrBursts::7 6769 # Per bank write bursts -system.physmem.perBankWrBursts::8 7058 # Per bank write bursts -system.physmem.perBankWrBursts::9 6682 # Per bank write bursts -system.physmem.perBankWrBursts::10 6146 # Per bank write bursts -system.physmem.perBankWrBursts::11 6016 # Per bank write bursts -system.physmem.perBankWrBursts::12 6658 # Per bank write bursts -system.physmem.perBankWrBursts::13 6472 # Per bank write bursts -system.physmem.perBankWrBursts::14 6707 # Per bank write bursts -system.physmem.perBankWrBursts::15 6699 # Per bank write bursts +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 557732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4265248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 631552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4773892 # Number of bytes read from this memory +system.physmem.bytes_read::total 10229960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 557732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 631552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1189284 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5300352 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory +system.physmem.bytes_written::total 7636212 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17168 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9868 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74593 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168816 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 82818 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123423 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 192011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1468404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 217425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1643516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3521886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 192011 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 217425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 409437 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1824761 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 798137 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2628932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1824761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 798468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 192011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1474434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 217425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1643519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6150817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168816 # Number of read requests accepted +system.physmem.writeReqs 123423 # Number of write requests accepted +system.physmem.readBursts 168816 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123423 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10794880 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 7651200 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10229960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7636212 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4512 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9768 # Per bank write bursts +system.physmem.perBankRdBursts::1 9653 # Per bank write bursts +system.physmem.perBankRdBursts::2 10324 # Per bank write bursts +system.physmem.perBankRdBursts::3 9994 # Per bank write bursts +system.physmem.perBankRdBursts::4 18675 # Per bank write bursts +system.physmem.perBankRdBursts::5 10148 # Per bank write bursts +system.physmem.perBankRdBursts::6 10372 # Per bank write bursts +system.physmem.perBankRdBursts::7 10429 # Per bank write bursts +system.physmem.perBankRdBursts::8 9938 # Per bank write bursts +system.physmem.perBankRdBursts::9 10451 # Per bank write bursts +system.physmem.perBankRdBursts::10 9811 # Per bank write bursts +system.physmem.perBankRdBursts::11 9561 # Per bank write bursts +system.physmem.perBankRdBursts::12 9986 # Per bank write bursts +system.physmem.perBankRdBursts::13 9803 # Per bank write bursts +system.physmem.perBankRdBursts::14 9966 # Per bank write bursts +system.physmem.perBankRdBursts::15 9791 # Per bank write bursts +system.physmem.perBankWrBursts::0 7253 # Per bank write bursts +system.physmem.perBankWrBursts::1 7191 # Per bank write bursts +system.physmem.perBankWrBursts::2 8157 # Per bank write bursts +system.physmem.perBankWrBursts::3 7614 # Per bank write bursts +system.physmem.perBankWrBursts::4 7092 # Per bank write bursts +system.physmem.perBankWrBursts::5 7380 # Per bank write bursts +system.physmem.perBankWrBursts::6 7560 # Per bank write bursts +system.physmem.perBankWrBursts::7 7725 # Per bank write bursts +system.physmem.perBankWrBursts::8 7575 # Per bank write bursts +system.physmem.perBankWrBursts::9 8007 # Per bank write bursts +system.physmem.perBankWrBursts::10 7415 # Per bank write bursts +system.physmem.perBankWrBursts::11 7436 # Per bank write bursts +system.physmem.perBankWrBursts::12 7462 # Per bank write bursts +system.physmem.perBankWrBursts::13 7248 # Per bank write bursts +system.physmem.perBankWrBursts::14 7309 # Per bank write bursts +system.physmem.perBankWrBursts::15 7126 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2627899414000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2904682126000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6644 # Read request sizes (log2) -system.physmem.readPktSize::3 15532042 # Read request sizes (log2) +system.physmem.readPktSize::2 9558 # Read request sizes (log2) +system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 151963 # Read request sizes (log2) +system.physmem.readPktSize::6 159244 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57404 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1139478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 982369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 987635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1091943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 997696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1062131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2775683 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2686264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3513182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 100216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 94857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 91541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 119042 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -157,453 +164,470 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1040215 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.829985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 906.043406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 203.863923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22728 2.18% 2.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22848 2.20% 4.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9187 0.88% 5.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2378 0.23% 5.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2112 0.20% 5.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1712 0.16% 5.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9383 0.90% 6.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 867 0.08% 6.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 969000 93.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1040215 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6002 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2614.234255 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 48623.103038 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 5977 99.58% 99.58% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 9 0.15% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6002 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6002 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.471176 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.313667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.128575 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 1 0.02% 0.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 5 0.08% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 9 0.15% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 6 0.10% 0.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.02% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 2 0.03% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 2 0.03% 0.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 6 0.10% 0.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.05% 0.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 2 0.03% 0.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 2 0.03% 0.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 2 0.03% 0.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 2 0.03% 0.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 12 0.20% 0.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2065 34.41% 35.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 28 0.47% 35.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3575 59.56% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 74 1.23% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 26 0.43% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 13 0.22% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 8 0.13% 97.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 17 0.28% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 20 0.33% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 23 0.38% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 19 0.32% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 14 0.23% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 21 0.35% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.10% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 12 0.20% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.17% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6002 # Writes before turning the bus around for reads -system.physmem.totQLat 402684411250 # Total ticks spent queuing -system.physmem.totMemAccLat 696883911250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78453200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25663.99 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58497 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 315.331590 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.690243 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.870742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21229 36.29% 36.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14764 25.24% 61.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5739 9.81% 71.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3179 5.43% 76.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2288 3.91% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1563 2.67% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1023 1.75% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1098 1.88% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7614 13.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58497 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.752472 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.127013 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5865 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5866 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.380157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.599784 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.515949 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 10 0.17% 0.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 13 0.22% 0.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 18 0.31% 0.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4930 84.04% 85.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 59 1.01% 86.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 57 0.97% 86.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 249 4.24% 91.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 210 3.58% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.34% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 11 0.19% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.14% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 30 0.51% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.09% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.07% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.05% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 157 2.68% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 19 0.32% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 6 0.10% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.10% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 6 0.10% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.12% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5866 # Writes before turning the bus around for reads +system.physmem.totQLat 1486718500 # Total ticks spent queuing +system.physmem.totMemAccLat 4649281000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 843350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8814.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44413.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 382.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27564.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.01 # Data bus utilization in percentage -system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 16.63 # Average write queue length when enqueuing -system.physmem.readRowHits 14667378 # Number of row buffer hits during reads -system.physmem.writeRowHits 87909 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.83 # Row buffer hit rate for writes -system.physmem.avgGap 159246.64 # Average gap between requests -system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2254944154750 # Time in different power states -system.physmem.memoryStateTime::REF 87751300000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.56 # Average write queue length when enqueuing +system.physmem.readRowHits 139009 # Number of row buffer hits during reads +system.physmem.writeRowHits 90713 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.41 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.88 # Row buffer hit rate for writes +system.physmem.avgGap 9939406.19 # Average gap between requests +system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2756104323000 # Time in different power states +system.physmem.memoryStateTime::REF 96993520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 285203111500 # Time in different power states +system.physmem.memoryStateTime::ACT 51578552000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3933127800 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3930897600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2146051875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2144835000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 61220499600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 61166492400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 339707520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 339798240 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 171641542800 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 171641542800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 154602145665 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 155429248725 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1441123214250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1440397685250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1835006289510 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1835050500015 # Total energy per rank (pJ) -system.physmem.averagePower::0 698.278968 # Core power per rank (mW) -system.physmem.averagePower::1 698.295792 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.physmem.actEnergy::0 224721000 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 217516320 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 122615625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 118684500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 697031400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 618579000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 388618560 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 386065440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 189719325120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 189719325120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 86947680015 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 86005039095 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1666535934000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1667362812000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1944635925720 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1944428021475 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.484538 # Core power per rank (mW) +system.physmem.averagePower::1 669.412962 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16743265 # Transaction distribution -system.membus.trans_dist::ReadResp 16743265 # Transaction distribution -system.membus.trans_dist::WriteReq 763389 # Transaction distribution -system.membus.trans_dist::WriteResp 763389 # Transaction distribution -system.membus.trans_dist::Writeback 57404 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution -system.membus.trans_dist::ReadExReq 131496 # Transaction distribution -system.membus.trans_dist::ReadExResp 131496 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383094 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1891706 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4278672 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35342736 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390554 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16442216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18840514 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 143096770 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 213883 # Request fanout histogram +system.membus.trans_dist::ReadReq 70577 # Transaction distribution +system.membus.trans_dist::ReadResp 70577 # Transaction distribution +system.membus.trans_dist::WriteReq 27613 # Transaction distribution +system.membus.trans_dist::WriteResp 27613 # Transaction distribution +system.membus.trans_dist::Writeback 82818 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4510 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4512 # Transaction distribution +system.membus.trans_dist::ReadExReq 129059 # Transaction distribution +system.membus.trans_dist::ReadExResp 129059 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 545872 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 618569 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15710305 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18029601 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 219 # Total snoops (count) +system.membus.snoop_fanout::samples 283020 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 213883 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 283020 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 213883 # Request fanout histogram -system.membus.reqLayer0.occupancy 1223591000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 283020 # Request fanout histogram +system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3677500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1735500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171099000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4987168321 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 38457119250 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.5 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1336695500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1640330738 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 61855 # number of replacements -system.l2c.tags.tagsinuse 50930.330896 # Cycle average of tags in use -system.l2c.tags.total_refs 1699074 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127234 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.353931 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574032162000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37932.108407 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2848.249708 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3170.076160 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4147.610246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2832.285487 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.578798 # Average percentage of cache occupancy +system.l2c.tags.replacements 89435 # number of replacements +system.l2c.tags.tagsinuse 64928.071050 # Cycle average of tags in use +system.l2c.tags.total_refs 2766017 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 154676 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.882651 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 50556.019026 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943993 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3889.866505 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2064.899937 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768384 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5760.330467 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2651.242275 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.771424 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.043461 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048372 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.063288 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.043217 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.777135 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6516 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56686 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17278829 # Number of tag accesses -system.l2c.tags.data_accesses 17278829 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9065 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3142 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 447117 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 182266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10696 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4002 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 397485 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 188475 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242248 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596597 # number of Writeback hits -system.l2c.Writeback_hits::total 596597 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57734 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56826 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114560 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9065 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3142 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 447117 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 240000 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10696 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4002 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 397485 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 245301 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356808 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9065 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3142 # number of overall hits -system.l2c.overall_hits::cpu0.inst 447117 # number of overall hits -system.l2c.overall_hits::cpu0.data 240000 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10696 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4002 # number of overall hits -system.l2c.overall_hits::cpu1.inst 397485 # number of overall hits -system.l2c.overall_hits::cpu1.data 245301 # number of overall hits -system.l2c.overall_hits::total 1356808 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4368 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5525 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6248 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4323 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20467 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1358 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1517 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 66435 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 66702 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133137 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 4368 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 71960 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6248 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 71025 # number of demand (read+write) misses -system.l2c.demand_misses::total 153604 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 4368 # number of overall misses -system.l2c.overall_misses::cpu0.data 71960 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6248 # number of overall misses -system.l2c.overall_misses::cpu1.data 71025 # number of overall misses -system.l2c.overall_misses::total 153604 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 305909750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 407234000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 435495000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 324083500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1472961000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 210491 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 255989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 466480 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4624449779 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4644924080 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9269373859 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 305909750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5031683779 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 435495000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4969007580 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10742334859 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 305909750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5031683779 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 435495000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4969007580 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10742334859 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9065 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3144 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 451485 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 187791 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 10697 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 4002 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 403733 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 192798 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1262715 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 596597 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 596597 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1371 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1530 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 124169 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 123528 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247697 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9065 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3144 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 451485 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 311960 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10697 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 4002 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 403733 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 316326 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1510412 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9065 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3144 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 451485 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 311960 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 10697 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 4002 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 403733 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 316326 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1510412 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000636 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.009675 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.029421 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000093 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.015476 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.022422 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016209 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990518 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991503 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.535037 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.539975 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.537499 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000636 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009675 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.230671 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000093 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.015476 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.224531 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.101697 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000636 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009675 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.230671 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000093 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.015476 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.224531 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.101697 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70034.283425 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73707.511312 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 69701.504481 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 74967.268101 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 71967.606391 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 155.000736 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 168.746869 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 162.253913 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69608.636698 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69636.953615 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69622.823550 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 70034.283425 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 69923.343232 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 69701.504481 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 69961.387962 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 69935.254674 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 70034.283425 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 69923.343232 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 69701.504481 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 69961.387962 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 69935.254674 # average overall miss latency +system.l2c.tags.occ_percent::cpu0.inst 0.059355 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.031508 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.087896 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.040455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990724 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65236 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6815 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56246 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.995422 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 26291974 # Number of tag accesses +system.l2c.tags.data_accesses 26291974 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6206 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3383 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 836468 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 253614 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5323 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2799 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 844176 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 261862 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2213831 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 686956 # number of Writeback hits +system.l2c.Writeback_hits::total 686956 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 86550 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78519 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 165069 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6206 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3383 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 836468 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 340164 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5323 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2799 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 844176 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 340381 # number of demand (read+write) hits +system.l2c.demand_hits::total 2378900 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6206 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3383 # number of overall hits +system.l2c.overall_hits::cpu0.inst 836468 # number of overall hits +system.l2c.overall_hits::cpu0.data 340164 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5323 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2799 # number of overall hits +system.l2c.overall_hits::cpu1.inst 844176 # number of overall hits +system.l2c.overall_hits::cpu1.data 340381 # number of overall hits +system.l2c.overall_hits::total 2378900 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 8151 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5123 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 9868 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 7019 # number of ReadReq misses +system.l2c.ReadReq_misses::total 30170 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1297 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1431 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 62337 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 68504 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130841 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 8151 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 67460 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 9868 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 75523 # number of demand (read+write) misses +system.l2c.demand_misses::total 161011 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 8151 # number of overall misses +system.l2c.overall_misses::cpu0.data 67460 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu1.inst 9868 # number of overall misses +system.l2c.overall_misses::cpu1.data 75523 # number of overall misses +system.l2c.overall_misses::total 161011 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 591637750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 390912500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 566500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 717694500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 529005500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2229966250 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 231490 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 463980 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 45998 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 45998 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4342067899 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4712323819 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9054391718 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 74500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 591637750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4732980399 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 566500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 717694500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 5241329319 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11284357968 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 74500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 591637750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4732980399 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 566500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 717694500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 5241329319 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11284357968 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 6207 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3384 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 844619 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 258737 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5330 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2799 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 854044 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 268881 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2244001 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 686956 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 686956 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1308 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1443 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2751 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 148887 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 147023 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295910 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 6207 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3384 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844619 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 407624 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5330 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2799 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 854044 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 415904 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2539911 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 6207 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3384 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844619 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 407624 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5330 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2799 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 854044 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 415904 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2539911 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000161 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000296 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.009651 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.019800 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001313 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.011554 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.026104 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.013445 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991590 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991684 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991639 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.418687 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.465941 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.442165 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000161 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000296 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009651 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.165496 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001313 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011554 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.181588 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.063392 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000161 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000296 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009651 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.165496 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001313 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011554 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.181588 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.063392 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72584.682861 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 76305.387468 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80928.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72729.479124 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 75367.644964 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 73913.365926 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 179.252120 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 161.767994 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 170.080645 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 22999 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 22999 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69654.745961 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68789.031575 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 69201.486675 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 72584.682861 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 70159.804314 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80928.571429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 72729.479124 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 69400.438529 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 70084.391551 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 72584.682861 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 70159.804314 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80928.571429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 72729.479124 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 69400.438529 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 70084.391551 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -612,127 +636,147 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57404 # number of writebacks -system.l2c.writebacks::total 57404 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 4368 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5525 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6248 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4323 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 20467 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1358 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1517 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 66435 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 66702 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133137 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 4368 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 71960 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6248 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 71025 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153604 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 4368 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 71960 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6248 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 71025 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153604 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 250603750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 338351500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 356302000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 270143000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1215601500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13581358 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15174017 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 28755375 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3774125721 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3790687920 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7564813641 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 250603750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4112477221 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 356302000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4060830920 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8780415141 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 250603750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4112477221 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 356302000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4060830920 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8780415141 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 349507750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83883763250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82798029500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167031300500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8325924664 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8377233499 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16703158163 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 349507750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92209687914 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91175262999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183734458663 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000636 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009675 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.029421 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000093 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015476 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022422 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016209 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990518 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991503 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.535037 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.539975 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537499 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000636 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009675 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.230671 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000093 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015476 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.224531 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101697 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000636 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009675 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.230671 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000093 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015476 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.224531 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101697 # mshr miss rate for overall accesses +system.l2c.writebacks::writebacks 82818 # number of writebacks +system.l2c.writebacks::total 82818 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 8151 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5123 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 9868 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 7019 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 30170 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1297 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1431 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2728 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 62337 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 68504 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 130841 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 8151 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 67460 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 9868 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 75523 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 161011 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 8151 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 67460 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 9868 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 75523 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 161011 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 488618750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 327007500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 479000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 592932000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 441364500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1850526750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12974797 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14335431 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 27310228 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 20002 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3544164101 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3834753681 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7378917782 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 488618750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3871171601 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 479000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 592932000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4276118181 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9229444532 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 488618750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3871171601 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 479000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 592932000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4276118181 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9229444532 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 474790500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2494979250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2890261000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5860030750 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1979887500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2118425500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4098313000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 474790500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4474866750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5008686500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 9958343750 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.019800 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026104 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013445 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.991590 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991684 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991639 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.418687 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.465941 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.442165 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.165496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.181588 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063392 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.165496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.181588 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063392 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57372.653388 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61240.090498 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57026.568502 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62489.706223 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59393.242781 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.647989 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.869565 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56809.298126 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56830.198795 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56819.769418 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63831.251220 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62881.393361 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61336.650646 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.698535 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.771488 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.080645 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56854.903204 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55978.536742 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56396.066844 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57372.653388 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57149.488897 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57026.568502 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57174.669764 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57162.672463 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57384.696131 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56620.078400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57321.826037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57372.653388 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57149.488897 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57026.568502 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57174.669764 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57162.672463 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57384.696131 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56620.078400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57321.826037 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -745,167 +789,194 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2471648 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471648 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763389 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763389 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596597 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2901 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2901 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247697 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247697 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725344 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5754019 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20105 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50232 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549700 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54760476 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83807014 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 138675122 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 18167 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2128077 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 2301461 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2301446 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 686956 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36226 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295910 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295910 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415394 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457263 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5925128 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750524 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868197 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46148 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205689601 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 53732 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3283133 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104795 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 2128077 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3246673 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36460 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2128077 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4809198500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3283133 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4418861248 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3866085496 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420737429 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12959000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 7658492249 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 3782893262 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30470250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22834207 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 16715395 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715395 # Transaction distribution -system.iobus.trans_dist::WriteReq 8184 # Transaction distribution -system.iobus.trans_dist::WriteResp 8184 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 30195 # Transaction distribution +system.iobus.trans_dist::ReadResp 30195 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383094 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447158 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2390554 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 126646810 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374910000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 39130786750 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36804759 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -929,25 +1000,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6554416 # DTB read hits -system.cpu0.dtb.read_misses 6570 # DTB read misses -system.cpu0.dtb.write_hits 5649486 # DTB write hits -system.cpu0.dtb.write_misses 1771 # DTB write misses -system.cpu0.dtb.flush_tlb 2491 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6094 # Number of entries that have been flushed from TLB +system.cpu0.dtb.read_hits 12289558 # DTB read hits +system.cpu0.dtb.read_misses 5978 # DTB read misses +system.cpu0.dtb.write_hits 9834640 # DTB write hits +system.cpu0.dtb.write_misses 1046 # DTB write misses +system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 4657 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 864 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 206 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6560986 # DTB read accesses -system.cpu0.dtb.write_accesses 5651257 # DTB write accesses +system.cpu0.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12295536 # DTB read accesses +system.cpu0.dtb.write_accesses 9835686 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12203902 # DTB hits -system.cpu0.dtb.misses 8341 # DTB misses -system.cpu0.dtb.accesses 12212243 # DTB accesses +system.cpu0.dtb.hits 22124198 # DTB hits +system.cpu0.dtb.misses 7024 # DTB misses +system.cpu0.dtb.accesses 22131222 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -969,162 +1040,162 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30237068 # ITB inst hits -system.cpu0.itb.inst_misses 3286 # ITB inst misses +system.cpu0.itb.inst_hits 58032783 # ITB inst hits +system.cpu0.itb.inst_misses 3465 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2491 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2575 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30240354 # ITB inst accesses -system.cpu0.itb.hits 30237068 # DTB hits -system.cpu0.itb.misses 3286 # DTB misses -system.cpu0.itb.accesses 30240354 # DTB accesses -system.cpu0.numCycles 2626678485 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 58036248 # ITB inst accesses +system.cpu0.itb.hits 58032783 # DTB hits +system.cpu0.itb.misses 3465 # DTB misses +system.cpu0.itb.accesses 58036248 # DTB accesses +system.cpu0.numCycles 2905319694 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29654606 # Number of instructions committed -system.cpu0.committedOps 35595186 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31825632 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5298 # Number of float alu accesses -system.cpu0.num_func_calls 1084226 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3738020 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31825632 # number of integer instructions -system.cpu0.num_fp_insts 5298 # number of float instructions -system.cpu0.num_int_register_reads 57689563 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21244985 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3888 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1412 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 127837061 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 14183382 # number of times the CC registers were written -system.cpu0.num_mem_refs 12632580 # number of memory refs -system.cpu0.num_load_insts 6723962 # Number of load instructions -system.cpu0.num_store_insts 5908618 # Number of store instructions -system.cpu0.num_idle_cycles 2294291978.637380 # Number of idle cycles -system.cpu0.num_busy_cycles 332386506.362621 # Number of busy cycles -system.cpu0.not_idle_fraction 0.126543 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.873457 # Percentage of idle cycles -system.cpu0.Branches 5094853 # Number of branches fetched -system.cpu0.op_class::No_OpClass 11433 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 23427860 64.87% 64.90% # Class of executed instruction -system.cpu0.op_class::IntMult 44876 0.12% 65.02% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 988 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.02% # Class of executed instruction -system.cpu0.op_class::MemRead 6723962 18.62% 83.64% # Class of executed instruction -system.cpu0.op_class::MemWrite 5908618 16.36% 100.00% # Class of executed instruction +system.cpu0.committedInsts 56513152 # Number of instructions committed +system.cpu0.committedOps 68067865 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60172056 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 6287 # Number of float alu accesses +system.cpu0.num_func_calls 4924591 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7649382 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60172056 # number of integer instructions +system.cpu0.num_fp_insts 6287 # number of float instructions +system.cpu0.num_int_register_reads 109432778 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41532373 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4990 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 245794862 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26123490 # number of times the CC registers were written +system.cpu0.num_mem_refs 22763355 # number of memory refs +system.cpu0.num_load_insts 12450624 # Number of load instructions +system.cpu0.num_store_insts 10312731 # Number of store instructions +system.cpu0.num_idle_cycles 2685746001.120693 # Number of idle cycles +system.cpu0.num_busy_cycles 219573692.879307 # Number of busy cycles +system.cpu0.not_idle_fraction 0.075576 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.924424 # Percentage of idle cycles +system.cpu0.Branches 12983474 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46789640 67.21% 67.21% # Class of executed instruction +system.cpu0.op_class::IntMult 58624 0.08% 67.30% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4273 0.01% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::MemRead 12450624 17.88% 85.19% # Class of executed instruction +system.cpu0.op_class::MemWrite 10312731 14.81% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 36117737 # Class of executed instruction +system.cpu0.op_class::total 69618096 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83036 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856352 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.872863 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60653974 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856864 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.785999 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 19832593000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 151.975513 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 358.897350 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.296827 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.700971 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997799 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 1698167 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.774848 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113885210 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1698679 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.043397 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 25359588250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 419.089770 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.685078 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.818535 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.179072 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997607 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62367702 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62367702 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29784788 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30869186 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60653974 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29784788 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30869186 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60653974 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29784788 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30869186 # number of overall hits -system.cpu0.icache.overall_hits::total 60653974 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 452280 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 404584 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856864 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 452280 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 404584 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856864 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 452280 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 404584 # number of overall misses -system.cpu0.icache.overall_misses::total 856864 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6154944247 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5645212999 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11800157246 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6154944247 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 5645212999 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11800157246 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6154944247 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 5645212999 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11800157246 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30237068 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 31273770 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61510838 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30237068 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 31273770 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61510838 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30237068 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 31273770 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61510838 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014958 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012937 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014958 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012937 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014958 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012937 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13608.703120 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13953.129632 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13771.330393 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13608.703120 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13953.129632 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13771.330393 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13608.703120 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13953.129632 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13771.330393 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117282580 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117282580 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 57188150 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 56697060 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113885210 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 57188150 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 56697060 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113885210 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 57188150 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 56697060 # number of overall hits +system.cpu0.icache.overall_hits::total 113885210 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844633 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 854052 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1698685 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844633 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 854052 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1698685 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844633 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 854052 # number of overall misses +system.cpu0.icache.overall_misses::total 1698685 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11522277749 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11755816000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 23278093749 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11522277749 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 11755816000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 23278093749 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11522277749 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 11755816000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 23278093749 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 58032783 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 57551112 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115583895 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 58032783 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 57551112 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115583895 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 58032783 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 57551112 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115583895 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014554 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014840 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014697 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014554 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014840 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014697 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014554 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014840 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.756537 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13764.754371 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13703.596458 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.756537 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13764.754371 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13703.596458 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.756537 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13764.754371 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13703.596458 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1133,280 +1204,297 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 452280 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 404584 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856864 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 452280 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 404584 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856864 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 452280 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 404584 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 856864 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5248743753 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 4833652001 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10082395754 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5248743753 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 4833652001 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10082395754 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5248743753 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 4833652001 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10082395754 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 440846250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 440846250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 440846250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 440846250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014958 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012937 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013930 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014958 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.012937 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013930 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014958 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.012937 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013930 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11605.075955 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11947.214920 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11766.623121 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11605.075955 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11947.214920 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11766.623121 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11605.075955 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11947.214920 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11766.623121 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 844633 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 854052 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1698685 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 844633 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 854052 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1698685 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 844633 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 854052 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1698685 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9830070251 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10044101000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19874171251 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9830070251 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10044101000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19874171251 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9830070251 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10044101000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19874171251 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 598490500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 598490500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014697 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014697 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.273962 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.526291 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11699.739063 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.273962 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.526291 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11699.739063 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.273962 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.526291 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11699.739063 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627774 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.876288 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21798278 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628286 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.694833 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 151.360555 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 360.515733 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.295626 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.704132 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999758 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 822985 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.850755 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43241496 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 823497 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.509597 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.068899 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.781856 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625135 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374574 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999709 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 90462374 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 90462374 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5593916 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 5661901 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11255817 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5011257 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4959929 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9971186 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 42993 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 41213 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 84206 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 120215 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 116148 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236363 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126346 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 121459 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247805 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10605173 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10621830 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21227003 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10648166 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10663043 # number of overall hits -system.cpu0.dcache.overall_hits::total 21311209 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 143610 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 152503 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 296113 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 128053 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 127367 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 255420 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 51303 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 48866 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100169 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6128 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5315 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11443 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 271663 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 279870 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 551533 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 322966 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 328736 # number of overall misses -system.cpu0.dcache.overall_misses::total 651702 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2007762250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2072626499 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4080388749 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5753453329 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5756409687 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11509863016 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81968750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77716000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 159684750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 7761215579 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 7829036186 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15590251765 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 7761215579 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 7829036186 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15590251765 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5737526 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 5814404 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 11551930 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5139310 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5087296 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10226606 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 94296 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 90079 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 184375 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126343 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 121463 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247806 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126346 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 121459 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247805 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10876836 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 10901700 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21778536 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10971132 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 10991779 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21962911 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025030 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026228 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.025633 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024916 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.025036 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024976 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.544063 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.542479 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.543289 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048503 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.043758 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046177 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024976 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025672 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025325 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029438 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029907 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029673 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13980.657684 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13590.726078 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13779.836579 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44930.250201 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45195.456335 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45062.497126 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13376.101501 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14622.013170 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13954.797693 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28569.277299 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27973.831372 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 28267.124116 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24031.060790 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23815.572940 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23922.362928 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 177151472 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177151472 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11581595 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11533851 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23115446 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9437905 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9389787 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18827692 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199754 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192263 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392017 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227024 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 216270 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443294 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 235238 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 225056 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460294 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 21019500 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20923638 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41943138 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 21219254 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21115901 # number of overall hits +system.cpu0.dcache.overall_hits::total 42335155 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197290 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 205524 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 402814 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 150195 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 148466 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 298661 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58530 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 60464 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 118994 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11127 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11645 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22772 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 347485 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 353990 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 701475 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 406015 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 414454 # number of overall misses +system.cpu0.dcache.overall_misses::total 820469 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2867929500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3066278250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5934207750 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5744425374 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6031803093 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11776228467 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 135157750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 145057500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 280215250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 52002 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 52002 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8612354874 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 9098081343 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 17710436217 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8612354874 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 9098081343 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 17710436217 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11778885 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11739375 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23518260 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9588100 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9538253 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19126353 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 258284 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 252727 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511011 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 238151 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 227915 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 466066 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 235240 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 225056 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460296 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 21366985 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21277628 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42644613 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21625269 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21530355 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43155624 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016749 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017507 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.017128 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015665 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015565 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015615 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226611 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.239246 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232860 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046722 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.051094 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048860 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016263 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016637 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016449 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018775 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019250 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019012 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14536.618683 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14919.319642 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.880595 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38246.448777 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40627.504567 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39430.084500 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12146.827537 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12456.633748 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12305.254260 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26001 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26001 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24784.824882 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25701.520786 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25247.423240 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21211.913043 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21951.968959 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21585.746953 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 38 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596597 # number of writebacks -system.cpu0.dcache.writebacks::total 596597 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 230 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 293 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 523 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2513 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 2309 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 4822 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2743 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 2602 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 5345 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2743 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 2602 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 5345 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 143380 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 152210 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 295590 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 125540 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 125058 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250598 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 38283 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 35273 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 73556 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6128 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5315 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11443 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 268920 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 277268 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 546188 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 307203 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 312541 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619744 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1717602000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1764563500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3482165500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5365627921 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5380262063 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10745889984 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 643406250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 581822500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1225228750 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69708250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67035000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136743250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7083229921 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7144825563 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 14228055484 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7726636171 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7726648063 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15453284234 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91635621250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90440418250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182076039500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13169946836 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13069221001 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239167837 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104805568086 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103509639251 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208315207337 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024990 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026178 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025588 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024427 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.405988 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.391579 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.398948 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048503 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043758 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024724 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025433 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025079 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028001 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028434 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028218 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11979.369508 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.953814 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11780.390067 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42740.384905 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43022.134234 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42880.988611 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16806.578638 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16494.840246 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16657.087797 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.367167 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12612.417686 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11949.947566 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26339.543065 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25768.662677 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26049.740170 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25151.564832 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24722.030271 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24934.947711 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 686956 # number of writebacks +system.cpu0.dcache.writebacks::total 686956 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 328 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 615 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7032 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7182 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14214 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 287 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 328 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 615 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 287 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 328 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 615 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 197003 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205196 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 402199 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 150195 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 148466 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 298661 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57639 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 59222 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 116861 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4095 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4463 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8558 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 347198 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 353662 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 700860 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 404837 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 412884 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 817721 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2467791750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2647821500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115613250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416554578 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5704545869 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121100447 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 696038250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 742244000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1438282250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48274750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52699750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100974500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 47998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 47998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884346328 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8352367369 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16236713697 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580384578 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9094611369 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 17674995947 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2687639750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3103027500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5790667250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2165315000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2264487500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429802500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4852954750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5367515000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220469750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016725 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017479 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017102 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015665 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015565 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015615 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223161 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234332 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228686 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017195 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019582 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018362 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016249 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016621 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016435 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018721 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019177 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018948 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.670914 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.865085 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12719.109819 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36063.481328 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.247538 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37236.533886 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12075.821059 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12533.247780 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11788.705739 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11808.144746 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11798.843188 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23999 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23999 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.501570 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.807486 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.843160 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.664959 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22027.037543 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21614.946843 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1440,25 +1528,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6613806 # DTB read hits -system.cpu1.dtb.read_misses 7420 # DTB read misses -system.cpu1.dtb.write_hits 5584575 # DTB write hits -system.cpu1.dtb.write_misses 1868 # DTB write misses -system.cpu1.dtb.flush_tlb 2491 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6816 # Number of entries that have been flushed from TLB +system.cpu1.dtb.read_hits 12236378 # DTB read hits +system.cpu1.dtb.read_misses 5657 # DTB read misses +system.cpu1.dtb.write_hits 9775690 # DTB write hits +system.cpu1.dtb.write_misses 790 # DTB write misses +system.cpu1.dtb.flush_tlb 2934 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 4044 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 152 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 917 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 246 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6621226 # DTB read accesses -system.cpu1.dtb.write_accesses 5586443 # DTB write accesses +system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12242035 # DTB read accesses +system.cpu1.dtb.write_accesses 9776480 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12198381 # DTB hits -system.cpu1.dtb.misses 9288 # DTB misses -system.cpu1.dtb.accesses 12207669 # DTB accesses +system.cpu1.dtb.hits 22012068 # DTB hits +system.cpu1.dtb.misses 6447 # DTB misses +system.cpu1.dtb.accesses 22018515 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1480,113 +1568,173 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 31273770 # ITB inst hits -system.cpu1.itb.inst_misses 4023 # ITB inst misses +system.cpu1.itb.inst_hits 57551112 # ITB inst hits +system.cpu1.itb.inst_misses 3277 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2491 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 3046 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb 2934 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2396 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31277793 # ITB inst accesses -system.cpu1.itb.hits 31273770 # DTB hits -system.cpu1.itb.misses 4023 # DTB misses -system.cpu1.itb.accesses 31277793 # DTB accesses -system.cpu1.numCycles 2629128939 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 57554389 # ITB inst accesses +system.cpu1.itb.hits 57551112 # DTB hits +system.cpu1.itb.misses 3277 # DTB misses +system.cpu1.itb.accesses 57554389 # DTB accesses +system.cpu1.numCycles 2904045401 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30562057 # Number of instructions committed -system.cpu1.committedOps 36321926 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 32452923 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 4971 # Number of float alu accesses -system.cpu1.num_func_calls 1056400 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3813741 # number of instructions that are conditional controls -system.cpu1.num_int_insts 32452923 # number of integer instructions -system.cpu1.num_fp_insts 4971 # number of float instructions -system.cpu1.num_int_register_reads 58477662 # number of times the integer registers were read -system.cpu1.num_int_register_writes 21639168 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3605 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1368 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 130057431 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 14822724 # number of times the CC registers were written -system.cpu1.num_mem_refs 12626030 # number of memory refs -system.cpu1.num_load_insts 6797131 # Number of load instructions -system.cpu1.num_store_insts 5828899 # Number of store instructions -system.cpu1.num_idle_cycles 2287592720.742589 # Number of idle cycles -system.cpu1.num_busy_cycles 341536218.257411 # Number of busy cycles -system.cpu1.not_idle_fraction 0.129905 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.870095 # Percentage of idle cycles -system.cpu1.Branches 5215542 # Number of branches fetched -system.cpu1.op_class::No_OpClass 17085 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 24167965 65.58% 65.62% # Class of executed instruction -system.cpu1.op_class::IntMult 43107 0.12% 65.74% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1123 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.74% # Class of executed instruction -system.cpu1.op_class::MemRead 6797131 18.44% 84.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 5828899 15.82% 100.00% # Class of executed instruction +system.cpu1.committedInsts 55972216 # Number of instructions committed +system.cpu1.committedOps 67554299 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59752061 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5003 # Number of float alu accesses +system.cpu1.num_func_calls 4972349 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7584517 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59752061 # number of integer instructions +system.cpu1.num_fp_insts 5003 # number of float instructions +system.cpu1.num_int_register_reads 108688873 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41135339 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3588 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 244070995 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25783519 # number of times the CC registers were written +system.cpu1.num_mem_refs 22653694 # number of memory refs +system.cpu1.num_load_insts 12397895 # Number of load instructions +system.cpu1.num_store_insts 10255799 # Number of store instructions +system.cpu1.num_idle_cycles 2693922745.089012 # Number of idle cycles +system.cpu1.num_busy_cycles 210122655.910988 # Number of busy cycles +system.cpu1.not_idle_fraction 0.072355 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.927645 # Percentage of idle cycles +system.cpu1.Branches 12941354 # Number of branches fetched +system.cpu1.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 46411426 67.14% 67.14% # Class of executed instruction +system.cpu1.op_class::IntMult 56056 0.08% 67.22% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4164 0.01% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::MemRead 12397895 17.94% 85.16% # Class of executed instruction +system.cpu1.op_class::MemWrite 10255799 14.84% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 36855310 # Class of executed instruction +system.cpu1.op_class::total 69125473 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.replacements 36424 # number of replacements +system.iocache.tags.tagsinuse 1.083103 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 309429741000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.083103 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067694 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067694 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328122 # Number of tag accesses +system.iocache.tags.data_accesses 328122 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses +system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses +system.iocache.demand_misses::total 234 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 234 # number of overall misses +system.iocache.overall_misses::total 234 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1779782747750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1779782747750 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2203719731 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2203719731 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal Binary files differindex 711cdcec2..b3be0ec54 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 68a408e3f..fe256a291 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1560,7 +1560,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1583,7 +1583,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1807,6 +1807,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index 0067e63a5..0a8bc6fbe 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -1,11 +1,11 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 -warn: x86 cpuid: unimplemented function 8 -warn: x86 cpuid: unimplemented function 8 +warn: x86 cpuid: unknown family 0x8086 warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. warn: instruction 'wbinvd' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 86995b769..3b996a550 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:13:07 -gem5 started Jun 21 2014 22:16:40 -gem5 executing on phenom -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Oct 29 2014 09:18:07 +gem5 started Oct 29 2014 09:27:02 +gem5 executing on u200540-lin +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5137926173000 because m5_exit instruction encountered +Exiting @ tick 5125902116500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 5b52389f0..7d489dc5f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.125902 # Nu sim_ticks 5125902116500 # Number of ticks simulated final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 254798 # Simulator instruction rate (inst/s) -host_op_rate 503662 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3201100243 # Simulator tick rate (ticks/s) -host_mem_usage 749084 # Number of bytes of host memory used -host_seconds 1601.29 # Real time elapsed on the host +host_inst_rate 196886 # Simulator instruction rate (inst/s) +host_op_rate 389187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2473535129 # Simulator tick rate (ticks/s) +host_mem_usage 743248 # Number of bytes of host memory used +host_seconds 2072.30 # Real time elapsed on the host sim_insts 408006726 # Number of instructions simulated sim_ops 806511598 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -426,8 +426,6 @@ system.iocache.fast_writes 46720 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses @@ -442,16 +440,14 @@ system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60928.460338 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60928.460338 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 2c304759f..5c0ccd72f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1616,7 +1616,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1639,7 +1639,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1863,6 +1863,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index 56f83c534..b4d02041b 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -1,13 +1,10 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. -warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 -warn: x86 cpuid: unimplemented function 8 -warn: x86 cpuid: unimplemented function 8 warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. warn: instruction 'wbinvd' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index 6a57a8844..ca2891ded 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:13:07 -gem5 started Jun 21 2014 22:18:32 -gem5 executing on phenom -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full +gem5 compiled Oct 29 2014 09:18:07 +gem5 started Oct 29 2014 09:28:19 +gem5 executing on u200540-lin +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index e53b3f285..847df0bf1 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.137752 # Nu sim_ticks 5137751757500 # Number of ticks simulated final_tick 5137751757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205879 # Simulator instruction rate (inst/s) -host_op_rate 409313 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4343855741 # Simulator tick rate (ticks/s) -host_mem_usage 976756 # Number of bytes of host memory used -host_seconds 1182.76 # Real time elapsed on the host +host_inst_rate 311526 # Simulator instruction rate (inst/s) +host_op_rate 619354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6572918502 # Simulator tick rate (ticks/s) +host_mem_usage 927072 # Number of bytes of host memory used +host_seconds 781.65 # Real time elapsed on the host sim_insts 243506025 # Number of instructions simulated sim_ops 484120527 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -854,8 +854,6 @@ system.iocache.fast_writes 46720 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 22056 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 22056 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses @@ -870,16 +868,14 @@ system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93740027 system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.472089 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.472089 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60294.715633 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60294.715633 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency |