diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/fs | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/fs')
18 files changed, 2681 insertions, 2706 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 46790add4..62b96c7c4 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -11,14 +11,14 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -152,20 +152,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -451,20 +444,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -590,20 +576,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -889,20 +868,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -937,7 +909,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -957,7 +929,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -986,20 +958,13 @@ is_top_level=true latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -1018,20 +983,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=2 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -1085,7 +1043,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index fd99ca0d0..70213a160 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,15 +1,12 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 3 2012 13:46:22 -gem5 started Feb 3 2012 13:46:34 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:47:49 +gem5 executing on zizzer +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 106949500 Exiting @ tick 1897464893500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 78411ca4d..89ae1dc03 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.897465 # Nu sim_ticks 1897464893500 # Number of ticks simulated final_tick 1897464893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100310 # Simulator instruction rate (inst/s) -host_tick_rate 3391719918 # Simulator tick rate (ticks/s) -host_mem_usage 326488 # Number of bytes of host memory used -host_seconds 559.44 # Real time elapsed on the host +host_inst_rate 189830 # Simulator instruction rate (inst/s) +host_op_rate 189830 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6418636186 # Simulator tick rate (ticks/s) +host_mem_usage 296280 # Number of bytes of host memory used +host_seconds 295.62 # Real time elapsed on the host sim_insts 56117221 # Number of instructions simulated +sim_ops 56117221 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30408512 # Number of bytes read from this memory system.physmem.bytes_inst_read 1099328 # Number of instructions bytes read from this memory system.physmem.bytes_written 10470144 # Number of bytes written to this memory @@ -25,122 +27,153 @@ system.l2c.total_refs 2482376 # To system.l2c.sampled_refs 433566 # Sample count of references to valid blocks. system.l2c.avg_refs 5.725486 # Average number of references to valid blocks. system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12005.589305 # Average occupied blocks per context -system.l2c.occ_blocks::1 237.479904 # Average occupied blocks per context -system.l2c.occ_blocks::2 22866.713220 # Average occupied blocks per context -system.l2c.occ_percent::0 0.183191 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.003624 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.348918 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1720206 # number of ReadReq hits -system.l2c.ReadReq_hits::1 147304 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 22866.713220 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4068.067496 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 7937.521810 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 126.484558 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 110.995347 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.348918 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.062074 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.121117 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001930 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.001694 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.535733 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 955732 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 764474 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 109195 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 38109 # number of ReadReq hits system.l2c.ReadReq_hits::total 1867510 # number of ReadReq hits -system.l2c.Writeback_hits::0 827202 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 827202 # number of Writeback hits system.l2c.Writeback_hits::total 827202 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 175 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 45 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 45 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 27 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 27 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 168180 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 11095 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 168180 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 11095 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 179275 # number of ReadExReq hits -system.l2c.demand_hits::0 1888386 # number of demand (read+write) hits -system.l2c.demand_hits::1 158399 # number of demand (read+write) hits -system.l2c.demand_hits::2 0 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 955732 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 932654 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 109195 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 49204 # number of demand (read+write) hits system.l2c.demand_hits::total 2046785 # number of demand (read+write) hits -system.l2c.overall_hits::0 1888386 # number of overall hits -system.l2c.overall_hits::1 158399 # number of overall hits -system.l2c.overall_hits::2 0 # number of overall hits +system.l2c.overall_hits::cpu0.inst 955732 # number of overall hits +system.l2c.overall_hits::cpu0.data 932654 # number of overall hits +system.l2c.overall_hits::cpu1.inst 109195 # number of overall hits +system.l2c.overall_hits::cpu1.data 49204 # number of overall hits system.l2c.overall_hits::total 2046785 # number of overall hits -system.l2c.ReadReq_misses::0 305580 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4046 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 15234 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 290346 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1960 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2086 # number of ReadReq misses system.l2c.ReadReq_misses::total 309626 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2447 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 562 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2447 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 562 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 45 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 84 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 45 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 84 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 129 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 113888 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 10746 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 113888 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 10746 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 124634 # number of ReadExReq misses -system.l2c.demand_misses::0 419468 # number of demand (read+write) misses -system.l2c.demand_misses::1 14792 # number of demand (read+write) misses -system.l2c.demand_misses::2 0 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 15234 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 404234 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1960 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12832 # number of demand (read+write) misses system.l2c.demand_misses::total 434260 # number of demand (read+write) misses -system.l2c.overall_misses::0 419468 # number of overall misses -system.l2c.overall_misses::1 14792 # number of overall misses -system.l2c.overall_misses::2 0 # number of overall misses +system.l2c.overall_misses::cpu0.inst 15234 # number of overall misses +system.l2c.overall_misses::cpu0.data 404234 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1960 # number of overall misses +system.l2c.overall_misses::cpu1.data 12832 # number of overall misses system.l2c.overall_misses::total 434260 # number of overall misses -system.l2c.ReadReq_miss_latency 16117985000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 4084000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 629500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6538201500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22656186500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22656186500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2025786 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 151350 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu0.inst 796850500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 15107982000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 102548000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 110604500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 16117985000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 2465000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1619000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 4084000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 420000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 209500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 629500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5974507500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 563694000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6538201500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 796850500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 21082489500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 102548000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 674298500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22656186500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 796850500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 21082489500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 102548000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 674298500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22656186500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 970966 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1054820 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 111155 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 40195 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2177136 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 827202 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 827202 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 827202 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2622 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 607 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2622 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 3229 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 74 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 111 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 74 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 111 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 185 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 282068 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 21841 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 282068 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 21841 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 303909 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2307854 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 173191 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 970966 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1336888 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 111155 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 62036 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2481045 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2307854 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 173191 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 970966 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1336888 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 111155 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 62036 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2481045 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.150845 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.026733 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.933257 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.925865 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.608108 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.756757 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.403761 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.492010 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.181757 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.085409 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate 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0.756757 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.403761 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.492010 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015690 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.302369 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.017633 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.206848 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015690 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.302369 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.017633 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.206848 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52307.371669 # average ReadReq miss latency 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+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.403761 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.492010 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015690 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.302369 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017489 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.206815 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015690 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.302369 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017489 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.206815 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.412892 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40025.021870 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40089.506173 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40799.904031 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40027.176134 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40003.558719 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40033.333333 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40303.565784 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40246.184627 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40065.412892 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40103.498221 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40089.506173 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40336.126267 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40065.412892 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40103.498221 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40089.506173 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40336.126267 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41697 # number of replacements system.iocache.tagsinuse 0.463236 # Cycle average of tags in use @@ -211,58 +299,41 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1709322783000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.463236 # Average occupied blocks per context -system.iocache.occ_percent::1 0.028952 # Average percentage of cache occupancy -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 177 # number of ReadReq misses +system.iocache.occ_blocks::tsunami.ide 0.463236 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.028952 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.028952 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses system.iocache.ReadReq_misses::total 177 # number of ReadReq misses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41729 # number of demand (read+write) misses +system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses system.iocache.demand_misses::total 41729 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41729 # number of overall misses +system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses system.iocache.overall_misses::total 41729 # number of overall misses -system.iocache.ReadReq_miss_latency 20391998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5720293806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5740685804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5740685804 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_latency::tsunami.ide 20391998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20391998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5720293806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5720293806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5740685804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5740685804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5740685804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5740685804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115209.028249 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137665.907923 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137570.653598 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137570.653598 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115209.028249 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.907923 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137570.653598 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137570.653598 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64638062 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked @@ -271,38 +342,32 @@ system.iocache.avg_blocked_cycles::no_mshrs 6181.319881 # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41520 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 177 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41729 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41729 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 11187998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3559436992 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3570624990 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3570624990 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63209.028249 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85662.230266 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85566.991541 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85566.991541 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11187998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11187998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559436992 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3559436992 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3570624990 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3570624990 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3570624990 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3570624990 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63209.028249 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.230266 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.991541 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.991541 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -570,6 +635,7 @@ system.cpu0.iew.wb_rate 0.479623 # in system.cpu0.iew.wb_fanout 0.742958 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitCommittedInsts 53643051 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 53643051 # The number of committed instructions system.cpu0.commit.commitSquashedInsts 8183882 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 637663 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 648245 # The number of times a branch was mispredicted @@ -590,7 +656,8 @@ system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::total 76953268 # Number of insts commited each cycle -system.cpu0.commit.count 53643051 # Number of instructions committed +system.cpu0.commit.committedInsts 53643051 # Number of instructions committed +system.cpu0.commit.committedOps 53643051 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.refs 14593748 # Number of memory references committed system.cpu0.commit.loads 8594447 # Number of loads committed @@ -607,6 +674,7 @@ system.cpu0.timesIdled 1231743 # Nu system.cpu0.idleCycles 33834806 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.quiesceCycles 3682779567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.committedInsts 50529139 # Number of Instructions Simulated +system.cpu0.committedOps 50529139 # Number of Ops (including micro ops) Simulated system.cpu0.committedInsts_total 50529139 # Number of Instructions Simulated system.cpu0.cpi 2.219390 # CPI: Cycles Per Instruction system.cpu0.cpi_total 2.219390 # CPI: Total CPI of All Threads @@ -655,51 +723,39 @@ system.cpu0.icache.total_refs 7511566 # To system.cpu0.icache.sampled_refs 970922 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 7.736529 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 23358767000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 510.008513 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.996110 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 7511566 # number of ReadReq hits +system.cpu0.icache.occ_blocks::cpu0.inst 510.008513 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996110 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996110 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 7511566 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 7511566 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 7511566 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 7511566 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 7511566 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 7511566 # number of overall hits -system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 7511566 # number of overall hits system.cpu0.icache.overall_hits::total 7511566 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 1025306 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 1025306 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 1025306 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 1025306 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 1025306 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 1025306 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 1025306 # number of overall misses -system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 1025306 # number of overall misses system.cpu0.icache.overall_misses::total 1025306 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 15323045497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 15323045497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 15323045497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 8536872 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15323045497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 15323045497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 15323045497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 15323045497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 15323045497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 15323045497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8536872 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 8536872 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 8536872 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 8536872 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 8536872 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 8536872 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8536872 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 8536872 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.120103 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.120103 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.120103 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14944.851095 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14944.851095 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14944.851095 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120103 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120103 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120103 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14944.851095 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14944.851095 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14944.851095 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 1297498 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 107 # number of cycles access was blocked @@ -708,120 +764,102 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 12126.149533 system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 220 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 54249 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 54249 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 54249 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 971057 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 971057 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 971057 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 11617533498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 11617533498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 11617533498 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113749 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.113749 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.113749 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11963.801814 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11963.801814 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11963.801814 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.writebacks::writebacks 220 # number of writebacks +system.cpu0.icache.writebacks::total 220 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54249 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54249 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54249 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54249 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54249 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54249 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 971057 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 971057 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 971057 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 971057 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 971057 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 971057 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11617533498 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11617533498 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11617533498 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11617533498 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11617533498 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11617533498 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 1340651 # number of replacements -system.cpu0.dcache.tagsinuse 503.872538 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 504.872538 # Cycle average of tags in use system.cpu0.dcache.total_refs 11358067 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 1341162 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 8.468826 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 504.872538 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.986079 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 6993872 # number of ReadReq hits +system.cpu0.dcache.warmup_cycle 19222000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 504.872538 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.986079 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.986079 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6993872 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 6993872 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 3966970 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3966970 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 3966970 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 182544 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 182544 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 182544 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 208490 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208490 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 208490 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 10960842 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 10960842 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 10960842 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 10960842 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 10960842 # number of overall hits system.cpu0.dcache.overall_hits::total 10960842 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 1697480 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 1697480 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 1697480 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1808304 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1808304 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 1808304 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 21693 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21693 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 21693 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 688 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 688 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 688 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 3505784 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 3505784 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 3505784 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 3505784 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 3505784 # number of overall misses system.cpu0.dcache.overall_misses::total 3505784 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 37053025000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 55161743853 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 326351000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 6342500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 92214768853 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 92214768853 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8691352 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 37053025000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 37053025000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55161743853 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 55161743853 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326351000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 326351000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6342500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 6342500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 92214768853 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 92214768853 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 92214768853 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 92214768853 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8691352 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8691352 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5775274 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5775274 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 5775274 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 204237 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 204237 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 204237 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 209178 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 209178 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 209178 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14466626 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 14466626 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 14466626 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14466626 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14466626 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14466626 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.195307 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.313111 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106215 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003289 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.242336 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.242336 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 21828.254236 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 30504.684972 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15044.069516 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9218.750000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 26303.608224 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 26303.608224 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195307 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.313111 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.106215 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003289 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.242336 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.242336 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21828.254236 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30504.684972 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15044.069516 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9218.750000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26303.608224 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26303.608224 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 888039305 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 98700 # number of cycles access was blocked @@ -830,57 +868,63 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8997.358713 system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 791009 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 651385 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1523767 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 4864 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 2175152 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 2175152 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 1046095 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 284537 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16829 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 688 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 1330632 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 1330632 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 24225951000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 8293520304 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 195490000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4269500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 32519471304 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 32519471304 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 916801000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1252089998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 2168890998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120360 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049268 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082399 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003289 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.091979 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.091979 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23158.461708 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29147.423021 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11616.257650 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6205.668605 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 24439.117129 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 24439.117129 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 791009 # number of writebacks +system.cpu0.dcache.writebacks::total 791009 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 651385 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 651385 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1523767 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1523767 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4864 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4864 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2175152 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2175152 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2175152 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2175152 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1046095 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1046095 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 284537 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 284537 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16829 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16829 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 688 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 688 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1330632 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1330632 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1330632 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1330632 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24225951000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24225951000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8293520304 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8293520304 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 195490000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 195490000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4269500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4269500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 32519471304 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 32519471304 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 32519471304 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 32519471304 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 916801000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 916801000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1252089998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1252089998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2168890998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2168890998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120360 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049268 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.082399 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003289 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091979 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091979 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23158.461708 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29147.423021 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11616.257650 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6205.668605 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24439.117129 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24439.117129 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -1136,6 +1180,7 @@ system.cpu1.iew.wb_rate 0.614403 # in system.cpu1.iew.wb_fanout 0.731621 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.commit.commitCommittedInsts 5811574 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 5811574 # The number of committed instructions system.cpu1.commit.commitSquashedInsts 1309607 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 75493 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 100450 # The number of times a branch was mispredicted @@ -1156,7 +1201,8 @@ system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::total 9046955 # Number of insts commited each cycle -system.cpu1.commit.count 5811574 # Number of instructions committed +system.cpu1.commit.committedInsts 5811574 # Number of instructions committed +system.cpu1.commit.committedOps 5811574 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed system.cpu1.commit.refs 1881487 # Number of memory references committed system.cpu1.commit.loads 1153406 # Number of loads committed @@ -1173,6 +1219,7 @@ system.cpu1.timesIdled 81901 # Nu system.cpu1.idleCycles 697375 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 3784961926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.committedInsts 5588082 # Number of Instructions Simulated +system.cpu1.committedOps 5588082 # Number of Ops (including micro ops) Simulated system.cpu1.committedInsts_total 5588082 # Number of Instructions Simulated system.cpu1.cpi 1.783238 # CPI: Cycles Per Instruction system.cpu1.cpi_total 1.783238 # CPI: Total CPI of All Threads @@ -1190,51 +1237,39 @@ system.cpu1.icache.total_refs 936898 # To system.cpu1.icache.sampled_refs 111117 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 8.431635 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 1874818624000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 453.435417 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.885616 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 936898 # number of ReadReq hits +system.cpu1.icache.occ_blocks::cpu1.inst 453.435417 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.885616 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.885616 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 936898 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 936898 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 936898 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::cpu1.inst 936898 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 936898 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 936898 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::cpu1.inst 936898 # number of overall hits system.cpu1.icache.overall_hits::total 936898 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 116421 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::cpu1.inst 116421 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 116421 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 116421 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::cpu1.inst 116421 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 116421 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 116421 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::cpu1.inst 116421 # number of overall misses system.cpu1.icache.overall_misses::total 116421 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 1750783999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 1750783999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 1750783999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 1053319 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1750783999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1750783999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1750783999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1750783999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1750783999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1750783999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1053319 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 1053319 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 1053319 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::cpu1.inst 1053319 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 1053319 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 1053319 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1053319 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 1053319 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.110528 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.110528 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.110528 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 15038.386537 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 15038.386537 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 15038.386537 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110528 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110528 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110528 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15038.386537 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15038.386537 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15038.386537 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 96999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 14 # number of cycles access was blocked @@ -1243,33 +1278,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 6928.500000 system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 37 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 5236 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 5236 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 5236 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 111185 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 111185 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 111185 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1333353499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 1333353499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 1333353499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.105557 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.105557 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.105557 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11992.206674 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11992.206674 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11992.206674 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.writebacks::writebacks 37 # number of writebacks +system.cpu1.icache.writebacks::total 37 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 5236 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 5236 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 5236 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 5236 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 5236 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 5236 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 111185 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 111185 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 111185 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 111185 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 111185 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 111185 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1333353499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1333353499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1333353499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1333353499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1333353499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1333353499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 62388 # number of replacements system.cpu1.dcache.tagsinuse 392.324021 # Cycle average of tags in use @@ -1277,84 +1311,69 @@ system.cpu1.dcache.total_refs 1699992 # To system.cpu1.dcache.sampled_refs 62715 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 27.106625 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1874614053500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 392.324021 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.766258 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 1127254 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 392.324021 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.766258 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.766258 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1127254 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 1127254 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 549515 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 549515 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 549515 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 16791 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16791 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 16791 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 14923 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 14923 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 14923 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 1676769 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 1676769 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 1676769 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 1676769 # number of overall hits -system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 1676769 # number of overall hits system.cpu1.dcache.overall_hits::total 1676769 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 106582 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 106582 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 106582 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 157839 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 157839 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 157839 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 1481 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1481 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 1481 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 695 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 695 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 695 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 264421 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 264421 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 264421 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 264421 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 264421 # number of overall misses system.cpu1.dcache.overall_misses::total 264421 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 1787903500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 5181152780 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 19396000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 8380000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 6969056280 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 6969056280 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 1233836 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1787903500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1787903500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5181152780 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5181152780 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 19396000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 19396000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8380000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 8380000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6969056280 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6969056280 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6969056280 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6969056280 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1233836 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 1233836 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 707354 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 707354 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 707354 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 18272 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18272 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 18272 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 15618 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15618 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 15618 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 1941190 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 1941190 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 1941190 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 1941190 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1941190 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1941190 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.086383 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.223140 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.081053 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044500 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.136216 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.136216 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 16774.910398 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 32825.555028 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13096.556381 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12057.553957 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 26355.910764 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 26355.910764 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.086383 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223140 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081053 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044500 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136216 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136216 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16774.910398 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32825.555028 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.556381 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12057.553957 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 86281997 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 6886 # number of cycles access was blocked @@ -1363,57 +1382,63 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12530.060558 system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 35937 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 62835 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 134042 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 295 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 196877 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 196877 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 43747 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 23797 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1186 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 695 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 67544 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 67544 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 555340000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 753314485 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11632000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6287000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 1308654485 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 1308654485 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 19116500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 320800500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 339917000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035456 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033642 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064908 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044500 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.034795 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.034795 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.356184 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31655.859352 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9807.757167 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9046.043165 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19374.844324 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19374.844324 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 35937 # number of writebacks +system.cpu1.dcache.writebacks::total 35937 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62835 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 62835 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 134042 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 134042 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 295 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 295 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 196877 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 196877 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 196877 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 196877 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43747 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 43747 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23797 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1186 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1186 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 695 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 695 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 67544 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 67544 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 67544 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 67544 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 555340000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 555340000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 753314485 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 753314485 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 11632000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 11632000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6287000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6287000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1308654485 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1308654485 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1308654485 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1308654485 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19116500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19116500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320800500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 320800500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 339917000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 339917000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035456 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033642 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064908 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044500 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12694.356184 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31655.859352 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9807.757167 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9046.043165 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index c884dc482..ecd4c00a8 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -11,14 +11,14 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -152,20 +152,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -451,20 +444,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -499,7 +485,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -519,7 +505,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -548,20 +534,13 @@ is_top_level=true latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -580,20 +559,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -647,7 +619,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 0ab209212..c3587ff5d 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,14 +1,11 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 3 2012 13:46:22 -gem5 started Feb 3 2012 13:46:34 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:47:47 +gem5 executing on zizzer +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1859850554500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 44b3ca581..3b4a45a9b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.859851 # Nu sim_ticks 1859850554500 # Number of ticks simulated final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100457 # Simulator instruction rate (inst/s) -host_tick_rate 3519496587 # Simulator tick rate (ticks/s) -host_mem_usage 323652 # Number of bytes of host memory used -host_seconds 528.44 # Real time elapsed on the host +host_inst_rate 188989 # Simulator instruction rate (inst/s) +host_op_rate 188989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6621174751 # Simulator tick rate (ticks/s) +host_mem_usage 292896 # Number of bytes of host memory used +host_seconds 280.89 # Real time elapsed on the host sim_insts 53085804 # Number of instructions simulated +sim_ops 53085804 # Number of ops (including micro ops) simulated system.physmem.bytes_read 29820864 # Number of bytes read from this memory system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory system.physmem.bytes_written 10193536 # Number of bytes written to this memory @@ -25,83 +27,89 @@ system.l2c.total_refs 2406767 # To system.l2c.sampled_refs 424249 # Sample count of references to valid blocks. system.l2c.avg_refs 5.673006 # Average number of references to valid blocks. system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12305.465353 # Average occupied blocks per context -system.l2c.occ_blocks::1 22620.354669 # Average occupied blocks per context -system.l2c.occ_percent::0 0.187767 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.345159 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1800764 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 22620.354669 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4081.669847 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 8223.795506 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.345159 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.062281 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.125485 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.532926 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 988583 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 812181 # number of ReadReq hits system.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits -system.l2c.Writeback_hits::0 835189 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 835189 # number of Writeback hits system.l2c.Writeback_hits::total 835189 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 183241 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 183241 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits -system.l2c.demand_hits::0 1984005 # number of demand (read+write) hits -system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 988583 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 995422 # number of demand (read+write) hits system.l2c.demand_hits::total 1984005 # number of demand (read+write) hits -system.l2c.overall_hits::0 1984005 # number of overall hits -system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::cpu.inst 988583 # number of overall hits +system.l2c.overall_hits::cpu.data 995422 # number of overall hits system.l2c.overall_hits::total 1984005 # number of overall hits -system.l2c.ReadReq_misses::0 308137 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 16626 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 291511 # number of ReadReq misses system.l2c.ReadReq_misses::total 308137 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 35 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 35 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 116889 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 116889 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 116889 # number of ReadExReq misses -system.l2c.demand_misses::0 425026 # number of demand (read+write) misses -system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 16626 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 408400 # number of demand (read+write) misses system.l2c.demand_misses::total 425026 # number of demand (read+write) misses -system.l2c.overall_misses::0 425026 # number of overall misses -system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::cpu.inst 16626 # number of overall misses +system.l2c.overall_misses::cpu.data 408400 # number of overall misses system.l2c.overall_misses::total 425026 # number of overall misses -system.l2c.ReadReq_miss_latency 16037812500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 424500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6132457500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22170270000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22170270000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2108901 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu.inst 869674000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 15168138500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 16037812500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 424500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 424500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6132457500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6132457500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 869674000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 21300596000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22170270000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 869674000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 21300596000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22170270000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 1005209 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1103692 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 835189 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835189 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 51 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 51 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 300130 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 300130 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2409031 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1005209 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1403822 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2409031 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1005209 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1403822 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.146113 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.686275 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.389461 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.176430 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.176430 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52047.668732 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 12128.571429 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52463.940148 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52162.150080 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency -system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52162.150080 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency -system.l2c.overall_avg_miss_latency::total inf # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.264124 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.686275 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.389461 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.290920 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.290920 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52308.071695 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52032.816943 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 12128.571429 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52463.940148 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -110,48 +118,59 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117762 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 308137 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 116889 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 425026 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 425026 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12334071500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 1460000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4711233500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17045305000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17045305000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 809589500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1114928998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1924518498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146113 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.686275 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.389461 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.176430 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.176430 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40027.882078 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 41714.285714 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40305.191250 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 117762 # number of writebacks +system.l2c.writebacks::total 117762 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.inst 16626 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 291511 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 308137 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 116889 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 116889 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 16626 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 408400 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 425026 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 16626 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 408400 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 425026 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 666148500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 11667923000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 12334071500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1460000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1460000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4711233500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4711233500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 666148500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 16379156500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 17045305000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 666148500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 16379156500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 17045305000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809589500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 809589500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114928998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1114928998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924518498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1924518498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264124 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.686275 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389461 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.672681 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40025.669700 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41714.285714 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40305.191250 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements system.iocache.tagsinuse 1.276011 # Cycle average of tags in use @@ -159,58 +178,41 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.276011 # Average occupied blocks per context -system.iocache.occ_percent::1 0.079751 # Average percentage of cache occupancy -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 173 # number of ReadReq misses +system.iocache.occ_blocks::tsunami.ide 1.276011 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079751 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079751 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41725 # number of demand (read+write) misses +system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41725 # number of overall misses +system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5721891806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5741829804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5741829804 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5721891806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5721891806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5741829804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5741829804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5741829804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5741829804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137704.365759 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137611.259533 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137611.259533 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.365759 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked @@ -219,38 +221,32 @@ system.iocache.avg_blocked_cycles::no_mshrs 6168.215752 # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41512 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561041984 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3571983982 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3571983982 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85700.856373 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.writebacks::writebacks 41512 # number of writebacks +system.iocache.writebacks::total 41512 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561041984 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3561041984 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3571983982 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3571983982 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3571983982 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3571983982 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85700.856373 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -518,6 +514,7 @@ system.cpu.iew.wb_rate 0.487979 # in system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions +system.cpu.commit.commitCommittedOps 56280196 # The number of committed instructions system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted @@ -538,7 +535,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle -system.cpu.commit.count 56280196 # Number of instructions committed +system.cpu.commit.committedInsts 56280196 # Number of instructions committed +system.cpu.commit.committedOps 56280196 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 15504446 # Number of memory references committed system.cpu.commit.loads 9112319 # Number of loads committed @@ -555,6 +553,7 @@ system.cpu.timesIdled 1255783 # Nu system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 53085804 # Number of Instructions Simulated +system.cpu.committedOps 53085804 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads @@ -603,51 +602,39 @@ system.cpu.icache.total_refs 7985769 # To system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.963959 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.996023 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 7985770 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 509.963959 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996023 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996023 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7985770 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits -system.cpu.icache.demand_hits::0 7985770 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 7985770 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 7985770 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 7985770 # number of overall hits system.cpu.icache.overall_hits::total 7985770 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1065446 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 1065446 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1065446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 1065446 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1065446 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 1065446 # number of overall misses system.cpu.icache.overall_misses::total 1065446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15927822494 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15927822494 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15927822494 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9051216 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15927822494 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15927822494 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15927822494 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15927822494 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15927822494 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15927822494 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9051216 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9051216 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 9051216 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9051216 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9051216 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.117713 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.117713 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.117713 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14949.441355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14949.441355 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14949.441355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117713 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.117713 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.117713 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14949.441355 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked @@ -656,33 +643,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 234 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 60134 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 60134 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 60134 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1005312 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1005312 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1005312 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12047333996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12047333996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12047333996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111069 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.111069 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.111069 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.676705 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 234 # number of writebacks +system.cpu.icache.writebacks::total 234 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60134 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 60134 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 60134 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 60134 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 60134 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 60134 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1005312 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1005312 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1005312 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1005312 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1005312 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1005312 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12047333996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12047333996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12047333996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12047333996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12047333996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12047333996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.676705 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1403406 # number of replacements system.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use @@ -690,84 +676,69 @@ system.cpu.dcache.total_refs 12086534 # To system.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.996008 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7453772 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.996008 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7453772 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4220462 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4220462 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 192050 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 192050 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 220033 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 220033 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 11674234 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 11674234 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 11674234 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 11674234 # number of overall hits system.cpu.dcache.overall_hits::total 11674234 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1809182 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1809182 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1936475 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1936475 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 22599 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22599 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3745657 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 3745657 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3745657 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 3745657 # number of overall misses system.cpu.dcache.overall_misses::total 3745657 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 38930236000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 57815325976 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 338636000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 96745561976 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 96745561976 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9262954 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 38930236000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 38930236000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57815325976 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57815325976 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338636000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 338636000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 28500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 28500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 96745561976 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 96745561976 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 96745561976 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 96745561976 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9262954 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6156937 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6156937 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 214649 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214649 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 220035 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 220035 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15419891 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 15419891 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15419891 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15419891 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.195314 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.314519 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105284 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.242911 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.242911 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 21518.142453 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.963013 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14984.556839 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 25828.729640 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 25828.729640 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195314 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314519 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.105284 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.242911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.242911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21518.142453 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29855.963013 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14984.556839 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14250 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked @@ -776,57 +747,63 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 9036.683421 system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 834955 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 721461 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1637588 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 5103 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2359049 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2359049 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1087721 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298887 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17496 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1386608 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1386608 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24804888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8509686826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206420500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33314575326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33314575326 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904009500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234178998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2138188498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117427 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048545 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081510 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.089923 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.089923 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22804.458588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28471.251095 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.153864 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 834955 # number of writebacks +system.cpu.dcache.writebacks::total 834955 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721461 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 721461 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1637588 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1637588 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5103 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5103 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2359049 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2359049 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2359049 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2359049 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1087721 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1087721 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298887 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298887 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17496 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17496 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386608 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386608 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386608 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386608 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24804888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24804888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509686826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509686826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206420500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206420500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33314575326 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33314575326 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33314575326 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 33314575326 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904009500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904009500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234178998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234178998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138188498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138188498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.117427 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048545 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.081510 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22804.458588 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28471.251095 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11798.153864 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 631ad091d..23b3ee992 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -62,7 +62,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -173,20 +173,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -481,20 +474,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -629,20 +615,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -937,20 +916,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -1002,20 +974,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -1034,20 +999,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=2 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 6780ea1b9..6921c92e4 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 3 2012 14:00:40 -gem5 started Feb 3 2012 14:01:00 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:40:16 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2582494330500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index d8f37781a..6605c6d1b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.582494 # Nu sim_ticks 2582494330500 # Number of ticks simulated final_tick 2582494330500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58235 # Simulator instruction rate (inst/s) -host_tick_rate 1883208568 # Simulator tick rate (ticks/s) -host_mem_usage 413296 # Number of bytes of host memory used -host_seconds 1371.33 # Real time elapsed on the host -sim_insts 79859495 # Number of instructions simulated +host_inst_rate 80373 # Simulator instruction rate (inst/s) +host_op_rate 103823 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3357432165 # Simulator tick rate (ticks/s) +host_mem_usage 383300 # Number of bytes of host memory used +host_seconds 769.19 # Real time elapsed on the host +sim_insts 61822124 # Number of instructions simulated +sim_ops 79859495 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 384 # Number of bytes read from this memory system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -34,127 +36,233 @@ system.l2c.total_refs 1820044 # To system.l2c.sampled_refs 162190 # Sample count of references to valid blocks. system.l2c.avg_refs 11.221678 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 4997.961622 # Average occupied blocks per context -system.l2c.occ_blocks::1 7175.690427 # Average occupied blocks per context -system.l2c.occ_blocks::2 15403.191755 # Average occupied blocks per context -system.l2c.occ_percent::0 0.076263 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.109492 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.235034 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 739066 # number of ReadReq hits -system.l2c.ReadReq_hits::1 627724 # number of ReadReq hits -system.l2c.ReadReq_hits::2 184257 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 15356.692298 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 22.670587 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 1.636552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3410.170856 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 1587.790766 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 18.616033 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 3.576285 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2636.430831 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4539.259596 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.234325 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000346 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000025 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.052035 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.024228 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000284 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000055 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.040229 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.069264 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.420789 # 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number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9896210999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 3650500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 521000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 567333500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5606089999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 4067500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 625000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 392575500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3321348000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9896210999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 89253 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 17223 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 537297 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 221556 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 74024 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3927 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 484630 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 163657 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1591567 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 599046 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 599046 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 599046 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 8343 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4816 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 8343 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4816 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13159 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 1024 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 891 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1024 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 891 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1915 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 156488 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 89319 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 156488 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 89319 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 245807 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 915341 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 737606 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 184427 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.dtb.walker 89253 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 17223 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 537297 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 378044 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 74024 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3927 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 484630 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 252976 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1837374 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 915341 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 737606 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 184427 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 89253 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 17223 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 537297 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 378044 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 74024 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3927 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 484630 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 252976 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1837374 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026075 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.031719 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.000922 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.058716 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.881098 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.792359 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.829102 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.502806 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.625511 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.564202 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.128555 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.096199 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.000922 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.225676 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.128555 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.096199 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.000922 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.225676 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 106994.946177 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 102957.204688 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 12453582.352941 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12663534.503806 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 8207.046660 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 15809.748428 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 9038.280330 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 17128.348214 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 79471.849609 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 154365.638747 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 84099.964299 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 139467.719873 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 58213005.876471 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 58436573.560642 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 84099.964299 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 139467.719873 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 58213005.876471 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 58436573.560642 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000581 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.020192 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.040342 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001054 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.003056 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.015484 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.079795 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.881098 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.792359 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.829102 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.502806 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.625511 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.564202 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000581 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.020192 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.282568 # 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miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52150 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52100 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.621532 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52182.591184 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52083.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52315.498401 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52219.006049 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3746.361039 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8592.898323 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2087.161366 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13172.991071 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52507.350452 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52375.679644 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52100 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52293.621532 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52480.177481 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52315.498401 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52343.435299 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52100 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52293.621532 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52480.177481 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52315.498401 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52343.435299 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -163,61 +271,178 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31653443800 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32535008680 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4981000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 125287415380 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1891000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39205637300 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164499924680 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.040152 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.079569 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.881098 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.792359 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.829102 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.502806 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.625511 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564202 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.282457 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.250680 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.282457 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.250680 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40053.394784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40046.075872 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.859883 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40016.640461 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.446408 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.892857 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40076.707350 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40053.012263 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40074.765164 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40051.587927 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40074.765164 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40051.587927 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -471,9 +696,9 @@ system.cpu0.iew.iewDispNonSpecInsts 864933 # Nu system.cpu0.iew.iewIQFullEvents 62296 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 5639 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 20483 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 506934 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 506933 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 135852 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 642786 # Number of branch mispredicts detected at execute +system.cpu0.iew.branchMispredicts 642785 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 79552569 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 42849690 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 723060 # Number of squashed instructions skipped in execute @@ -491,7 +716,8 @@ system.cpu0.iew.wb_penalized 0 # nu system.cpu0.iew.wb_rate 0.132406 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.537861 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 41923639 # The number of committed instructions +system.cpu0.commit.commitCommittedInsts 31935522 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 41923639 # The number of committed instructions system.cpu0.commit.commitSquashedInsts 10377261 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 1044424 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 567428 # The number of times a branch was mispredicted @@ -512,7 +738,8 @@ system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::total 108046246 # Number of insts commited each cycle -system.cpu0.commit.count 41923639 # Number of instructions committed +system.cpu0.commit.committedInsts 31935522 # Number of instructions committed +system.cpu0.commit.committedOps 41923639 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.refs 15936098 # Number of memory references committed system.cpu0.commit.loads 9243307 # Number of loads committed @@ -528,12 +755,13 @@ system.cpu0.rob.rob_writes 106372981 # Th system.cpu0.timesIdled 1454145 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 242719810 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.quiesceCycles 4812449027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 41797812 # Number of Instructions Simulated -system.cpu0.committedInsts_total 41797812 # Number of Instructions Simulated -system.cpu0.cpi 8.433071 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.433071 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.118581 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.118581 # IPC: Total IPC of All Threads +system.cpu0.committedInsts 31809695 # Number of Instructions Simulated +system.cpu0.committedOps 41797812 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31809695 # Number of Instructions Simulated +system.cpu0.cpi 11.081021 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 11.081021 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.090244 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.090244 # IPC: Total IPC of All Threads system.cpu0.int_regfile_reads 354190813 # number of integer regfile reads system.cpu0.int_regfile_writes 46128461 # number of integer regfile writes system.cpu0.fp_regfile_reads 3999 # number of floating regfile reads @@ -546,51 +774,39 @@ system.cpu0.icache.total_refs 5838964 # To system.cpu0.icache.sampled_refs 539299 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 10.826951 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 16020224000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 511.612990 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.999244 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 5838964 # number of ReadReq hits +system.cpu0.icache.occ_blocks::cpu0.inst 511.612990 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999244 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999244 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5838964 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 5838964 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 5838964 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 5838964 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 5838964 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 5838964 # number of overall hits -system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 5838964 # number of overall hits system.cpu0.icache.overall_hits::total 5838964 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 583385 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 583385 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 583385 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 583385 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 583385 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 583385 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 583385 # number of overall misses -system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 583385 # number of overall misses system.cpu0.icache.overall_misses::total 583385 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 8740145988 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 8740145988 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 8740145988 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 6422349 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8740145988 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8740145988 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 8740145988 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8740145988 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 8740145988 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8740145988 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6422349 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 6422349 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 6422349 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 6422349 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 6422349 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 6422349 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6422349 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 6422349 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.090837 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.090837 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.090837 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14981.780450 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14981.780450 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14981.780450 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.090837 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.090837 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.090837 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14981.780450 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 1633991 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 240 # number of cycles access was blocked @@ -599,122 +815,108 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 6808.295833 system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 29665 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 44065 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 44065 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 44065 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 539320 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 539320 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 539320 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 6552239991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 6552239991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 6552239991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency 6685500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.083976 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.083976 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.083976 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12149.076598 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12149.076598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12149.076598 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.writebacks::writebacks 29665 # number of writebacks +system.cpu0.icache.writebacks::total 29665 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44065 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 44065 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 44065 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 44065 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 44065 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 44065 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539320 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 539320 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 539320 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 539320 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 539320 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 539320 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6552239991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6552239991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6552239991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6552239991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6552239991 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6552239991 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6685500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 6685500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 6685500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 6685500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 372182 # number of replacements -system.cpu0.dcache.tagsinuse 487.975562 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 487.992960 # Cycle average of tags in use system.cpu0.dcache.total_refs 12779920 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 372694 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 34.290651 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 487.992960 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -0.017397 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.953111 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.000034 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7966835 # number of ReadReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 487.992960 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.953111 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.953111 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7966835 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7966835 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 4346487 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4346487 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 4346487 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 221211 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 221211 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 221211 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 199868 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 199868 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 199868 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 12313322 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 12313322 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 12313322 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 12313322 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 12313322 # number of overall hits system.cpu0.dcache.overall_hits::total 12313322 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 463412 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 463412 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 463412 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1864293 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1864293 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 1864293 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 10042 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10042 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 10042 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 7686 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7686 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 7686 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 2327705 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 2327705 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 2327705 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 2327705 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 2327705 # number of overall misses system.cpu0.dcache.overall_misses::total 2327705 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 6478995500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 70420524827 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 122158000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 87202500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 76899520327 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 76899520327 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8430247 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6478995500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6478995500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 70420524827 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 70420524827 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 122158000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 122158000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 87202500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 87202500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 76899520327 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 76899520327 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 76899520327 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 76899520327 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8430247 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8430247 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 6210780 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6210780 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 6210780 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 231253 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 231253 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 231253 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 207554 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 207554 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 207554 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14641027 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 14641027 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 14641027 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14641027 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14641027 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14641027 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.054970 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.300171 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043424 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037031 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.158985 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.158985 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 13981.069761 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 37773.313973 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12164.708225 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11345.628415 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 33036.626345 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 33036.626345 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.054970 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.300171 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.043424 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037031 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.158985 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.158985 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13981.069761 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37773.313973 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12164.708225 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11345.628415 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 6780486 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 1857500 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 854 # number of cycles access was blocked @@ -723,59 +925,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7939.679157 system.cpu0.dcache.avg_blocked_cycles::no_targets 14511.718750 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 327766 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 223882 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1685987 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 318 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1909869 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1909869 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 239530 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 178306 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9724 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 7685 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 417836 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 417836 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 2943060000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6370530485 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 87975000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 64109000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 9313590485 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 9313590485 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138958680000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038766498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 139997446498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028413 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028709 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.042049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.028539 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.028539 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12286.811673 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35728.076930 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9047.202797 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8342.094990 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 327766 # number of writebacks +system.cpu0.dcache.writebacks::total 327766 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223882 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 223882 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1685987 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1685987 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 318 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 318 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1909869 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1909869 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1909869 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1909869 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 239530 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 239530 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178306 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 178306 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9724 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9724 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7685 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7685 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 417836 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 417836 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 417836 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 417836 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2943060000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2943060000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6370530485 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6370530485 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87975000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87975000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 64109000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 64109000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9313590485 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9313590485 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9313590485 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9313590485 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 138958680000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 138958680000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1038766498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1038766498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 139997446498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 139997446498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028413 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028709 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.042049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028539 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028539 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12286.811673 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35728.076930 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9047.202797 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8342.094990 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22290.062333 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22290.062333 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -1043,7 +1252,8 @@ system.cpu1.iew.wb_penalized 0 # nu system.cpu1.iew.wb_rate 0.640894 # insts written-back per cycle system.cpu1.iew.wb_fanout 0.545985 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38086237 # The number of committed instructions +system.cpu1.commit.commitCommittedInsts 30036983 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 38086237 # The number of committed instructions system.cpu1.commit.commitSquashedInsts 18573771 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 519501 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 450480 # The number of times a branch was mispredicted @@ -1064,7 +1274,8 @@ system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::total 47701192 # Number of insts commited each cycle -system.cpu1.commit.count 38086237 # Number of instructions committed +system.cpu1.commit.committedInsts 30036983 # Number of instructions committed +system.cpu1.commit.committedOps 38086237 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed system.cpu1.commit.refs 12651383 # Number of memory references committed system.cpu1.commit.loads 7112761 # Number of loads committed @@ -1080,12 +1291,13 @@ system.cpu1.rob.rob_writes 116493771 # Th system.cpu1.timesIdled 450197 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.idleCycles 18365285 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 5095139417 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38061683 # Number of Instructions Simulated -system.cpu1.committedInsts_total 38061683 # Number of Instructions Simulated -system.cpu1.cpi 1.814944 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.814944 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550981 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550981 # IPC: Total IPC of All Threads +system.cpu1.committedInsts 30012429 # Number of Instructions Simulated +system.cpu1.committedOps 38061683 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30012429 # Number of Instructions Simulated +system.cpu1.cpi 2.301707 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.301707 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.434460 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.434460 # IPC: Total IPC of All Threads system.cpu1.int_regfile_reads 222861231 # number of integer regfile reads system.cpu1.int_regfile_writes 47167724 # number of integer regfile writes system.cpu1.fp_regfile_reads 4217 # number of floating regfile reads @@ -1098,51 +1310,39 @@ system.cpu1.icache.total_refs 7684975 # To system.cpu1.icache.sampled_refs 486098 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 15.809518 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74234723000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 498.788681 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.974197 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 7684975 # number of ReadReq hits +system.cpu1.icache.occ_blocks::cpu1.inst 498.788681 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974197 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974197 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7684975 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 7684975 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 7684975 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::cpu1.inst 7684975 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 7684975 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 7684975 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::cpu1.inst 7684975 # number of overall hits system.cpu1.icache.overall_hits::total 7684975 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 527035 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::cpu1.inst 527035 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 527035 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 527035 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::cpu1.inst 527035 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 527035 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 527035 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::cpu1.inst 527035 # number of overall misses system.cpu1.icache.overall_misses::total 527035 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7752735997 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7752735997 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7752735997 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 8212010 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7752735997 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7752735997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7752735997 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7752735997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7752735997 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7752735997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8212010 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 8212010 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 8212010 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::cpu1.inst 8212010 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 8212010 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 8212010 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8212010 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 8212010 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.064179 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.064179 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.064179 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14710.097047 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14710.097047 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14710.097047 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.064179 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.064179 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.064179 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14710.097047 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14710.097047 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14710.097047 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 1321997 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 170 # number of cycles access was blocked @@ -1151,35 +1351,38 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 7776.452941 system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 18538 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 40914 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 40914 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 40914 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 486121 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 486121 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 486121 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5799471497 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5799471497 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5799471497 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059196 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.059196 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.059196 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11930.098673 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11930.098673 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11930.098673 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.writebacks::writebacks 18538 # number of writebacks +system.cpu1.icache.writebacks::total 18538 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 40914 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 40914 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 40914 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 40914 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 40914 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 40914 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 486121 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 486121 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 486121 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 486121 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 486121 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 486121 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5799471497 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5799471497 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5799471497 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5799471497 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5799471497 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5799471497 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2517500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2517500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2517500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2517500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 272200 # number of replacements system.cpu1.dcache.tagsinuse 447.953212 # Cycle average of tags in use @@ -1187,84 +1390,69 @@ system.cpu1.dcache.total_refs 10416163 # To system.cpu1.dcache.sampled_refs 272587 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 38.212252 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 66688833000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 447.953212 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.874909 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 7085363 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 447.953212 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.874909 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.874909 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 7085363 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 7085363 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 3139669 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3139669 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 3139669 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 75360 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 75360 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 75360 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 72622 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72622 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 72622 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 10225032 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 10225032 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 10225032 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 10225032 # number of overall hits -system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 10225032 # number of overall hits system.cpu1.dcache.overall_hits::total 10225032 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 323287 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 323287 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 323287 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 1273508 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1273508 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 1273508 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 12669 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12669 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 12669 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 11046 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 11046 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 11046 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 1596795 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 1596795 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 1596795 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 1596795 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 1596795 # number of overall misses system.cpu1.dcache.overall_misses::total 1596795 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 5044696500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 46343696337 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 148164500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 87512500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 51388392837 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 51388392837 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 7408650 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5044696500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5044696500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 46343696337 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 46343696337 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 148164500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 148164500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87512500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 87512500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 51388392837 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 51388392837 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 51388392837 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 51388392837 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7408650 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 7408650 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 4413177 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4413177 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 4413177 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 88029 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 88029 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 88029 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 83668 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83668 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 83668 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 11821827 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 11821827 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 11821827 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 11821827 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11821827 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 11821827 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.043636 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.288569 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.143918 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132022 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.135072 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.135072 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15604.390217 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 36390.581243 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11695.043018 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7922.551150 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 32182.210514 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 32182.210514 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.043636 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.288569 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.143918 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.132022 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135072 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135072 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15604.390217 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36390.581243 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11695.043018 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7922.551150 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32182.210514 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32182.210514 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 13033547 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 5494000 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3077 # number of cycles access was blocked @@ -1273,57 +1461,63 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4235.796880 system.cpu1.dcache.avg_blocked_cycles::no_targets 32898.203593 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 223077 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 133946 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 1157260 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 1008 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 1291206 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 1291206 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 189341 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 116248 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 11661 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 11046 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 305589 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 305589 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2489937000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 3452864547 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 99179500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54297000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 5942801547 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 5942801547 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455613500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41497603581 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 49953217081 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025557 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026341 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.132468 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132022 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.025850 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.025850 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13150.543200 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29702.571631 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8505.231112 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4915.535035 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 223077 # number of writebacks +system.cpu1.dcache.writebacks::total 223077 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 133946 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 133946 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1157260 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1157260 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1008 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1008 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1291206 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1291206 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1291206 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1291206 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 189341 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 189341 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 116248 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 116248 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11661 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11661 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 11046 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 11046 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 305589 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 305589 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 305589 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 305589 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2489937000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2489937000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3452864547 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3452864547 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 99179500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 99179500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 54297000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 54297000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5942801547 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5942801547 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5942801547 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5942801547 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 8455613500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 8455613500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41497603581 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41497603581 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 49953217081 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 49953217081 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025557 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026341 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132468 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.132022 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.025850 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.025850 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.543200 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29702.571631 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8505.231112 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4915.535035 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19447.040132 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19447.040132 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -1331,38 +1525,6 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1371,28 +1533,12 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1308174844926 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1308174844926 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1308174844926 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1308174844926 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 55723 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index f906b4862..2ad88f280 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -62,7 +62,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -173,20 +173,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -481,20 +474,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -546,20 +532,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -578,20 +557,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 46d2cdea6..1c96dc767 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 3 2012 14:00:40 -gem5 started Feb 3 2012 14:01:01 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:39:00 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2503580880500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b494abcbb..1df010cb5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.503581 # Nu sim_ticks 2503580880500 # Number of ticks simulated final_tick 2503580880500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56444 # Simulator instruction rate (inst/s) -host_tick_rate 1840259079 # Simulator tick rate (ticks/s) -host_mem_usage 413160 # Number of bytes of host memory used -host_seconds 1360.45 # Real time elapsed on the host -sim_insts 76789886 # Number of instructions simulated +host_inst_rate 80550 # Simulator instruction rate (inst/s) +host_op_rate 104045 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3392180683 # Simulator tick rate (ticks/s) +host_mem_usage 382816 # Number of bytes of host memory used +host_seconds 738.04 # Real time elapsed on the host +sim_insts 59449329 # Number of instructions simulated +sim_ops 76789886 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 64 # Number of bytes read from this memory system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -34,91 +36,132 @@ system.l2c.total_refs 1795685 # To system.l2c.sampled_refs 150314 # Sample count of references to valid blocks. system.l2c.avg_refs 11.946226 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11478.014025 # Average occupied blocks per context -system.l2c.occ_blocks::1 14356.915365 # Average occupied blocks per context -system.l2c.occ_percent::0 0.175141 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.219069 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1349535 # number of ReadReq hits -system.l2c.ReadReq_hits::1 153277 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 14304.535648 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 48.618373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 3.761343 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6047.704729 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5430.309296 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.218270 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000742 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.092281 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.082860 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.394210 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 143695 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 9582 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 973305 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 376230 # number of ReadReq hits system.l2c.ReadReq_hits::total 1502812 # number of ReadReq hits -system.l2c.Writeback_hits::0 630148 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 630148 # number of Writeback hits system.l2c.Writeback_hits::total 630148 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 47 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 47 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 17 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 17 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 105970 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 105970 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 105970 # number of ReadExReq hits -system.l2c.demand_hits::0 1455505 # number of demand (read+write) hits -system.l2c.demand_hits::1 153277 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.dtb.walker 143695 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 9582 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 973305 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 482200 # number of demand (read+write) hits system.l2c.demand_hits::total 1608782 # number of demand (read+write) hits -system.l2c.overall_hits::0 1455505 # number of overall hits -system.l2c.overall_hits::1 153277 # number of overall hits +system.l2c.overall_hits::cpu.dtb.walker 143695 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 9582 # number of overall hits +system.l2c.overall_hits::cpu.inst 973305 # number of overall hits +system.l2c.overall_hits::cpu.data 482200 # number of overall hits system.l2c.overall_hits::total 1608782 # number of overall hits -system.l2c.ReadReq_misses::0 36088 # number of ReadReq misses -system.l2c.ReadReq_misses::1 150 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.dtb.walker 134 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 16 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 17088 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 19000 # number of ReadReq misses system.l2c.ReadReq_misses::total 36238 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3252 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 3252 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 3252 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 4 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 140397 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 140397 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 140397 # number of ReadExReq misses -system.l2c.demand_misses::0 176485 # number of demand (read+write) misses -system.l2c.demand_misses::1 150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.dtb.walker 134 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 17088 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 159397 # number of demand (read+write) misses system.l2c.demand_misses::total 176635 # number of demand (read+write) misses -system.l2c.overall_misses::0 176485 # number of overall misses -system.l2c.overall_misses::1 150 # number of overall misses +system.l2c.overall_misses::cpu.dtb.walker 134 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 16 # number of overall misses +system.l2c.overall_misses::cpu.inst 17088 # number of overall misses +system.l2c.overall_misses::cpu.data 159397 # number of overall misses system.l2c.overall_misses::total 176635 # number of overall misses -system.l2c.ReadReq_miss_latency 1895542500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 1059500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7383005500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9278548000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9278548000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1385623 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 153427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7004000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 843500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 894670500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 993024500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1895542500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1059500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1059500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7383005500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7383005500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 7004000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 843500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 894670500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8376030000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9278548000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 7004000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 843500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 894670500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8376030000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9278548000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 143829 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 9598 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 990393 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 395230 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1539050 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 630148 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 630148 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 630148 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 3299 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3299 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 3299 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 21 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 21 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 21 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 246367 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246367 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1631990 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 153427 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.dtb.walker 143829 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 9598 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 990393 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 641597 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1785417 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1631990 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 153427 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 143829 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 9598 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 990393 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 641597 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1785417 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026045 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000978 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.027022 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.985753 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.190476 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.569869 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.108141 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000978 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.109119 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.108141 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000978 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.109119 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52525.562514 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 12636950 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12689475.562514 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 325.799508 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52586.632905 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52574.145111 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 61856986.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 61909560.811778 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52574.145111 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 61856986.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 61909560.811778 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000932 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.017254 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.048073 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.985753 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.190476 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.569869 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000932 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.017254 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.248438 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000932 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.017254 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.248438 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52268.656716 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52718.750000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52356.653792 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52264.447368 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 325.799508 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52586.632905 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -127,55 +170,102 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 102643 # number of writebacks -system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 94 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 36144 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3252 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 4 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 140397 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 176541 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 176541 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1450468000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 131324500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 160000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5639183500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7089651500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7089651500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131770082500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32364127897 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164134210397 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.235578 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.261663 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.985753 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.190476 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.569869 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.108175 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.150651 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.258827 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.108175 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.150651 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.258827 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40130.256751 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40382.687577 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40165.982891 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 102643 # number of writebacks +system.l2c.writebacks::total 102643 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 80 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 80 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 94 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 134 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 16 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 17074 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 18920 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 36144 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 3252 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3252 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 140397 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140397 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 134 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 16 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 17074 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 159317 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176541 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 134 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 16 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 17074 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 159317 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176541 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 5376000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 651000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 685402500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 759038500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1450468000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 131324500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 131324500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 160000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 160000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5639183500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5639183500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5376000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 651000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 685402500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6398222000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7089651500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5376000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 651000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 685402500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6398222000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7089651500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 4738500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765344000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131770082500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32364127897 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32364127897 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 4738500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164129471897 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164134210397 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.047871 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985753 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.190476 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569869 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.053766 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40118.313953 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40382.687577 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40165.982891 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -429,9 +519,9 @@ system.cpu.iew.iewDispNonSpecInsts 1227782 # Nu system.cpu.iew.iewIQFullEvents 84296 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 7341 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 32675 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 852505 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 852504 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 256815 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1109320 # Number of branch mispredicts detected at execute +system.cpu.iew.branchMispredicts 1109319 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 123469909 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 52917262 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 3434775 # Number of squashed instructions skipped in execute @@ -449,7 +539,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 0.209988 # insts written-back per cycle system.cpu.iew.wb_fanout 0.543006 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 76940267 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 59599710 # The number of committed instructions +system.cpu.commit.commitCommittedOps 76940267 # The number of committed instructions system.cpu.commit.commitSquashedInsts 27835988 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1499707 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 978113 # The number of times a branch was mispredicted @@ -470,7 +561,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 151014616 # Number of insts commited each cycle -system.cpu.commit.count 76940267 # Number of instructions committed +system.cpu.commit.committedInsts 59599710 # Number of instructions committed +system.cpu.commit.committedOps 76940267 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 27459843 # Number of memory references committed system.cpu.commit.loads 15680763 # Number of loads committed @@ -486,12 +578,13 @@ system.cpu.rob.rob_writes 214319630 # Th system.cpu.timesIdled 1877181 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 260374175 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 4591130340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 76789886 # Number of Instructions Simulated -system.cpu.committedInsts_total 76789886 # Number of Instructions Simulated -system.cpu.cpi 5.416643 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.416643 # CPI: Total CPI of All Threads -system.cpu.ipc 0.184616 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.184616 # IPC: Total IPC of All Threads +system.cpu.committedInsts 59449329 # Number of Instructions Simulated +system.cpu.committedOps 76789886 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59449329 # Number of Instructions Simulated +system.cpu.cpi 6.996604 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.996604 # CPI: Total CPI of All Threads +system.cpu.ipc 0.142926 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.142926 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 559798057 # number of integer regfile reads system.cpu.int_regfile_writes 89741069 # number of integer regfile writes system.cpu.fp_regfile_reads 8257 # number of floating regfile reads @@ -504,51 +597,39 @@ system.cpu.icache.total_refs 13035657 # To system.cpu.icache.sampled_refs 991689 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 13.144904 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 511.615293 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 13035657 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 511.615293 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13035657 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 13035657 # number of ReadReq hits -system.cpu.icache.demand_hits::0 13035657 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 13035657 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 13035657 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 13035657 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 13035657 # number of overall hits system.cpu.icache.overall_hits::total 13035657 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1079227 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 1079227 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1079227 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1079227 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 1079227 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1079227 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1079227 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 1079227 # number of overall misses system.cpu.icache.overall_misses::total 1079227 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15906225491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15906225491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15906225491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 14114884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15906225491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15906225491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15906225491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15906225491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15906225491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15906225491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14114884 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 14114884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 14114884 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 14114884 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 14114884 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 14114884 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14114884 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 14114884 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.076460 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.076460 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.076460 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14738.535536 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14738.535536 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14738.535536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.076460 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.076460 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.076460 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14738.535536 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2390996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked @@ -557,35 +638,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7011.718475 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 57255 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 87505 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 87505 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 87505 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 991722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 991722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 991722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11850340996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11850340996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11850340996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070261 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.070261 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.070261 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11949.256945 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11949.256945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11949.256945 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 57255 # number of writebacks +system.cpu.icache.writebacks::total 57255 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87505 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 87505 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 87505 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 87505 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 87505 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 87505 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991722 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991722 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991722 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991722 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11850340996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11850340996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11850340996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11850340996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11850340996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11850340996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6359500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6359500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6359500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 6359500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11949.256945 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 643728 # number of replacements system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use @@ -593,84 +677,69 @@ system.cpu.dcache.total_refs 22270301 # To system.cpu.dcache.sampled_refs 644240 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 34.568330 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 14416609 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.991681 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 14416609 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 14416609 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 7264899 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7264899 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 7264899 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 299899 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 299899 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 299899 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 285488 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285488 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 285488 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 21681508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 21681508 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 21681508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 21681508 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 21681508 # number of overall hits system.cpu.dcache.overall_hits::total 21681508 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 722544 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 722544 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 722544 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2966373 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2966373 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2966373 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 13502 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13502 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 13502 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::0 21 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 21 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3688917 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 3688917 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3688917 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3688917 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 3688917 # number of overall misses system.cpu.dcache.overall_misses::total 3688917 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 10864923000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 110367485740 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 219139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency 467500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 121232408740 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 121232408740 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 15139153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10864923000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10864923000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110367485740 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110367485740 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 219139000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 219139000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 467500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 467500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121232408740 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121232408740 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121232408740 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121232408740 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 15139153 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 15139153 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 10231272 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10231272 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10231272 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 313401 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 313401 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 313401 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 285509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285509 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 285509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 25370425 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 25370425 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 25370425 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 25370425 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 25370425 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 25370425 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.047727 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.289932 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043082 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000074 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.145402 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.145402 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15037.039959 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 37206.206280 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16230.114057 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 22261.904762 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 32863.956749 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 32863.956749 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047727 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289932 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043082 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000074 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.145402 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.145402 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15037.039959 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37206.206280 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16230.114057 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22261.904762 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 16658435 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 7526500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2975 # number of cycles access was blocked @@ -679,57 +748,63 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 5599.473950 system.cpu.dcache.avg_blocked_cycles::no_targets 27171.480144 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 572893 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 336628 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2716799 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3053427 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3053427 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 385916 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249574 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 12049 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 21 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 635490 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 635490 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5245615500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8926036935 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161663500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 398500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 14171652435 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 14171652435 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147159299000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42287348315 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 189446647315 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025491 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038446 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000074 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.025048 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.025048 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13592.635444 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35765.091456 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13417.171550 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 18976.190476 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 572893 # number of writebacks +system.cpu.dcache.writebacks::total 572893 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 336628 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 336628 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716799 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2716799 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3053427 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3053427 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3053427 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3053427 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385916 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385916 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249574 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249574 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12049 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12049 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 21 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 21 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635490 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635490 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635490 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635490 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5245615500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5245615500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926036935 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926036935 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 161663500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 161663500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 398500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 398500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14171652435 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14171652435 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14171652435 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14171652435 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159299000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159299000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42287348315 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42287348315 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189446647315 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189446647315 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025491 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038446 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13592.635444 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35765.091456 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13417.171550 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18976.190476 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -737,38 +812,6 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -777,28 +820,12 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1307927966543 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1307927966543 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307927966543 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307927966543 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 87993 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index ea30d17bb..a45397a7d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -8,14 +8,14 @@ time_sync_spin_threshold=100000000 [system] type=LinuxX86System -children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus +children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus acpi_description_table_pointer=system.acpi_description_table_pointer boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -50,6 +50,17 @@ oem_id= oem_revision=0 oem_table_id= +[system.apicbridge] +type=Bridge +delay=50000 +nack_delay=4000 +ranges=11529215046068469760:11529215046068473855 +req_size=16 +resp_size=16 +write_ack=false +master=system.membus.port[2] +slave=system.iobus.port[1] + [system.bridge] type=Bridge delay=50000 @@ -169,20 +180,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -212,20 +216,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -507,20 +504,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -559,20 +549,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -946,17 +929,6 @@ subtractive_decode=true type=IntrControl sys=system -[system.iobridge] -type=Bridge -delay=50000 -nack_delay=4000 -ranges=11529215046068469760:11529215046068473855 -req_size=16 -resp_size=16 -write_ack=false -master=system.membus.port[2] -slave=system.iobus.port[1] - [system.iobus] type=Bus block_size=64 @@ -966,7 +938,7 @@ header_cycles=1 use_default_range=true width=64 default=system.pc.pciconfig.pio -port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side +port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side [system.iocache] type=BaseCache @@ -979,20 +951,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -1011,20 +976,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -1042,7 +1000,7 @@ header_cycles=1 use_default_range=false width=64 default=system.membus.badaddr_responder.pio -port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.membus.badaddr_responder] type=IsaFake @@ -1303,7 +1261,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1323,7 +1281,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 647f02ab1..7b718bc11 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,15 +1,12 @@ -Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 3 2012 12:36:19 -gem5 started Feb 3 2012 12:37:07 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:31:16 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5163317092500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 9bce828a3..477cac0b5 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 5.163317 # Nu sim_ticks 5163317092500 # Number of ticks simulated final_tick 5163317092500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210982 # Simulator instruction rate (inst/s) -host_tick_rate 1295931182 # Simulator tick rate (ticks/s) -host_mem_usage 391560 # Number of bytes of host memory used -host_seconds 3984.25 # Real time elapsed on the host -sim_insts 840604148 # Number of instructions simulated +host_inst_rate 184798 # Simulator instruction rate (inst/s) +host_op_rate 364169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2236864416 # Simulator tick rate (ticks/s) +host_mem_usage 361200 # Number of bytes of host memory used +host_seconds 2308.28 # Real time elapsed on the host +sim_insts 426565585 # Number of instructions simulated +sim_ops 840604148 # Number of ops (including micro ops) simulated system.physmem.bytes_read 15861056 # Number of bytes read from this memory system.physmem.bytes_inst_read 1233408 # Number of instructions bytes read from this memory system.physmem.bytes_written 12134976 # Number of bytes written to this memory @@ -25,84 +27,125 @@ system.l2c.total_refs 3777661 # To system.l2c.sampled_refs 200841 # Sample count of references to valid blocks. system.l2c.avg_refs 18.809212 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11087.594784 # Average occupied blocks per context -system.l2c.occ_blocks::1 26777.855453 # Average occupied blocks per context -system.l2c.occ_percent::0 0.169183 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.408598 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2326799 # number of ReadReq hits -system.l2c.ReadReq_hits::1 141457 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 26765.864627 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 11.948564 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.042262 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 2364.419048 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 8723.175736 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.408415 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.036078 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.133105 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.577781 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 134155 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 7302 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1001370 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1325429 # number of ReadReq hits system.l2c.ReadReq_hits::total 2468256 # number of ReadReq hits -system.l2c.Writeback_hits::0 1603120 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 1603120 # number of Writeback hits system.l2c.Writeback_hits::total 1603120 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 322 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 322 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 322 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 150704 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 150704 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 150704 # number of ReadExReq hits -system.l2c.demand_hits::0 2477503 # number of demand (read+write) hits -system.l2c.demand_hits::1 141457 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.dtb.walker 134155 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 7302 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 1001370 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1476133 # number of demand (read+write) hits system.l2c.demand_hits::total 2618960 # number of demand (read+write) hits -system.l2c.overall_hits::0 2477503 # number of overall hits -system.l2c.overall_hits::1 141457 # number of overall hits +system.l2c.overall_hits::cpu.dtb.walker 134155 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 7302 # number of overall hits +system.l2c.overall_hits::cpu.inst 1001370 # number of overall hits +system.l2c.overall_hits::cpu.data 1476133 # number of overall hits system.l2c.overall_hits::total 2618960 # number of overall hits -system.l2c.ReadReq_misses::0 64223 # number of ReadReq misses -system.l2c.ReadReq_misses::1 92 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.dtb.walker 82 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 19273 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 44950 # number of ReadReq misses system.l2c.ReadReq_misses::total 64315 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 5079 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 5079 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5079 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 141389 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 141389 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 141389 # number of ReadExReq misses -system.l2c.demand_misses::0 205612 # number of demand (read+write) misses -system.l2c.demand_misses::1 92 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.dtb.walker 82 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 19273 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 186339 # number of demand (read+write) misses system.l2c.demand_misses::total 205704 # number of demand (read+write) misses -system.l2c.overall_misses::0 205612 # number of overall misses -system.l2c.overall_misses::1 92 # number of overall misses +system.l2c.overall_misses::cpu.dtb.walker 82 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu.inst 19273 # number of overall misses +system.l2c.overall_misses::cpu.data 186339 # number of overall misses system.l2c.overall_misses::total 205704 # number of overall misses -system.l2c.ReadReq_miss_latency 3374675500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 37477500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7363267000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 10737942500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 10737942500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2391022 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 141549 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 4278000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 521000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 1007154000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 2362722500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 3374675500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 37477500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 37477500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7363267000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7363267000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 4278000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 521000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 1007154000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 9725989500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10737942500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 4278000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 521000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 1007154000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 9725989500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10737942500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 134237 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 7312 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1020643 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1370379 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2532571 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1603120 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1603120 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1603120 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 5401 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 5401 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5401 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 292093 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 292093 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 292093 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2683115 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 141549 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.dtb.walker 134237 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 7312 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1020643 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1662472 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2824664 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2683115 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 141549 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 134237 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 7312 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1020643 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1662472 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2824664 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026860 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000650 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.027510 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.940381 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.484055 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.076632 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000650 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.077282 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.076632 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000650 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.077282 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52546.213973 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 36681255.434783 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 36733801.648756 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 7378.913172 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52078.075381 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52224.298679 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 116716766.304348 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 116768990.603027 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52224.298679 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 116716766.304348 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 116768990.603027 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000611 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001368 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.018883 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.032801 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.940381 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.484055 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000611 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001368 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.018883 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.112085 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000611 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001368 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.018883 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.112085 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52170.731707 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52100 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52257.251077 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52563.348165 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 7378.913172 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52078.075381 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52170.731707 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52100 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52257.251077 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52195.136284 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52170.731707 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52100 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52257.251077 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52195.136284 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -111,49 +154,92 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142942 # number of writebacks -system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 64313 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 5079 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 141389 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 205702 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 205702 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2588909500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 203533000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5656832000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8245741500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8245741500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 59975483500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1228994000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 61204477500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026898 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.454351 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.481249 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.940381 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.484055 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.076665 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.453221 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.529887 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.076665 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.453221 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.529887 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40254.839613 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40073.439653 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40008.996457 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40085.859642 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40085.859642 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 142942 # number of writebacks +system.l2c.writebacks::total 142942 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 82 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 19272 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 44949 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 64313 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 5079 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 5079 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 141389 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 141389 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 82 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 19272 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 186338 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 205702 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 82 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 19272 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 186338 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 205702 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 3286000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 400000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 771698500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 1813525000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2588909500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 203533000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 203533000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5656832000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5656832000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 3286000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 400000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 771698500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 7470357000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8245741500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 3286000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 400000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 771698500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 7470357000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8245741500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59975483500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59975483500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1228994000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1228994000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 61204477500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 61204477500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000611 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001368 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018882 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.032800 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.940381 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.484055 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000611 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001368 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.018882 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.112085 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000611 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001368 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.018882 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.112085 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40042.470942 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40346.281341 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40073.439653 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40008.996457 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40042.470942 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.357308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40042.470942 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.357308 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47580 # number of replacements system.iocache.tagsinuse 0.183883 # Cycle average of tags in use @@ -161,58 +247,41 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 47596 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 4996389534000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.183883 # Average occupied blocks per context -system.iocache.occ_percent::1 0.011493 # Average percentage of cache occupancy -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 915 # number of ReadReq misses +system.iocache.occ_blocks::pc.south_bridge.ide 0.183883 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.011493 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.011493 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses system.iocache.ReadReq_misses::total 915 # number of ReadReq misses -system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses +system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47635 # number of demand (read+write) misses +system.iocache.demand_misses::pc.south_bridge.ide 47635 # number of demand (read+write) misses system.iocache.demand_misses::total 47635 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47635 # number of overall misses +system.iocache.overall_misses::pc.south_bridge.ide 47635 # number of overall misses system.iocache.overall_misses::total 47635 # number of overall misses -system.iocache.ReadReq_miss_latency 114575932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6365614160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6480190092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6480190092 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 915 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 114575932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 114575932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6365614160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6365614160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6480190092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6480190092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6480190092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6480190092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47635 # number of demand (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47635 # number of demand (read+write) accesses system.iocache.demand_accesses::total 47635 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47635 # number of overall (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47635 # number of overall (read+write) accesses system.iocache.overall_accesses::total 47635 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125219.597814 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136250.303082 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136038.419062 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136038.419062 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125219.597814 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136250.303082 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136038.419062 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136038.419062 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 68485452 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11259 # number of cycles access was blocked @@ -221,38 +290,32 @@ system.iocache.avg_blocked_cycles::no_mshrs 6082.729550 # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46667 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 915 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 47635 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 47635 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 66972982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3935855798 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4002828780 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4002828780 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73194.515847 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84243.488827 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84031.253910 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84031.253910 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47635 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47635 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47635 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47635 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66972982 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 66972982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3935855798 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3935855798 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4002828780 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4002828780 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4002828780 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4002828780 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73194.515847 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84243.488827 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84031.253910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84031.253910 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -487,7 +550,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.850453 # insts written-back per cycle system.cpu.iew.wb_fanout 0.573064 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 840604148 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 426565585 # The number of committed instructions +system.cpu.commit.commitCommittedOps 840604148 # The number of committed instructions system.cpu.commit.commitSquashedInsts 30510484 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1519690 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1250933 # The number of times a branch was mispredicted @@ -508,7 +572,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 302314482 # Number of insts commited each cycle -system.cpu.commit.count 840604148 # Number of instructions committed +system.cpu.commit.committedInsts 426565585 # Number of instructions committed +system.cpu.commit.committedOps 840604148 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 23747567 # Number of memory references committed system.cpu.commit.loads 15324009 # Number of loads committed @@ -524,12 +589,13 @@ system.cpu.rob.rob_writes 1746826364 # Th system.cpu.timesIdled 2858532 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 155577248 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 9864170951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 840604148 # Number of Instructions Simulated -system.cpu.committedInsts_total 840604148 # Number of Instructions Simulated -system.cpu.cpi 0.550153 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.550153 # CPI: Total CPI of All Threads -system.cpu.ipc 1.817677 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.817677 # IPC: Total IPC of All Threads +system.cpu.committedInsts 426565585 # Number of Instructions Simulated +system.cpu.committedOps 840604148 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 426565585 # Number of Instructions Simulated +system.cpu.cpi 1.084149 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.084149 # CPI: Total CPI of All Threads +system.cpu.ipc 0.922382 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.922382 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 1406313694 # number of integer regfile reads system.cpu.int_regfile_writes 857070459 # number of integer regfile writes system.cpu.fp_regfile_reads 62 # number of floating regfile reads @@ -541,51 +607,39 @@ system.cpu.icache.total_refs 8587640 # To system.cpu.icache.sampled_refs 1020665 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 8.413769 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 56648796000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.928344 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.995954 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8587640 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 509.928344 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.995954 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.995954 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8587640 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 8587640 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8587640 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 8587640 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 8587640 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8587640 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 8587640 # number of overall hits system.cpu.icache.overall_hits::total 8587640 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1084449 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 1084449 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1084449 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1084449 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 1084449 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1084449 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1084449 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 1084449 # number of overall misses system.cpu.icache.overall_misses::total 1084449 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16282601991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16282601991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16282601991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9672089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16282601991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16282601991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16282601991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16282601991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16282601991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16282601991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9672089 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9672089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9672089 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 9672089 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 9672089 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9672089 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9672089 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 9672089 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.112121 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.112121 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.112121 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 15014.631385 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 15014.631385 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 15014.631385 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112121 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.112121 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.112121 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15014.631385 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15014.631385 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15014.631385 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2694492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 263 # number of cycles access was blocked @@ -594,33 +648,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 10245.216730 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1551 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 60108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 60108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 60108 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1024341 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1024341 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1024341 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12392610492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12392610492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12392610492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.105907 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.105907 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.105907 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12098.129912 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12098.129912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12098.129912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 1551 # number of writebacks +system.cpu.icache.writebacks::total 1551 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60108 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 60108 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 60108 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 60108 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 60108 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 60108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1024341 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1024341 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1024341 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1024341 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1024341 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1024341 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12392610492 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12392610492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12392610492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12392610492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12392610492 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12392610492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12098.129912 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12098.129912 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12098.129912 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 8553 # number of replacements system.cpu.itb_walker_cache.tagsinuse 6.010935 # Cycle average of tags in use @@ -628,55 +681,43 @@ system.cpu.itb_walker_cache.total_refs 26637 # To system.cpu.itb_walker_cache.sampled_refs 8564 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 3.110346 # Average number of references to valid blocks. system.cpu.itb_walker_cache.warmup_cycle 5140402124000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 6.010935 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.375683 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 26742 # number of ReadReq hits +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.010935 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375683 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375683 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26742 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 26742 # number of ReadReq hits -system.cpu.itb_walker_cache.WriteReq_hits::1 3 # number of WriteReq hits +system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 26745 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26745 # number of demand (read+write) hits system.cpu.itb_walker_cache.demand_hits::total 26745 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 26745 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26745 # number of overall hits system.cpu.itb_walker_cache.overall_hits::total 26745 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 9424 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9424 # number of ReadReq misses system.cpu.itb_walker_cache.ReadReq_misses::total 9424 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 9424 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9424 # number of demand (read+write) misses system.cpu.itb_walker_cache.demand_misses::total 9424 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 9424 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9424 # number of overall misses system.cpu.itb_walker_cache.overall_misses::total 9424 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 120935500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 120935500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 120935500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 36166 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 120935500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 120935500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 120935500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 120935500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 120935500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 120935500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36166 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.ReadReq_accesses::total 36166 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) +system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 36169 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36169 # number of demand (read+write) accesses system.cpu.itb_walker_cache.demand_accesses::total 36169 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 36169 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36169 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 36169 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.260576 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.260555 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.260555 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12832.714346 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12832.714346 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12832.714346 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.260576 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.260555 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.260555 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12832.714346 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12832.714346 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12832.714346 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,32 +726,26 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 1616 # number of writebacks -system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 9424 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 9424 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 9424 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 92324000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 92324000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 92324000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.260576 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.260555 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.260555 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9796.689304 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9796.689304 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9796.689304 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.itb_walker_cache.writebacks::writebacks 1616 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1616 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9424 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9424 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9424 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 9424 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9424 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 9424 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 92324000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 92324000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 92324000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 92324000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 92324000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 92324000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.260576 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.260555 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.260555 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.replacements 140574 # number of replacements system.cpu.dtb_walker_cache.tagsinuse 13.858803 # Cycle average of tags in use @@ -718,51 +753,39 @@ system.cpu.dtb_walker_cache.total_refs 148049 # To system.cpu.dtb_walker_cache.sampled_refs 140589 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.053062 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5108661869000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.858803 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.866175 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 148058 # number of ReadReq hits +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.858803 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866175 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.866175 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 148058 # number of ReadReq hits system.cpu.dtb_walker_cache.ReadReq_hits::total 148058 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 148058 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 148058 # number of demand (read+write) hits system.cpu.dtb_walker_cache.demand_hits::total 148058 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 148058 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 148058 # number of overall hits system.cpu.dtb_walker_cache.overall_hits::total 148058 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 141571 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 141571 # number of ReadReq misses system.cpu.dtb_walker_cache.ReadReq_misses::total 141571 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 141571 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 141571 # number of demand (read+write) misses system.cpu.dtb_walker_cache.demand_misses::total 141571 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 141571 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 141571 # number of overall misses system.cpu.dtb_walker_cache.overall_misses::total 141571 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 1989434500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 1989434500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 1989434500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 289629 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1989434500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1989434500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1989434500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1989434500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1989434500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1989434500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 289629 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 289629 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 289629 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 289629 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 289629 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 289629 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 289629 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 289629 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.488801 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.488801 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.488801 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 14052.556668 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 14052.556668 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 14052.556668 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.488801 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.488801 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.488801 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 14052.556668 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 14052.556668 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 14052.556668 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -771,32 +794,26 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 49457 # number of writebacks -system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 141571 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 141571 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 141571 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1560743500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1560743500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1560743500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.488801 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.488801 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.488801 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 11024.457693 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 11024.457693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 11024.457693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dtb_walker_cache.writebacks::writebacks 49457 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 49457 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 141571 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 141571 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 141571 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 141571 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 141571 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 141571 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1560743500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1560743500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1560743500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1662584 # number of replacements system.cpu.dcache.tagsinuse 511.995323 # Cycle average of tags in use @@ -804,62 +821,49 @@ system.cpu.dcache.total_refs 19274168 # To system.cpu.dcache.sampled_refs 1663096 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.589330 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 34335000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.995323 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11173849 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.995323 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11173849 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 11173849 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 8093995 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8093995 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 8093995 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 19267844 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 19267844 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 19267844 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 19267844 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 19267844 # number of overall hits system.cpu.dcache.overall_hits::total 19267844 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 2389581 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 2389581 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2389581 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 320205 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 320205 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 320205 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 2709786 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 2709786 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2709786 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 2709786 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 2709786 # number of overall misses system.cpu.dcache.overall_misses::total 2709786 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 35746262500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10712131492 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 46458393992 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 46458393992 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13563430 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35746262500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35746262500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10712131492 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10712131492 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46458393992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46458393992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46458393992 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46458393992 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563430 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13563430 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8414200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8414200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 8414200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 21977630 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 21977630 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 21977630 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 21977630 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21977630 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21977630 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.176178 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.038055 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.123297 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.123297 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 14959.217746 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33453.979457 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 17144.672676 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 17144.672676 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.176178 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038055 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.123297 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.123297 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14959.217746 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33453.979457 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17144.672676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17144.672676 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 27702492 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4792 # number of cycles access was blocked @@ -868,44 +872,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 5780.987479 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1550496 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1018010 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 22803 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1040813 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1040813 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1371571 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 297402 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1668973 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1668973 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 18013626000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9484899492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27498525492 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27498525492 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 85207760000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1392508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 86600268500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.101123 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035345 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.075940 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.075940 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13133.571649 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31892.520871 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16476.315370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16476.315370 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 1550496 # number of writebacks +system.cpu.dcache.writebacks::total 1550496 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1018010 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1018010 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22803 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 22803 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1040813 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1040813 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1040813 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1040813 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371571 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1371571 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 297402 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 297402 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1668973 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1668973 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1668973 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1668973 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18013626000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18013626000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9484899492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9484899492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27498525492 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27498525492 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27498525492 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27498525492 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207760000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207760000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1392508500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392508500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600268500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600268500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.101123 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035345 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075940 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075940 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13133.571649 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31892.520871 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16476.315370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16476.315370 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index 409b736b6..490c0c72f 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=200000000 time_sync_spin_threshold=200000 @@ -8,7 +9,6 @@ time_sync_spin_threshold=200000 [system] type=SparcSystem children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000 -boot_cpu_frequency=1 boot_osflags=a hypervisor_addr=1099243257856 hypervisor_bin=/dist/m5/system/binaries/q_new.bin @@ -19,7 +19,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic -memories=system.physmem2 system.nvram system.partition_desc system.rom system.physmem system.hypervisor_desc +memories=system.rom system.hypervisor_desc system.physmem2 system.nvram system.physmem system.partition_desc num_work_ids=16 nvram=system.nvram nvram_addr=133429198848 @@ -83,6 +83,7 @@ simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 +workload= dcache_port=system.membus.port[11] icache_port=system.membus.port[10] @@ -106,7 +107,6 @@ children=image image=system.disk0.image pio_addr=134217728000 pio_latency=2 -platform=system.t1000 system=system pio=system.iobus.port[15] @@ -165,7 +165,6 @@ fake_mem=false pio_addr=0 pio_latency=2 pio_size=8 -platform=system.t1000 ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -238,7 +237,6 @@ fake_mem=false pio_addr=644245094400 pio_latency=2 pio_size=4294967296 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -255,7 +253,6 @@ fake_mem=false pio_addr=549755813888 pio_latency=2 pio_size=4294967296 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -272,7 +269,6 @@ fake_mem=false pio_addr=725849473024 pio_latency=2 pio_size=8 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -289,7 +285,6 @@ fake_mem=false pio_addr=725849473088 pio_latency=2 pio_size=8 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -306,7 +301,6 @@ fake_mem=false pio_addr=725849473152 pio_latency=2 pio_size=8 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -323,7 +317,6 @@ fake_mem=false pio_addr=725849473216 pio_latency=2 pio_size=8 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -340,7 +333,6 @@ fake_mem=false pio_addr=734439407616 pio_latency=2 pio_size=8 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -357,7 +349,6 @@ fake_mem=false pio_addr=734439407680 pio_latency=2 pio_size=8 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -374,7 +365,6 @@ fake_mem=false pio_addr=734439407744 pio_latency=2 pio_size=8 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -391,7 +381,6 @@ fake_mem=false pio_addr=734439407808 pio_latency=2 pio_size=8 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -408,7 +397,6 @@ fake_mem=false pio_addr=648540061696 pio_latency=2 pio_size=16384 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -425,7 +413,6 @@ fake_mem=false pio_addr=1095216660480 pio_latency=2 pio_size=268435456 -platform=system.t1000 ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -447,7 +434,6 @@ port=3456 type=DumbTOD pio_addr=1099255906296 pio_latency=2 -platform=system.t1000 system=system time=Thu Jan 1 00:00:00 2009 pio=system.membus.port[1] diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout index d81b5c20f..c2315f7a1 100755 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -1,14 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:05:05 -gem5 started Jan 23 2012 06:26:23 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 14:02:46 gem5 executing on zizzer -command line: build/SPARC_FS/gem5.opt -d build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second - 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 - - 0: system.t1000.htod: Real-time clock set to 1230768000 info: No kernel set for full system simulation. Assuming you know what you're doing... info: Entering event queue @ 0. Starting simulation... info: Ignoring write to SPARC ERROR regsiter diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 21a50a501..26c5818ca 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.116889 # Nu sim_ticks 2233777512 # Number of ticks simulated final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 2000000000 # Frequency of simulated ticks -host_inst_rate 3505728 # Simulator instruction rate (inst/s) -host_tick_rate 3512989 # Simulator tick rate (ticks/s) -host_mem_usage 500940 # Number of bytes of host memory used -host_seconds 635.86 # Real time elapsed on the host -sim_insts 2229160714 # Number of instructions simulated +host_inst_rate 4520258 # Simulator instruction rate (inst/s) +host_op_rate 4522035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4531400 # Simulator tick rate (ticks/s) +host_mem_usage 500812 # Number of bytes of host memory used +host_seconds 492.96 # Real time elapsed on the host +sim_insts 2228284650 # Number of instructions simulated +sim_ops 2229160714 # Number of ops (including micro ops) simulated system.hypervisor_desc.bytes_read 16792 # Number of bytes read from this memory system.hypervisor_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory system.hypervisor_desc.bytes_written 0 # Number of bytes written to this memory @@ -17,6 +19,15 @@ system.hypervisor_desc.num_writes 0 # Nu system.hypervisor_desc.num_other 0 # Number of other requests responded to by this memory system.hypervisor_desc.bw_read 15035 # Total read bandwidth from this memory (bytes/s) system.hypervisor_desc.bw_total 15035 # Total bandwidth to/from this memory (bytes/s) +system.rom.bytes_read 1128688 # Number of bytes read from this memory +system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory +system.rom.bytes_written 0 # Number of bytes written to this memory +system.rom.num_reads 195123 # Number of read requests responded to by this memory +system.rom.num_writes 0 # Number of write requests responded to by this memory +system.rom.num_other 0 # Number of other requests responded to by this memory +system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s) system.physmem2.bytes_read 9813991967 # Number of bytes read from this memory system.physmem2.bytes_inst_read 8318106840 # Number of instructions bytes read from this memory system.physmem2.bytes_written 897268422 # Number of bytes written to this memory @@ -36,23 +47,6 @@ system.nvram.num_other 0 # Nu system.nvram.bw_read 254 # Total read bandwidth from this memory (bytes/s) system.nvram.bw_write 82 # Write bandwidth from this memory (bytes/s) system.nvram.bw_total 337 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bytes_read 4846 # Number of bytes read from this memory -system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.partition_desc.bytes_written 0 # Number of bytes written to this memory -system.partition_desc.num_reads 608 # Number of read requests responded to by this memory -system.partition_desc.num_writes 0 # Number of write requests responded to by this memory -system.partition_desc.num_other 0 # Number of other requests responded to by this memory -system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s) -system.rom.bytes_read 1128688 # Number of bytes read from this memory -system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory -system.rom.bytes_written 0 # Number of bytes written to this memory -system.rom.num_reads 195123 # Number of read requests responded to by this memory -system.rom.num_writes 0 # Number of write requests responded to by this memory -system.rom.num_other 0 # Number of other requests responded to by this memory -system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read 709825348 # Number of bytes read from this memory system.physmem.bytes_inst_read 612291324 # Number of instructions bytes read from this memory system.physmem.bytes_written 15400223 # Number of bytes written to this memory @@ -63,10 +57,19 @@ system.physmem.bw_read 635538091 # To system.physmem.bw_inst_read 548211557 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write 13788502 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total 649326593 # Total bandwidth to/from this memory (bytes/s) +system.partition_desc.bytes_read 4846 # Number of bytes read from this memory +system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory +system.partition_desc.bytes_written 0 # Number of bytes written to this memory +system.partition_desc.num_reads 608 # Number of read requests responded to by this memory +system.partition_desc.num_writes 0 # Number of write requests responded to by this memory +system.partition_desc.num_other 0 # Number of other requests responded to by this memory +system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s) +system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s) system.cpu.numCycles 2233777513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2229160714 # Number of instructions executed +system.cpu.committedInsts 2228284650 # Number of instructions committed +system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses system.cpu.num_func_calls 44037246 # number of times a function call or return occured |