diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:41:27 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:41:27 -0500 |
| commit | af2e83c7f13098b66ceb6ba69599f1959da44ea1 (patch) | |
| tree | a634f32d705cb32d614dcd43d819d8e3e26dd547 /tests/long/fs | |
| parent | 22b60c57e697289baa205f11b164f356363c2bee (diff) | |
| download | gem5-af2e83c7f13098b66ceb6ba69599f1959da44ea1.tar.xz | |
x86, regressions: updates stats
This is due to op class, function call, walker patches.
Diffstat (limited to 'tests/long/fs')
3 files changed, 2185 insertions, 2188 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 77940f18e..8f4e7d03c 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.132953 # Number of seconds simulated -sim_ticks 5132953103000 # Number of ticks simulated -final_tick 5132953103000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.140938 # Number of seconds simulated +sim_ticks 5140937585000 # Number of ticks simulated +final_tick 5140937585000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118788 # Simulator instruction rate (inst/s) -host_op_rate 234812 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1494512187 # Simulator tick rate (ticks/s) -host_mem_usage 768808 # Number of bytes of host memory used -host_seconds 3434.53 # Real time elapsed on the host -sim_insts 407981680 # Number of instructions simulated -sim_ops 806469686 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2427072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1080064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10859584 # Number of bytes read from this memory -system.physmem.bytes_read::total 14370176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1080064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1080064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9570112 # Number of bytes written to this memory -system.physmem.bytes_written::total 9570112 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 37923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16876 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169681 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224534 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149533 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149533 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 472841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2115660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2799592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1864446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1864446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1864446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 472841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2115660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4664038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 224534 # Total number of read requests seen -system.physmem.writeReqs 149533 # Total number of write requests seen -system.physmem.cpureqs 378540 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14370176 # Total number of bytes read from memory -system.physmem.bytesWritten 9570112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14370176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9570112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 118 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4466 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14182 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13087 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 16327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 15686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13366 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15652 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8678 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8635 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 11642 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8788 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8537 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8431 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 11660 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 9003 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 11092 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8524 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8172 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8641 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 11087 # Track writes on a per bank basis +host_inst_rate 121697 # Simulator instruction rate (inst/s) +host_op_rate 240559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1534230705 # Simulator tick rate (ticks/s) +host_mem_usage 773616 # Number of bytes of host memory used +host_seconds 3350.82 # Real time elapsed on the host +sim_insts 407786881 # Number of instructions simulated +sim_ops 806071515 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2479872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1026240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10765120 # Number of bytes read from this memory +system.physmem.bytes_read::total 14275328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1026240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1026240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9536256 # Number of bytes written to this memory +system.physmem.bytes_written::total 9536256 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16035 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168205 # Number of read requests responded to by this memory +system.physmem.num_reads::total 223052 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149004 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149004 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2093999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2776795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199621 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199621 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1854964 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1854964 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1854964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2093999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4631759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 223052 # Total number of read requests seen +system.physmem.writeReqs 149004 # Total number of write requests seen +system.physmem.cpureqs 373790 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14275328 # Total number of bytes read from memory +system.physmem.bytesWritten 9536256 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14275328 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9536256 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 13636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13124 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13111 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13382 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13394 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 15885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13088 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12601 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13202 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15809 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 8387 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8583 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 11810 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8818 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8522 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 11661 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8790 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8601 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8761 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 11230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8431 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8093 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8583 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 11174 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 5132953050000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry +system.physmem.totGap 5140937531500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 224534 # Categorize read packet sizes +system.physmem.readPktSize::6 223052 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 149533 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 174096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 19313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1047 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149004 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 172997 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 18175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -136,92 +136,92 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.totQLat 4726159249 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9244557999 # Sum of mem lat for all requests -system.physmem.totBusLat 1122080000 # Total cycles spent in databus access -system.physmem.totBankLat 3396318750 # Total cycles spent in bank access -system.physmem.avgQLat 21059.81 # Average queueing delay per request -system.physmem.avgBankLat 15134.03 # Average bank access latency per request +system.physmem.totQLat 4794975750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9301923250 # Sum of mem lat for all requests +system.physmem.totBusLat 1114905000 # Total cycles spent in databus access +system.physmem.totBankLat 3392042500 # Total cycles spent in bank access +system.physmem.avgQLat 21503.97 # Average queueing delay per request +system.physmem.avgBankLat 15212.25 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41193.85 # Average memory access latency -system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 41716.21 # Average memory access latency +system.physmem.avgRdBW 2.78 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.69 # Average write queue length over time -system.physmem.readRowHits 193610 # Number of row buffer hits during reads -system.physmem.writeRowHits 105925 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.84 # Row buffer hit rate for writes -system.physmem.avgGap 13722015.17 # Average gap between requests -system.iocache.replacements 47570 # number of replacements -system.iocache.tagsinuse 0.103974 # Cycle average of tags in use +system.physmem.avgWrQLen 15.58 # Average write queue length over time +system.physmem.readRowHits 191257 # Number of row buffer hits during reads +system.physmem.writeRowHits 105612 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.88 # Row buffer hit rate for writes +system.physmem.avgGap 13817644.47 # Average gap between requests +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.128763 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991995541000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.103974 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006498 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006498 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses +system.iocache.warmup_cycle 4991974997000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.128763 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.008048 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.008048 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses -system.iocache.demand_misses::total 47625 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses -system.iocache.overall_misses::total 47625 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 145555660 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 145555660 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10008674105 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10008674105 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10154229765 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10154229765 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10154229765 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10154229765 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147497397 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 147497397 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10072244306 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10072244306 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10219741703 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10219741703 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10219741703 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10219741703 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -230,40 +230,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160834.983425 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 160834.983425 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214226.757384 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 214226.757384 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213212.173543 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 213212.173543 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213212.173543 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 213212.173543 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 133059 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 161907.131723 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 161907.131723 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215587.420933 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 215587.420933 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 214560.721022 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 214560.721022 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 139153 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12235 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12645 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.875276 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.004587 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 905 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47625 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47625 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47625 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47625 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98473941 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 98473941 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7577901783 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7577901783 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7676375724 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7676375724 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7676375724 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7676375724 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100104427 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100104427 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7641446543 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7641446543 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7741550970 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7741550970 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -272,18 +272,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108810.984530 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 108810.984530 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162198.240218 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 162198.240218 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161183.742236 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 161183.742236 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161183.742236 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 161183.742236 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 109884.113063 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 109884.113063 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163558.359225 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 163558.359225 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -293,410 +293,410 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 86237029 # Number of BP lookups -system.cpu.branchPred.condPredicted 86237029 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1109949 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 81299216 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79239397 # Number of BTB hits +system.cpu.branchPred.lookups 85620726 # Number of BP lookups +system.cpu.branchPred.condPredicted 85620726 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 882198 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79268619 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77534559 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.466373 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.numCycles 448469531 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.812426 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1442315 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180251 # Number of incorrect RAS predictions. +system.cpu.numCycles 447791761 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27529474 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 426122909 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86237029 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79239397 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163627324 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4728707 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 117219 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 63156445 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36498 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 53889 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 420 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9038392 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 487130 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2791 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 258101520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.259173 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.417982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25559948 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422856490 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85620726 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78976874 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162677741 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4000997 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 98298 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 65919320 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 43594 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86507 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 459 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8492083 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 383635 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2345 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257461374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.243647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.415529 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94901402 36.77% 36.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1566001 0.61% 37.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71924847 27.87% 65.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 935145 0.36% 65.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1600289 0.62% 66.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2428838 0.94% 67.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1075499 0.42% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1377865 0.53% 68.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82291634 31.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95198026 36.98% 36.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1534816 0.60% 37.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71825104 27.90% 65.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 895357 0.35% 65.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1570607 0.61% 66.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2391332 0.93% 67.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1020158 0.40% 67.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1325162 0.51% 68.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81700812 31.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 258101520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192292 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.950171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31223769 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60616281 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159439032 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3242187 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3580251 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838065302 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 921 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3580251 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33968457 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37481730 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11034324 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159610574 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12426184 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834407058 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18980 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5821881 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4760224 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8257 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 995986207 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1811362671 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1811361735 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 936 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964469787 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31516413 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 458013 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 465231 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28772388 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17093245 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10135018 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1252851 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1005934 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828306143 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1250828 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823325440 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 150511 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22168488 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33636711 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 196648 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 258101520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.189929 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.384557 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257461374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.191207 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.944315 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29461192 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63064302 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158550724 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3309649 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3075507 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832761340 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 863 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3075507 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32153278 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38465118 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12079112 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158824437 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12863922 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829829025 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19879 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6055166 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4924546 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11525 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 991492877 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800847756 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1800847292 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 464 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963999366 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27493506 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 456551 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 462682 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29304477 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16752339 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9837983 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1099709 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 928773 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 825036488 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1186686 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 821069910 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 146070 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19309743 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29357166 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 131932 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257461374 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.189099 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.383585 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71580535 27.73% 27.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15499802 6.01% 33.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10327986 4.00% 37.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7455254 2.89% 40.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75927506 29.42% 70.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3856019 1.49% 71.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72517162 28.10% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 787235 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 150021 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71259249 27.68% 27.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15575755 6.05% 33.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10479111 4.07% 37.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7383615 2.87% 40.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75752504 29.42% 70.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3772068 1.47% 71.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72307575 28.08% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 782694 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 148803 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 258101520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257461374 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 366750 34.22% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553108 51.61% 85.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 151931 14.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 356313 33.63% 33.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 241 0.02% 33.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 2452 0.23% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547502 51.68% 85.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152922 14.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 309801 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795758940 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17866354 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9390345 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 308526 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793557907 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150412 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124298 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17694567 2.16% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9234200 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823325440 # Type of FU issued -system.cpu.iq.rate 1.835856 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1071789 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001302 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1906104602 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851735215 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818848735 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 378 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 94 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 824087257 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 171 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1645357 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 821069910 # Type of FU issued +system.cpu.iq.rate 1.833598 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1059430 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001290 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1900915279 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845543458 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817157785 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 194 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821820724 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1686147 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3104742 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 23669 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11440 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1716567 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2748440 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17101 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11930 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1411969 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932461 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11842 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931504 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11624 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3580251 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26245227 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2113533 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829556971 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 304073 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17093245 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10135018 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 718533 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1617499 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11192 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11440 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 653820 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 594083 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1247903 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821445654 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17451760 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1879785 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3075507 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26873503 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2150322 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826223174 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241070 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16752339 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9837983 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 692103 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1621529 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12267 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11930 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498132 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506603 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1004735 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819660888 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17391685 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1409021 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26608752 # number of memory reference insts executed -system.cpu.iew.exec_branches 83225006 # Number of branches executed -system.cpu.iew.exec_stores 9156992 # Number of stores executed -system.cpu.iew.exec_rate 1.831664 # Inst execution rate -system.cpu.iew.wb_sent 820984205 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818848829 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639993786 # num instructions producing a value -system.cpu.iew.wb_consumers 1045886534 # num instructions consuming a value +system.cpu.iew.exec_refs 26440023 # number of memory reference insts executed +system.cpu.iew.exec_branches 83107253 # Number of branches executed +system.cpu.iew.exec_stores 9048338 # Number of stores executed +system.cpu.iew.exec_rate 1.830451 # Inst execution rate +system.cpu.iew.wb_sent 819258374 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817157837 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638799704 # num instructions producing a value +system.cpu.iew.wb_consumers 1044337102 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.825874 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611915 # average fanout of values written-back +system.cpu.iew.wb_rate 1.824861 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611680 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22977930 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054178 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1115022 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254521269 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.168575 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.855004 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 20042352 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054753 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 891546 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254385866 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.168696 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.858566 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82765060 32.52% 32.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11818595 4.64% 37.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3860584 1.52% 38.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74956276 29.45% 68.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2441275 0.96% 69.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1480165 0.58% 69.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 888603 0.35% 70.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70922136 27.86% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5388575 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82972146 32.62% 32.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11724447 4.61% 37.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3813249 1.50% 38.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74747378 29.38% 68.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2384925 0.94% 69.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1476326 0.58% 69.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 865615 0.34% 69.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70850824 27.85% 97.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5550956 2.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254521269 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407981680 # Number of instructions committed -system.cpu.commit.committedOps 806469686 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254385866 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407786881 # Number of instructions committed +system.cpu.commit.committedOps 806071515 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22406951 # Number of memory references committed -system.cpu.commit.loads 13988500 # Number of loads committed -system.cpu.commit.membars 474453 # Number of memory barriers committed -system.cpu.commit.branches 82201236 # Number of branches committed +system.cpu.commit.refs 22429911 # Number of memory references committed +system.cpu.commit.loads 14003897 # Number of loads committed +system.cpu.commit.membars 474463 # Number of memory barriers committed +system.cpu.commit.branches 82163817 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735408262 # Number of committed integer instructions. -system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5388575 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 735061477 # Number of committed integer instructions. +system.cpu.commit.function_calls 1156045 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5550956 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1078502153 # The number of ROB reads -system.cpu.rob.rob_writes 1662494402 # The number of ROB writes -system.cpu.timesIdled 1221401 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190368011 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9817434094 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407981680 # Number of Instructions Simulated -system.cpu.committedOps 806469686 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407981680 # Number of Instructions Simulated -system.cpu.cpi 1.099239 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.099239 # CPI: Total CPI of All Threads -system.cpu.ipc 0.909720 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.909720 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1507130605 # number of integer regfile reads -system.cpu.int_regfile_writes 977067823 # number of integer regfile writes -system.cpu.fp_regfile_reads 94 # number of floating regfile reads -system.cpu.misc_regfile_reads 264732336 # number of misc regfile reads -system.cpu.misc_regfile_writes 402254 # number of misc regfile writes -system.cpu.icache.replacements 1049385 # number of replacements -system.cpu.icache.tagsinuse 509.447090 # Cycle average of tags in use -system.cpu.icache.total_refs 7923264 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1049897 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.546706 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56158934000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.447090 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.995014 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.995014 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7923264 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7923264 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7923264 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7923264 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7923264 # number of overall hits -system.cpu.icache.overall_hits::total 7923264 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1115125 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1115125 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1115125 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1115125 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1115125 # number of overall misses -system.cpu.icache.overall_misses::total 1115125 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15322207492 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15322207492 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15322207492 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15322207492 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15322207492 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15322207492 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9038389 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9038389 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9038389 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9038389 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9038389 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9038389 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123377 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123377 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123377 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123377 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123377 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123377 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13740.349729 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13740.349729 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13740.349729 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13740.349729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13740.349729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13740.349729 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 10877 # number of cycles access was blocked +system.cpu.rob.rob_reads 1074870508 # The number of ROB reads +system.cpu.rob.rob_writes 1655318425 # The number of ROB writes +system.cpu.timesIdled 1256763 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190330387 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9834088814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407786881 # Number of Instructions Simulated +system.cpu.committedOps 806071515 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407786881 # Number of Instructions Simulated +system.cpu.cpi 1.098102 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.098102 # CPI: Total CPI of All Threads +system.cpu.ipc 0.910662 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.910662 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1504614065 # number of integer regfile reads +system.cpu.int_regfile_writes 975429838 # number of integer regfile writes +system.cpu.fp_regfile_reads 52 # number of floating regfile reads +system.cpu.misc_regfile_reads 264130300 # number of misc regfile reads +system.cpu.misc_regfile_writes 403010 # number of misc regfile writes +system.cpu.icache.replacements 955437 # number of replacements +system.cpu.icache.tagsinuse 509.903328 # Cycle average of tags in use +system.cpu.icache.total_refs 7482159 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 955949 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.826944 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 146514700000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.903328 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.995905 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.995905 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7482159 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7482159 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7482159 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7482159 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7482159 # number of overall hits +system.cpu.icache.overall_hits::total 7482159 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1009922 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1009922 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1009922 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1009922 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1009922 # number of overall misses +system.cpu.icache.overall_misses::total 1009922 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13938284992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13938284992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13938284992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13938284992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13938284992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13938284992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8492081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8492081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8492081 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8492081 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8492081 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8492081 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118925 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.118925 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.118925 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.118925 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.118925 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.118925 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.348017 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13801.348017 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13801.348017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13801.348017 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8199 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 301 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 36.136213 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.389163 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62547 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 62547 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 62547 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 62547 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 62547 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 62547 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1052578 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1052578 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1052578 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1052578 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1052578 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1052578 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12612158993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12612158993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12612158993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12612158993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12612158993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12612158993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116456 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116456 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116456 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116456 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116456 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116456 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11982.160935 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11982.160935 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11982.160935 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11982.160935 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11982.160935 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11982.160935 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53908 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53908 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53908 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53908 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53908 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53908 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 956014 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 956014 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 956014 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 956014 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 956014 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 956014 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11502740492 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11502740492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11502740492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11502740492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11502740492 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11502740492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112577 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.112577 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112577 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.979126 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.979126 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 8504 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.007408 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 27369 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 8519 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.212701 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5106816403500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.007408 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375463 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375463 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27369 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 27369 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 7960 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.326712 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 20386 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 7973 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.556879 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5107329698000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.326712 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.395420 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.395420 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20403 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 20403 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27371 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 27371 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27371 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 27371 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9373 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9373 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9373 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 9373 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 104966500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 104966500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 104966500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 104966500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 104966500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 104966500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36742 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 36742 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20405 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 20405 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20405 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 20405 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8843 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 8843 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8843 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 8843 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8843 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 8843 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 96821500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 96821500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 96821500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 96821500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 96821500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 96821500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 29246 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 29246 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36744 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 36744 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36744 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 36744 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.255103 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.255103 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.255089 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.255089 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.255089 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.255089 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11198.815747 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11198.815747 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11198.815747 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11198.815747 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11198.815747 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11198.815747 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 29248 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 29248 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 29248 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 29248 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.302366 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.302366 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.302345 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.302345 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.302345 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.302345 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10948.942667 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10948.942667 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10948.942667 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10948.942667 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10948.942667 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10948.942667 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -705,78 +705,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1896 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1896 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9373 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9373 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9373 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9373 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9373 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9373 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86220500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86220500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86220500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86220500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86220500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86220500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.255103 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.255103 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.255089 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.255089 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.255089 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.255089 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9198.815747 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9198.815747 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9198.815747 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9198.815747 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9198.815747 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9198.815747 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1394 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1394 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8843 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8843 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8843 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 8843 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8843 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 8843 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 79135500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 79135500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 79135500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 79135500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 79135500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 79135500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.302366 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.302366 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.302345 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.302345 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8948.942667 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 107843 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.947477 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 134583 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 107858 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.247779 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5099863447000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.947477 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809217 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.809217 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134601 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 134601 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134601 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 134601 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134601 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 134601 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108812 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 108812 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108812 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 108812 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108812 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 108812 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1371802000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1371802000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1371802000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1371802000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1371802000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1371802000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243413 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 243413 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243413 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 243413 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243413 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 243413 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447026 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447026 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447026 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447026 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447026 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447026 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12607.083778 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12607.083778 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12607.083778 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12607.083778 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12607.083778 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12607.083778 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 67560 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 14.837353 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 92239 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 67575 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.364987 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100574572500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.837353 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.927335 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.927335 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92240 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 92240 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92240 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 92240 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92240 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 92240 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68644 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 68644 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68644 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 68644 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68644 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 68644 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 852599000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 852599000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 852599000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 852599000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 852599000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 852599000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160884 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 160884 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160884 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 160884 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160884 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 160884 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.426668 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.426668 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.426668 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.426668 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.426668 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.426668 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12420.590292 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12420.590292 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12420.590292 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12420.590292 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -785,146 +785,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 34946 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 34946 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108812 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108812 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108812 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 108812 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108812 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 108812 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1154178000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1154178000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1154178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1154178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1154178000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1154178000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447026 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447026 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447026 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447026 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447026 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447026 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10607.083778 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10607.083778 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10607.083778 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 19876 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 19876 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68644 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68644 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68644 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 68644 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68644 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 68644 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 715311000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 715311000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 715311000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 715311000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 715311000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 715311000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.426668 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.426668 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.426668 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10420.590292 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1657617 # number of replacements -system.cpu.dcache.tagsinuse 511.997737 # Cycle average of tags in use -system.cpu.dcache.total_refs 19103102 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1658129 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.520878 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27986000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997737 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11006955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11006955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8090467 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8090467 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19097422 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19097422 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19097422 # number of overall hits -system.cpu.dcache.overall_hits::total 19097422 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2237002 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2237002 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318492 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318492 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2555494 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2555494 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2555494 # number of overall misses -system.cpu.dcache.overall_misses::total 2555494 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32016735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32016735000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9683080495 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9683080495 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41699815495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41699815495 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41699815495 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41699815495 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13243957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13243957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8408959 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8408959 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21652916 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21652916 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21652916 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21652916 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168907 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.168907 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037875 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037875 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118021 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118021 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14312.340803 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14312.340803 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30402.900214 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30402.900214 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16317.712151 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16317.712151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16317.712151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16317.712151 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 383482 # number of cycles access was blocked +system.cpu.dcache.replacements 1655094 # number of replacements +system.cpu.dcache.tagsinuse 511.995445 # Cycle average of tags in use +system.cpu.dcache.total_refs 19021390 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1655606 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.489080 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 27980000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995445 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10917270 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10917270 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8101435 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8101435 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19018705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19018705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19018705 # number of overall hits +system.cpu.dcache.overall_hits::total 19018705 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2239579 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2239579 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315092 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315092 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2554671 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2554671 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2554671 # number of overall misses +system.cpu.dcache.overall_misses::total 2554671 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31946998000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31946998000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9622210995 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9622210995 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41569208995 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41569208995 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41569208995 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41569208995 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13156849 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13156849 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8416527 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8416527 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21573376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21573376 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21573376 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21573376 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037437 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037437 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118418 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118418 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118418 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118418 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14264.733684 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14264.733684 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30537.782600 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30537.782600 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16271.844396 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16271.844396 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16271.844396 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16271.844396 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 387071 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42249 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42390 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.076712 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.131187 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1559520 # number of writebacks -system.cpu.dcache.writebacks::total 1559520 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866015 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 866015 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26449 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 26449 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 892464 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 892464 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 892464 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 892464 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1370987 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1370987 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292043 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 292043 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1663030 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1663030 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1663030 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1663030 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17418217500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17418217500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8839751495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8839751495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26257968995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26257968995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26257968995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26257968995 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97350275500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97350275500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2525993500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2525993500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99876269000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99876269000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103518 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103518 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034730 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034730 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076804 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076804 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076804 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076804 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12704.874299 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12704.874299 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30268.664186 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30268.664186 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15789.233505 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15789.233505 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15789.233505 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15789.233505 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1557214 # number of writebacks +system.cpu.dcache.writebacks::total 1557214 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 870911 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 870911 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25892 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25892 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 896803 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 896803 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 896803 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 896803 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1368668 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1368668 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289200 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289200 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1657868 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1657868 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1657868 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1657868 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17401159000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17401159000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8794383495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8794383495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26195542495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26195542495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26195542495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26195542495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349101500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349101500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2522345500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2522345500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99871447000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99871447000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104027 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104027 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076848 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076848 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076848 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076848 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12713.937200 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12713.937200 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30409.348185 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30409.348185 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15800.740768 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15800.740768 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15800.740768 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15800.740768 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -932,141 +932,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 113549 # number of replacements -system.cpu.l2cache.tagsinuse 64828.327724 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3928640 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 177472 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.136675 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 111963 # number of replacements +system.cpu.l2cache.tagsinuse 64818.241357 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3779325 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 176193 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.449916 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50064.846561 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 9.159250 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.124586 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3285.119507 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11469.077820 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.763929 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000140 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.050127 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.175004 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989202 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102263 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7285 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1032873 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1333038 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2475459 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1596362 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1596362 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 310 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 310 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 153914 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 153914 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 102263 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 7285 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1032873 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1486952 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2629373 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 102263 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 7285 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1032873 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1486952 # number of overall hits -system.cpu.l2cache.overall_hits::total 2629373 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 49 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16879 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 36894 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 53827 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4124 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4124 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133799 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133799 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 49 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16879 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 170693 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 187626 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 49 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16879 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 170693 # number of overall misses -system.cpu.l2cache.overall_misses::total 187626 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4543000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 320500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1178779000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2492461998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3676104498 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17587000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17587000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6908700500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6908700500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4543000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 320500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1178779000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9401162498 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10584804998 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4543000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 320500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1178779000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9401162498 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10584804998 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 102312 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7290 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1049752 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1369932 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2529286 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1596362 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1596362 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4434 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4434 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287713 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287713 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 102312 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 7290 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1049752 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1657645 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2816999 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 102312 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 7290 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1049752 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1657645 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2816999 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000479 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000686 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016079 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026931 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021281 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.930086 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.930086 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.465043 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.465043 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000479 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000686 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016079 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102973 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.066605 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000479 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000686 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016079 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102973 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.066605 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92714.285714 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64100 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69837.016411 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67557.380550 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68294.805544 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4264.548982 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4264.548982 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51634.918796 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51634.918796 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92714.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64100 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69837.016411 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55076.438389 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56414.382857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92714.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64100 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69837.016411 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55076.438389 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56414.382857 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 50535.271880 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 14.689116 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.441967 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3088.733265 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11179.105128 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.771107 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000224 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.047130 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.170580 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989048 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63019 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 6673 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 939861 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1331810 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2341363 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1578484 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1578484 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 313 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 313 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 154035 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 154035 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 63019 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 6673 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 939861 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1485845 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2495398 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 63019 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 6673 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 939861 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1485845 # number of overall hits +system.cpu.l2cache.overall_hits::total 2495398 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 58 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16036 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 36136 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 52236 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1469 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1469 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133013 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133013 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 58 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16036 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169149 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 185249 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 58 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 16036 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169149 # number of overall misses +system.cpu.l2cache.overall_misses::total 185249 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4739500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 386000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1102660000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2500024999 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3607810499 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 18004500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 18004500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6917223500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6917223500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4739500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 386000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1102660000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9417248499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10525033999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4739500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 386000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1102660000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9417248499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10525033999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 63077 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 6679 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 955897 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1367946 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2393599 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1578484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1578484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1782 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1782 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 287048 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 287048 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 63077 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 6679 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 955897 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1654994 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2680647 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 63077 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 6679 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 955897 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1654994 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2680647 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000898 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016776 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026416 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021823 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.824355 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.824355 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463382 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.463382 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000898 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016776 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102205 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.069106 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000898 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016776 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102205 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.069106 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81715.517241 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64333.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68761.536543 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69183.777922 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69067.510893 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12256.296801 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12256.296801 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.116139 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.116139 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81715.517241 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64333.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68761.536543 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55674.278293 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56815.604937 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81715.517241 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64333.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68761.536543 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55674.278293 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56815.604937 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1075,99 +1075,96 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102866 # number of writebacks -system.cpu.l2cache.writebacks::total 102866 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 49 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16876 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36893 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 53823 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4124 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4124 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133799 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133799 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 49 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16876 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 170692 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 187622 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 49 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16876 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 170692 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 187622 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3930045 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 257504 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 968789302 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2034070067 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3007046918 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42432097 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42432097 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5258255507 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5258255507 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3930045 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 257504 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 968789302 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7292325574 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8265302425 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3930045 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 257504 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 968789302 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7292325574 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8265302425 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89237875000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89237875000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2360777500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2360777500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91598652500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91598652500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000686 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016076 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026931 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021280 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.930086 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.930086 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.465043 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.465043 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000686 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016076 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.066604 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000686 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016076 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.066604 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 80205 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 51500.800000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57406.334558 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55134.309137 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55869.180796 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10289.063288 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10289.063288 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39299.662232 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39299.662232 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 80205 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 51500.800000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57406.334558 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42722.128594 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44052.949148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 80205 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 51500.800000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57406.334558 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42722.128594 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44052.949148 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 102337 # number of writebacks +system.cpu.l2cache.writebacks::total 102337 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 58 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16035 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36136 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 52235 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1469 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1469 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133013 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133013 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 58 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16035 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169149 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185248 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 58 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16035 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169149 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185248 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4016555 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 310006 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 903103756 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2050826327 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2958256644 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15725947 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15725947 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5276958842 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5276958842 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4016555 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 310006 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 903103756 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327785169 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8235215486 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4016555 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 310006 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 903103756 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327785169 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8235215486 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236811500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236811500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2357396500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2357396500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91594208000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91594208000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000920 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000898 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016775 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026416 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021823 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.824355 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.824355 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463382 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463382 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000920 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000898 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016775 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102205 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069106 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000920 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000898 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016775 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102205 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.069106 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56320.783037 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56752.997758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56633.610491 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10705.205582 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10705.205582 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39672.504507 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39672.504507 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56320.783037 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43321.480878 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44455.084460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56320.783037 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43321.480878 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44455.084460 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index e29eb22f7..f3136422c 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.205149 # Nu sim_ticks 5205148879000 # Number of ticks simulated final_tick 5205148879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134092 # Simulator instruction rate (inst/s) -host_op_rate 257066 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6543163557 # Simulator tick rate (ticks/s) +host_inst_rate 131600 # Simulator instruction rate (inst/s) +host_op_rate 252290 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6421585329 # Simulator tick rate (ticks/s) host_mem_usage 872300 # Number of bytes of host memory used -host_seconds 795.51 # Real time elapsed on the host +host_seconds 810.57 # Real time elapsed on the host sim_insts 106671342 # Number of instructions simulated -sim_ops 204498755 # Number of ops (including micro ops) simulated +sim_ops 204498751 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 160344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 75328 # Number of bytes read from this memory @@ -264,10 +264,10 @@ system.cpu0.numCycles 10410297758 # nu system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 60288276 # Number of instructions committed -system.cpu0.committedOps 115773081 # Number of ops (including micro ops) committed +system.cpu0.committedOps 115773079 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 108731496 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 0 # number of times a function call or return occured +system.cpu0.num_func_calls 1065656 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 10277696 # number of instructions that are conditional controls system.cpu0.num_int_insts 108731496 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions @@ -288,10 +288,10 @@ system.cpu1.numCycles 10407399002 # nu system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 46383066 # Number of instructions committed -system.cpu1.committedOps 88725674 # Number of ops (including micro ops) committed +system.cpu1.committedOps 88725672 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 85218419 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 0 # number of times a function call or return occured +system.cpu1.num_func_calls 1670749 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 7955161 # number of instructions that are conditional controls system.cpu1.num_int_insts 85218419 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 09ee5a401..a3f0789f4 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,152 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133111 # Number of seconds simulated -sim_ticks 5133110815000 # Number of ticks simulated -final_tick 5133110815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.139557 # Number of seconds simulated +sim_ticks 5139557121500 # Number of ticks simulated +final_tick 5139557121500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 272926 # Simulator instruction rate (inst/s) -host_op_rate 542191 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5733082021 # Simulator tick rate (ticks/s) -host_mem_usage 964520 # Number of bytes of host memory used -host_seconds 895.35 # Real time elapsed on the host -sim_insts 244363664 # Number of instructions simulated -sim_ops 485450482 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2484864 # Number of bytes read from this memory +host_inst_rate 183644 # Simulator instruction rate (inst/s) +host_op_rate 364835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3871369364 # Simulator tick rate (ticks/s) +host_mem_usage 967408 # Number of bytes of host memory used +host_seconds 1327.58 # Real time elapsed on the host +sim_insts 243802016 # Number of instructions simulated +sim_ops 484348047 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2455296 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 399872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5730880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 105152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1659200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 489280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3010880 # Number of bytes read from this memory -system.physmem.bytes_read::total 13881664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 399872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 105152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 489280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 994304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9191104 # Number of bytes written to this memory -system.physmem.bytes_written::total 9191104 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38826 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 466944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5828928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 127616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1842944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 356032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2734144 # Number of bytes read from this memory +system.physmem.bytes_read::total 13813760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 466944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 127616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 356032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 950592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9154048 # Number of bytes written to this memory +system.physmem.bytes_written::total 9154048 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6248 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 89545 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 25925 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 7645 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 47045 # Number of read requests responded to by this memory -system.physmem.num_reads::total 216901 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143611 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143611 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 484085 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7296 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 91077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 28796 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 24 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 42721 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215840 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143032 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143032 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 477725 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 77901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1116454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 20485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 323235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 95318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 586560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2704337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 77901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 20485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 95318 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 193704 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1790552 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1790552 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1790552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 484085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 90853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1134130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 24830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 358580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 69273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 531980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2687734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 90853 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 24830 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 69273 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 184956 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1781097 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1781097 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1781097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 477725 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 77901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1116454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 20485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 323235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 95318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 586560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4494890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 101193 # Total number of read requests seen -system.physmem.writeReqs 78846 # Total number of write requests seen -system.physmem.cpureqs 181047 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 6476352 # Total number of bytes read from memory -system.physmem.bytesWritten 5046144 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6476352 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5046144 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 41 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1005 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6749 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6143 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6157 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7514 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6089 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 5671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 5777 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7080 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6052 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 5601 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 5675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7038 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5939 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 5837 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6375 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7455 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5123 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4689 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4672 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6199 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4650 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 90853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1134130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 24830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 358580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 69273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 531980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4468830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 99105 # Total number of read requests seen +system.physmem.writeReqs 78746 # Total number of write requests seen +system.physmem.cpureqs 178569 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 6342720 # Total number of bytes read from memory +system.physmem.bytesWritten 5039744 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 6342720 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5039744 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 712 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 5671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 5539 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 5876 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 5654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 5883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7012 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6334 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6064 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 5868 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 5762 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 5656 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7374 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4754 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5859 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4494 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 4387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4512 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5830 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4686 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4421 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4349 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4491 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4380 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4808 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6018 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4605 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5921 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5001 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4809 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4668 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5984 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4422 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4352 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4757 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6137 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry -system.physmem.totGap 5132091305000 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry +system.physmem.totGap 5135869541000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 101193 # Categorize read packet sizes +system.physmem.readPktSize::6 99105 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 78846 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 77214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 78746 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 75637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -156,304 +156,304 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3426 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 3424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.totQLat 2336250250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4424855250 # Sum of mem lat for all requests -system.physmem.totBusLat 505760000 # Total cycles spent in databus access -system.physmem.totBankLat 1582845000 # Total cycles spent in bank access -system.physmem.avgQLat 23096.43 # Average queueing delay per request -system.physmem.avgBankLat 15648.18 # Average bank access latency per request +system.physmem.wrQLenPdf::11 3421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.totQLat 2229520000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4250910000 # Sum of mem lat for all requests +system.physmem.totBusLat 495470000 # Total cycles spent in databus access +system.physmem.totBankLat 1525920000 # Total cycles spent in bank access +system.physmem.avgQLat 22499.04 # Average queueing delay per request +system.physmem.avgBankLat 15398.71 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43744.61 # Average memory access latency -system.physmem.avgRdBW 1.26 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 42897.75 # Average memory access latency +system.physmem.avgRdBW 1.23 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1.26 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1.23 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.98 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.10 # Average write queue length over time -system.physmem.readRowHits 84789 # Number of row buffer hits during reads -system.physmem.writeRowHits 54894 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.62 # Row buffer hit rate for writes -system.physmem.avgGap 28505442.18 # Average gap between requests -system.l2c.replacements 105754 # number of replacements -system.l2c.tagsinuse 64827.685609 # Cycle average of tags in use -system.l2c.total_refs 3731730 # Total number of references to valid blocks. -system.l2c.sampled_refs 169931 # Sample count of references to valid blocks. -system.l2c.avg_refs 21.960266 # Average number of references to valid blocks. +system.physmem.readRowHits 83478 # Number of row buffer hits during reads +system.physmem.writeRowHits 56534 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes +system.physmem.avgGap 28877372.30 # Average gap between requests +system.l2c.replacements 104936 # number of replacements +system.l2c.tagsinuse 64827.217537 # Cycle average of tags in use +system.l2c.total_refs 3630977 # Total number of references to valid blocks. +system.l2c.sampled_refs 168979 # Sample count of references to valid blocks. +system.l2c.avg_refs 21.487741 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50562.021644 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.124352 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 1105.122085 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4366.997770 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 211.458182 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 1301.465927 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 3.202289 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1974.838993 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 5302.454365 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.771515 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 50639.454481 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.125451 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 1092.997242 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4517.674660 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 223.356063 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 1300.523613 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 6.306120 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1891.819622 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 5154.960284 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.772697 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.016863 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.066635 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003227 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.019859 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000049 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.030134 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.080909 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989192 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 19783 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10976 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 335265 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 516181 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3330 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1120 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 152740 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 231467 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 92579 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13716 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 391764 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 554488 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2323409 # number of ReadReq hits +system.l2c.occ_percent::cpu0.inst 0.016678 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.068934 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.003408 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.019844 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.dtb.walker 0.000096 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.028867 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.078658 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989185 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 20688 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11397 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 368018 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 524840 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3790 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1830 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 151783 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 229669 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 45217 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 8673 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 312711 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 544544 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2223160 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1547018 # number of Writeback hits -system.l2c.Writeback_hits::total 1547018 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 46 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 75 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 254 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 67056 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 49870 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 55865 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172791 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 19783 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10978 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 335265 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 583237 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3330 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1120 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 152740 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 281337 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 92579 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 13716 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 391764 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 610353 # number of demand (read+write) hits -system.l2c.demand_hits::total 2496202 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 19783 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10978 # number of overall hits -system.l2c.overall_hits::cpu0.inst 335265 # number of overall hits -system.l2c.overall_hits::cpu0.data 583237 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 3330 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1120 # number of overall hits -system.l2c.overall_hits::cpu1.inst 152740 # number of overall hits -system.l2c.overall_hits::cpu1.data 281337 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 92579 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 13716 # number of overall hits -system.l2c.overall_hits::cpu2.inst 391764 # number of overall hits -system.l2c.overall_hits::cpu2.data 610353 # number of overall hits -system.l2c.overall_hits::total 2496202 # number of overall hits +system.l2c.Writeback_hits::writebacks 1544951 # number of Writeback hits +system.l2c.Writeback_hits::total 1544951 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 152 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 67 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 260 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 71407 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 43953 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 57565 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172925 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 20688 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 11399 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 368018 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 596247 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 3790 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1830 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 151783 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 273622 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 45217 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 8673 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 312711 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 602109 # number of demand (read+write) hits +system.l2c.demand_hits::total 2396087 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 20688 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 11399 # number of overall hits +system.l2c.overall_hits::cpu0.inst 368018 # number of overall hits +system.l2c.overall_hits::cpu0.data 596247 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 3790 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1830 # number of overall hits +system.l2c.overall_hits::cpu1.inst 151783 # number of overall hits +system.l2c.overall_hits::cpu1.data 273622 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 45217 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 8673 # number of overall hits +system.l2c.overall_hits::cpu2.inst 312711 # number of overall hits +system.l2c.overall_hits::cpu2.data 602109 # number of overall hits +system.l2c.overall_hits::total 2396087 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6248 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 12943 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1643 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4995 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 19 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 7645 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 15366 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48864 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 572 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 316 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 468 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1356 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76924 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 21191 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 32048 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130163 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 7296 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 14431 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1994 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4052 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 24 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 5567 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 14790 # number of ReadReq misses +system.l2c.ReadReq_misses::total 48159 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 746 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 231 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 361 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1338 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 77254 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 24966 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 28044 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130264 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6248 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 89867 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1643 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 26186 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 19 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 7645 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 47414 # number of demand (read+write) misses -system.l2c.demand_misses::total 179027 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7296 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 91685 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1994 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 29018 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 24 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 5567 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 42834 # number of demand (read+write) misses +system.l2c.demand_misses::total 178423 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6248 # number of overall misses -system.l2c.overall_misses::cpu0.data 89867 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1643 # number of overall misses -system.l2c.overall_misses::cpu1.data 26186 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 19 # number of overall misses -system.l2c.overall_misses::cpu2.inst 7645 # number of overall misses -system.l2c.overall_misses::cpu2.data 47414 # number of overall misses -system.l2c.overall_misses::total 179027 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 103398500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 296551000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 1601000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 553329000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1041727494 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1996606994 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 3261500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 5737499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 8998999 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1096336500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1799486495 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2895822995 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 103398500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1392887500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 1601000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 553329000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 2841213989 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 4892429989 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 103398500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1392887500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 1601000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 553329000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 2841213989 # number of overall miss cycles -system.l2c.overall_miss_latency::total 4892429989 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 19783 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10981 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 341513 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 529124 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 3330 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1120 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 154383 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 236462 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 92598 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 13716 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 399409 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 569854 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2372273 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 7296 # number of overall misses +system.l2c.overall_misses::cpu0.data 91685 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1994 # number of overall misses +system.l2c.overall_misses::cpu1.data 29018 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 24 # number of overall misses +system.l2c.overall_misses::cpu2.inst 5567 # number of overall misses +system.l2c.overall_misses::cpu2.data 42834 # number of overall misses +system.l2c.overall_misses::total 178423 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 122911000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 250826000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 1797000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 390878500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 976895991 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1743308491 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1987000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 4443500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 6430500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1303821500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1552905500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2856727000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 122911000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1554647500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 1797000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 390878500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 2529801491 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 4600035491 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 122911000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1554647500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 1797000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 390878500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 2529801491 # number of overall miss cycles +system.l2c.overall_miss_latency::total 4600035491 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 20688 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 11402 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 375314 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 539271 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 3790 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1830 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 153777 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 233721 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 45241 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 8673 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 318278 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 559334 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2271319 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1547018 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1547018 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 705 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 362 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 543 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1610 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 143980 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 71061 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 87913 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302954 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 19783 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10983 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 341513 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 673104 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 3330 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1120 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 154383 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 307523 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 92598 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 13716 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 399409 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 657767 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2675229 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 19783 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10983 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 341513 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 673104 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 3330 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1120 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 154383 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 307523 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 92598 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 13716 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 399409 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 657767 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2675229 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018295 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.024461 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010642 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.021124 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000205 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.019141 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.026965 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020598 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.811348 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.872928 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.861878 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.842236 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.534269 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.298209 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.364542 # miss rate for ReadExReq accesses +system.l2c.Writeback_accesses::writebacks 1544951 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1544951 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 898 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 272 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 428 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1598 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 148661 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 68919 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 85609 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 303189 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 20688 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 11404 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 375314 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 687932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 3790 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1830 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 153777 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 302640 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 45241 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 8673 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 318278 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 644943 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2574510 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 20688 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 11404 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 375314 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 687932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 3790 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1830 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 153777 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 302640 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 45241 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 8673 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 318278 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 644943 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2574510 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000439 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.019440 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.026760 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.012967 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017337 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000530 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.017491 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.026442 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.021203 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.830735 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.849265 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.843458 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.837297 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.519666 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.362251 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.327582 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.429646 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000455 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018295 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.133511 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010642 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.085151 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000205 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.019141 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.072083 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.066920 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000455 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018295 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.133511 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010642 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.085151 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000205 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.019141 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.072083 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.066920 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 62932.744979 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 59369.569570 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 84263.157895 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 72377.894048 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 67794.318235 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 40860.490218 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10321.202532 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12259.613248 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6636.429941 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 51735.949224 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 56149.728376 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 22247.666349 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 62932.744979 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 53192.068281 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 84263.157895 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 72377.894048 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 59923.524465 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 27327.889028 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 62932.744979 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 53192.068281 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 84263.157895 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 72377.894048 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 59923.524465 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 27327.889028 # average overall miss latency +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000438 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019440 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.133276 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.012967 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.095883 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000530 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.017491 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.066415 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.069304 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000438 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019440 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.133276 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.012967 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.095883 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000530 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.017491 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.066415 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.069304 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 61640.421264 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 61901.776900 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 74875 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70213.490210 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 66051.115010 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 36199.017650 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8601.731602 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12308.864266 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4806.053812 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52223.884483 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 55373.894594 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 21930.287723 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 61640.421264 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 53575.280860 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 74875 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 70213.490210 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 59060.594178 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 25781.628439 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 61640.421264 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 53575.280860 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 74875 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 70213.490210 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 59060.594178 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 25781.628439 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,119 +462,119 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96944 # number of writebacks -system.l2c.writebacks::total 96944 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.inst 1643 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4995 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 19 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 7645 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 15365 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 29667 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 316 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 468 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 784 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 21191 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 32048 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 53239 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1643 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 26186 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 19 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 7645 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 47413 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 82906 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1643 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 26186 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 19 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 7645 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 47413 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 82906 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 82735143 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 234275272 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1365263 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 458273787 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 850361157 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1627010622 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3210315 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 4800964 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 8011279 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 829338934 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1395043627 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2224382561 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 82735143 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1063614206 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1365263 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 458273787 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2245404784 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 3851393183 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 82735143 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1063614206 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1365263 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 458273787 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2245404784 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 3851393183 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28696022500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30542112500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 59238135000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 349705500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 850322500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1200028000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 29045728000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31392435000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 60438163000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010642 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021124 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000205 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.019141 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.026963 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.012506 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.872928 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.861878 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.486957 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.298209 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.364542 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.175733 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010642 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.085151 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000205 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.019141 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.072082 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.030990 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010642 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.085151 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000205 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.019141 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.072082 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.030990 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 50356.143031 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46901.956356 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 71855.947368 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59944.249444 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 55344.038855 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 54842.438467 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10159.224684 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10258.470085 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10218.468112 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 39136.375537 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43529.818616 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41781.073292 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50356.143031 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40617.666157 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 71855.947368 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59944.249444 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 47358.420349 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 46454.939124 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50356.143031 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40617.666157 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 71855.947368 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59944.249444 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 47358.420349 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 46454.939124 # average overall mshr miss latency +system.l2c.writebacks::writebacks 96365 # number of writebacks +system.l2c.writebacks::total 96365 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.inst 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 4 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.inst 1994 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4052 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 24 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 5563 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 14790 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 26423 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 231 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 361 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 592 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 24966 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 28044 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 53010 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1994 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 29018 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 24 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5563 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 42834 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 79433 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1994 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 29018 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 24 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5563 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 42834 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 79433 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 97847743 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 200215627 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1495274 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 321284586 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 792603807 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1413447037 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2410729 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3666859 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 6077588 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 988776449 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1199056726 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2187833175 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 97847743 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1188992076 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1495274 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 321284586 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1991660533 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 3601280212 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 97847743 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1188992076 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1495274 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 321284586 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1991660533 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 3601280212 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28659296500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30447811500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59107108000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 345721500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 690071500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1035793000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 29005018000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31137883000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60142901000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012967 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017337 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000530 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017478 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.026442 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.011633 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.849265 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.843458 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.370463 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.362251 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.327582 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.174841 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012967 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.095883 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017478 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.066415 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.030854 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012967 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.095883 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.066415 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.030854 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 49071.084754 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49411.556515 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57753.835341 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 53590.521095 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53493.056693 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10436.056277 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10157.504155 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10266.195946 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 39604.920652 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 42756.266082 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41272.084041 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 49071.084754 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40974.294438 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57753.835341 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46497.187585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 45337.330983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 49071.084754 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40974.294438 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57753.835341 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46497.187585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 45337.330983 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -585,39 +585,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47574 # number of replacements -system.iocache.tagsinuse 0.080510 # Cycle average of tags in use +system.iocache.replacements 47571 # number of replacements +system.iocache.tagsinuse 0.100524 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47587 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4999662298059 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.080510 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.005032 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.005032 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.warmup_cycle 4999700789059 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.100524 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006283 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006283 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses +system.iocache.ReadReq_misses::total 906 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses -system.iocache.demand_misses::total 47629 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses -system.iocache.overall_misses::total 47629 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129741871 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 129741871 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 4861732608 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4861732608 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 4991474479 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4991474479 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 4991474479 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4991474479 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses +system.iocache.demand_misses::total 47626 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses +system.iocache.overall_misses::total 47626 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 21701996 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21701996 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5260229904 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5260229904 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 5281931900 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5281931900 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 5281931900 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5281931900 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -626,60 +626,60 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142730.331133 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 142730.331133 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 104061.057534 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 104061.057534 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 104799.061055 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 104799.061055 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 104799.061055 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 104799.061055 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68462 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 23953.637969 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 23953.637969 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 112590.537329 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 112590.537329 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 110904.377861 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 110904.377861 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 110904.377861 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 110904.377861 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 67344 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6315 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6552 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.841172 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.278388 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 764 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 764 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 22592 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 22592 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 23356 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 23356 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 23356 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 23356 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89992399 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 89992399 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3686306893 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3686306893 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3776299292 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3776299292 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3776299292 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3776299292 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.840484 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.840484 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.483562 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.483562 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.490374 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.490374 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.490374 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.490374 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117791.098168 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117791.098168 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163168.683295 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 163168.683295 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161684.333448 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 161684.333448 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161684.333448 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 161684.333448 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 169 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24864 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 24864 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 25033 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 25033 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 25033 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 25033 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 12912498 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12912498 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3966572850 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3966572850 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3979485348 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3979485348 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3979485348 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3979485348 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.186534 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.186534 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.532192 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.532192 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.525616 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.525616 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.525616 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.525616 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 76405.313609 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76405.313609 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 159530.761342 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 159530.761342 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 158969.574082 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 158969.574082 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -689,336 +689,336 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 1742412594 # number of cpu cycles simulated +system.cpu0.numCycles 1838156995 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72300698 # Number of instructions committed -system.cpu0.committedOps 146721419 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 135119362 # Number of integer alu accesses +system.cpu0.committedInsts 73261263 # Number of instructions committed +system.cpu0.committedOps 148566469 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 136919559 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14129272 # number of instructions that are conditional controls -system.cpu0.num_int_insts 135119362 # number of integer instructions +system.cpu0.num_func_calls 1069041 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14289344 # number of instructions that are conditional controls +system.cpu0.num_int_insts 136919559 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 332380651 # number of times the integer registers were read -system.cpu0.num_int_register_writes 171799243 # number of times the integer registers were written +system.cpu0.num_int_register_reads 336929611 # number of times the integer registers were read +system.cpu0.num_int_register_writes 173945922 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 14355035 # number of memory refs -system.cpu0.num_load_insts 10404244 # Number of load instructions -system.cpu0.num_store_insts 3950791 # Number of store instructions -system.cpu0.num_idle_cycles 1032160899328.073853 # Number of idle cycles -system.cpu0.num_busy_cycles -1030418486734.073853 # Number of busy cycles -system.cpu0.not_idle_fraction -591.374563 # Percentage of non-idle cycles -system.cpu0.idle_fraction 592.374563 # Percentage of idle cycles +system.cpu0.num_mem_refs 14717824 # number of memory refs +system.cpu0.num_load_insts 10660250 # Number of load instructions +system.cpu0.num_store_insts 4057574 # Number of store instructions +system.cpu0.num_idle_cycles 1090327710419.609375 # Number of idle cycles +system.cpu0.num_busy_cycles -1088489553424.609375 # Number of busy cycles +system.cpu0.not_idle_fraction -592.163540 # Percentage of non-idle cycles +system.cpu0.idle_fraction 593.163540 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.replacements 894848 # number of replacements -system.cpu0.icache.tagsinuse 510.913561 # Cycle average of tags in use -system.cpu0.icache.total_refs 128448966 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 895360 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 143.460693 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 147286851000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 366.522543 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 28.161806 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 116.229212 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.715864 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.055004 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.227010 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.997878 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 88078408 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 37386418 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2984140 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 128448966 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 88078408 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 37386418 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2984140 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 128448966 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 88078408 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 37386418 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2984140 # number of overall hits -system.cpu0.icache.overall_hits::total 128448966 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 341513 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 154383 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 422579 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 918475 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 341513 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 154383 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 422579 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 918475 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 341513 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 154383 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 422579 # number of overall misses -system.cpu0.icache.overall_misses::total 918475 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2101458500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6067832979 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8169291479 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2101458500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 6067832979 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8169291479 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2101458500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 6067832979 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8169291479 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 88419921 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 37540801 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3406719 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 129367441 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 88419921 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 37540801 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3406719 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 129367441 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 88419921 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 37540801 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3406719 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 129367441 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003862 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004112 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.124043 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.007100 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003862 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004112 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.124043 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.007100 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003862 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004112 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.124043 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.007100 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13611.981241 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14359.049974 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8894.408099 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13611.981241 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14359.049974 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8894.408099 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13611.981241 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14359.049974 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8894.408099 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 12687 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 590 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 356 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 35.637640 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 590 # average number of cycles each access was blocked +system.cpu0.icache.replacements 846873 # number of replacements +system.cpu0.icache.tagsinuse 510.809979 # Cycle average of tags in use +system.cpu0.icache.total_refs 129726169 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 847385 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 153.089999 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 147287067000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 322.415881 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 27.501112 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 160.892986 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.629719 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.053713 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.314244 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.997676 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 89310227 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 37866681 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2549261 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 129726169 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 89310227 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 37866681 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2549261 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 129726169 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 89310227 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 37866681 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2549261 # number of overall hits +system.cpu0.icache.overall_hits::total 129726169 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 375314 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 153777 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 335702 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 864793 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 375314 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 153777 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 335702 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 864793 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 375314 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 153777 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 335702 # number of overall misses +system.cpu0.icache.overall_misses::total 864793 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2109411000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4767990981 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6877401981 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2109411000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4767990981 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6877401981 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2109411000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4767990981 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6877401981 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 89685541 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 38020458 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2884963 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 130590962 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 89685541 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 38020458 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2884963 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 130590962 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 89685541 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 38020458 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2884963 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 130590962 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004185 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004045 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116363 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006622 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004185 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004045 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116363 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006622 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004185 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004045 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116363 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006622 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13717.337443 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14203.046097 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7952.656857 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13717.337443 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14203.046097 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7952.656857 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13717.337443 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14203.046097 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7952.656857 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6416 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 225 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.515556 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23101 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 23101 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 23101 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 23101 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 23101 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 23101 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 154383 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 399478 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 553861 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 154383 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 399478 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 553861 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 154383 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 399478 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 553861 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1792692500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5012362480 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6805054980 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1792692500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5012362480 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6805054980 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1792692500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5012362480 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6805054980 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004112 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.117262 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004281 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004112 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.117262 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004281 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004112 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.117262 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004281 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11611.981241 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12547.280401 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12286.575477 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11611.981241 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12547.280401 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12286.575477 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11611.981241 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12547.280401 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12286.575477 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 17396 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 17396 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 17396 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 17396 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 17396 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 17396 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 153777 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 318306 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 472083 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 153777 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 318306 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 472083 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 153777 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 318306 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 472083 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1801857000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3960171483 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5762028483 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1801857000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3960171483 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5762028483 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1801857000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3960171483 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5762028483 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004045 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110333 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003615 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004045 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110333 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.003615 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004045 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110333 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.003615 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11717.337443 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12441.397533 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12205.541151 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11717.337443 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12441.397533 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12205.541151 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11717.337443 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12441.397533 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12205.541151 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1637829 # number of replacements -system.cpu0.dcache.tagsinuse 511.999325 # Cycle average of tags in use -system.cpu0.dcache.total_refs 19719847 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1638341 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 12.036473 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 7550500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 486.525664 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 16.669360 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 8.804301 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.950245 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.032557 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.017196 # Average percentage of cache occupancy +system.cpu0.dcache.replacements 1634958 # number of replacements +system.cpu0.dcache.tagsinuse 511.999366 # Cycle average of tags in use +system.cpu0.dcache.total_refs 19655982 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1635470 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 12.018552 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 482.608033 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 17.353549 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 12.037784 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.942594 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.033894 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.023511 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5387330 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2122125 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4119415 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11628870 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3803545 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1464488 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2821209 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8089242 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9190875 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3586613 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6940624 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19718112 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9190875 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3586613 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6940624 # number of overall hits -system.cpu0.dcache.overall_hits::total 19718112 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 529124 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 236462 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 932462 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1698048 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 144685 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 71423 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 99870 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 315978 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 673809 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 307885 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1032332 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2014026 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 673809 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 307885 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1032332 # number of overall misses -system.cpu0.dcache.overall_misses::total 2014026 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3328476000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15456118000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 18784594000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1822382500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 2810623495 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4633005995 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5150858500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 18266741495 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 23417599995 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5150858500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 18266741495 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 23417599995 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5916454 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2358587 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 5051877 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13326918 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3948230 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1535911 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2921079 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8405220 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9864684 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3894498 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7972956 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21732138 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9864684 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3894498 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7972956 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21732138 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.089433 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.100256 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184577 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127415 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036646 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.046502 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.034189 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037593 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.068305 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.079056 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.129479 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092675 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068305 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.079056 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.129479 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092675 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14076.156000 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16575.600936 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11062.463487 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 25515.345197 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 28142.820617 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14662.432179 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 16729.813080 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17694.638445 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 11627.258037 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16729.813080 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17694.638445 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11627.258037 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 176638 # number of cycles access was blocked +system.cpu0.dcache.ReadReq_hits::cpu0.data 5624800 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2207994 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 3726568 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11559362 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3904284 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1548034 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2642598 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8094916 # number of WriteReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9529084 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3756028 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6369166 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19654278 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9529084 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3756028 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6369166 # number of overall hits +system.cpu0.dcache.overall_hits::total 19654278 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 539271 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 233721 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 917659 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1690651 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 149559 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 69191 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 97336 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 316086 # number of WriteReq misses +system.cpu0.dcache.demand_misses::cpu0.data 688830 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 302912 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1014995 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2006737 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 688830 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 302912 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1014995 # number of overall misses +system.cpu0.dcache.overall_misses::total 2006737 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3256389500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15046703000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 18303092500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1959155500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 2564161499 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4523316999 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 5215545000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 17610864499 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 22826409499 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 5215545000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 17610864499 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 22826409499 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6164071 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2441715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4644227 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13250013 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4053843 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1617225 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2739934 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8411002 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10217914 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4058940 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7384161 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21661015 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10217914 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4058940 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7384161 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21661015 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.087486 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.095720 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.197591 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127596 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036893 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.042784 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.035525 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037580 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.067414 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.074628 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.137456 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092643 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067414 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.074628 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137456 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092643 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13932.806637 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16396.834772 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10826.061973 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28315.178275 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26343.403253 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14310.399698 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17218.020415 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17350.690889 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 11374.888438 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17218.020415 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17350.690889 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11374.888438 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 180086 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 12002 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 11859 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.717380 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.185597 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1547018 # number of writebacks -system.cpu0.dcache.writebacks::total 1547018 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 362388 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 362388 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 11634 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 11634 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 374022 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 374022 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 374022 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 374022 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 236462 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 570074 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 806536 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 71423 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 88236 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 159659 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 307885 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 658310 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 966195 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 307885 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 658310 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 966195 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2855552000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8374924000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11230476000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1679536500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2505829996 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4185366496 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4535088500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10880753996 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15415842496 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4535088500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10880753996 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15415842496 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31206994500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33315270500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64522265000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372935500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 904884500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1277820000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31579930000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34220155000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65800085000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.100256 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.112844 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060519 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.046502 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018995 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.079056 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.082568 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.044459 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.079056 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.082568 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.044459 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12076.156000 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14690.941878 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13924.333198 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23515.345197 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 28399.179428 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26214.410061 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 14729.813080 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16528.313403 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15955.208313 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 14729.813080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16528.313403 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15955.208313 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1544951 # number of writebacks +system.cpu0.dcache.writebacks::total 1544951 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 358302 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 358302 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 11322 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 11322 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 369624 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 369624 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 369624 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 369624 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 233721 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 559357 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 793078 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 69191 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 86014 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 155205 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 302912 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 645371 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 948283 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 302912 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 645371 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 948283 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2788947500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8180959500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 10969907000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1820773500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2270883499 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4091656999 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4609721000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10451842999 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15061563999 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4609721000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10451842999 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15061563999 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31167993500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33212773000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64380766500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 368756500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 730986500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1099743000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31536750000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33943759500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65480509500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.095720 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.120441 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.059855 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042784 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031393 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018453 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.074628 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087399 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.043778 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.074628 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087399 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.043778 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11932.806637 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14625.649630 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13832.065698 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26315.178275 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26401.324191 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26362.920003 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15218.020415 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16195.092434 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15882.984298 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15218.020415 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16195.092434 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15882.984298 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1029,303 +1029,303 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2604004638 # number of cpu cycles simulated +system.cpu1.numCycles 2606004355 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34050358 # Number of instructions committed -system.cpu1.committedOps 66241025 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 61396531 # Number of integer alu accesses +system.cpu1.committedInsts 34463532 # Number of instructions committed +system.cpu1.committedOps 67005357 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 62150402 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6330827 # number of instructions that are conditional controls -system.cpu1.num_int_insts 61396531 # number of integer instructions +system.cpu1.num_func_calls 411236 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6382216 # number of instructions that are conditional controls +system.cpu1.num_int_insts 62150402 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 147773528 # number of times the integer registers were read -system.cpu1.num_int_register_writes 79124330 # number of times the integer registers were written +system.cpu1.num_int_register_reads 149729485 # number of times the integer registers were read +system.cpu1.num_int_register_writes 79937808 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 4089746 # number of memory refs -system.cpu1.num_load_insts 2551885 # Number of load instructions -system.cpu1.num_store_insts 1537861 # Number of store instructions -system.cpu1.num_idle_cycles 7651672288.559311 # Number of idle cycles -system.cpu1.num_busy_cycles -5047667650.559310 # Number of busy cycles -system.cpu1.not_idle_fraction -1.938425 # Percentage of non-idle cycles -system.cpu1.idle_fraction 2.938425 # Percentage of idle cycles +system.cpu1.num_mem_refs 4253944 # number of memory refs +system.cpu1.num_load_insts 2634755 # Number of load instructions +system.cpu1.num_store_insts 1619189 # Number of store instructions +system.cpu1.num_idle_cycles 7677367348.593150 # Number of idle cycles +system.cpu1.num_busy_cycles -5071362993.593150 # Number of busy cycles +system.cpu1.not_idle_fraction -1.946030 # Percentage of non-idle cycles +system.cpu1.idle_fraction 2.946030 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29453623 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29453623 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 415098 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 27524978 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 26775027 # Number of BTB hits +system.cpu2.branchPred.lookups 28657213 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28657213 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 282528 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26332341 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25809696 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.275380 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155984085 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 98.015197 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 509678 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 56598 # Number of incorrect RAS predictions. +system.cpu2.numCycles 152138342 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10604817 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 145070644 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29453623 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26775027 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 55443665 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1825085 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 101909 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 22639923 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 2951 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 5864 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 5243 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 1584 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3406726 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 188434 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3455 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 90201759 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.168652 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.414059 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8765036 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 141230370 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28657213 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26319374 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54195726 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1350224 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 59186 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 22546148 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 3184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6465 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 18223 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 777 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2884967 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 126552 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1685 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 86648155 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.214672 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.414816 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 34888289 38.68% 38.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 600988 0.67% 39.34% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 24050058 26.66% 66.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 353959 0.39% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 625644 0.69% 67.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 870018 0.96% 68.06% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 382969 0.42% 68.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 534158 0.59% 69.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27895676 30.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 32565830 37.58% 37.58% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 546380 0.63% 38.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23846422 27.52% 65.74% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 287955 0.33% 66.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 558507 0.64% 66.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 803239 0.93% 67.64% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 320738 0.37% 68.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 484990 0.56% 68.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27234094 31.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 90201759 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.188825 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.930035 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 12002495 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 21681187 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 45325562 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1251433 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1399062 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 284656362 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 4 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1399062 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 13027629 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13040843 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 3781171 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 45395781 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5015320 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 283355773 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 7223 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2405393 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 1942678 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 3127 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 338147018 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 617097261 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 617097023 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 238 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 325868282 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12278736 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 148774 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 149957 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11224608 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6517761 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3579821 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 461835 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 357597 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 281093420 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 441880 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278958104 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 66093 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8698902 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13192307 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 82110 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 90201759 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.092602 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.393390 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 86648155 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.188363 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.928302 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10203383 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 21434341 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 42926723 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1270829 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1056674 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 277800524 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 10 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1056674 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11171095 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 12732005 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 3756843 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 43068844 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5106557 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 276894625 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 6426 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2483944 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 1961652 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 2548 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 331033770 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 601753258 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 601753178 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 80 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 321557178 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 9476592 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 136008 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 137084 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11206153 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 5917951 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3223233 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 365517 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 302609 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275352384 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 397965 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273886109 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 53996 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 6700477 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10323870 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 50144 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 86648155 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.160899 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.377923 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 26012470 28.84% 28.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6039286 6.70% 35.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3951880 4.38% 39.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2755931 3.06% 42.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25450269 28.21% 71.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1402946 1.56% 72.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24246567 26.88% 99.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 287223 0.32% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 55187 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 23779115 27.44% 27.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5842995 6.74% 34.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3792974 4.38% 38.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2596888 3.00% 41.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25119641 28.99% 70.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1266341 1.46% 72.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23944050 27.63% 99.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 257275 0.30% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 48876 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 90201759 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 86648155 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 134556 34.98% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 34.98% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 196649 51.12% 86.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 53504 13.91% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 118795 33.06% 33.06% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 241 0.07% 33.13% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 86 0.02% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 188736 52.53% 85.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 51440 14.32% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 83173 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 268863326 96.38% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.41% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6715737 2.41% 98.82% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3295868 1.18% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 68063 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264478225 96.57% 96.59% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 51078 0.02% 96.61% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 47173 0.02% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6223177 2.27% 98.90% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3018393 1.10% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278958104 # Type of FU issued -system.cpu2.iq.rate 1.788375 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 384709 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001379 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 648620730 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 290237963 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 277347431 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 26 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 279259593 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 47 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 629589 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 273886109 # Type of FU issued +system.cpu2.iq.rate 1.800244 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 359298 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001312 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 634870698 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 282454128 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272600027 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 31 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 8 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 274177330 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 14 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 614321 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1208294 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 7639 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4324 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 653312 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 929558 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6267 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3704 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 478908 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656809 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10508 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656133 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10377 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1399062 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 8628497 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 800211 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 281535300 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 104725 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6517761 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3579821 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 245066 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 628910 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4050 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4324 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 245790 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 219209 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 464999 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 278243266 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6548770 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 714838 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1056674 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 8226180 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 803204 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275750349 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 63685 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 5917951 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3223233 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 220549 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 623968 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3956 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3704 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 161931 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 157888 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 319819 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273437676 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6124763 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 448433 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9760405 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28303676 # Number of branches executed -system.cpu2.iew.exec_stores 3211635 # Number of stores executed -system.cpu2.iew.exec_rate 1.783793 # Inst execution rate -system.cpu2.iew.wb_sent 278068144 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 277347457 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 216266417 # num instructions producing a value -system.cpu2.iew.wb_consumers 353604041 # num instructions consuming a value +system.cpu2.iew.exec_refs 9083662 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27821550 # Number of branches executed +system.cpu2.iew.exec_stores 2958899 # Number of stores executed +system.cpu2.iew.exec_rate 1.797296 # Inst execution rate +system.cpu2.iew.wb_sent 273301697 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272600035 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212879972 # num instructions producing a value +system.cpu2.iew.wb_consumers 348297595 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.778050 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611606 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.791790 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611201 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9045420 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 359770 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 415805 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 88802697 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.068466 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.866565 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 6973062 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 347821 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 284653 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 85591481 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.140222 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.867307 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 30564443 34.42% 34.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4416110 4.97% 39.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1290481 1.45% 40.84% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 25052940 28.21% 69.06% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 877654 0.99% 70.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 569019 0.64% 70.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 327531 0.37% 71.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23624903 26.60% 97.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2079616 2.34% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 28429929 33.22% 33.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4148762 4.85% 38.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1193631 1.39% 39.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24678313 28.83% 68.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 797871 0.93% 69.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 541346 0.63% 69.85% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 330295 0.39% 70.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23445398 27.39% 97.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2025936 2.37% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 88802697 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 138012608 # Number of instructions committed -system.cpu2.commit.committedOps 272488038 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 85591481 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 136077221 # Number of instructions committed +system.cpu2.commit.committedOps 268776221 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8235976 # Number of memory references committed -system.cpu2.commit.loads 5309467 # Number of loads committed -system.cpu2.commit.membars 167075 # Number of memory barriers committed -system.cpu2.commit.branches 27913254 # Number of branches committed +system.cpu2.commit.refs 7732718 # Number of memory references committed +system.cpu2.commit.loads 4988393 # Number of loads committed +system.cpu2.commit.membars 163760 # Number of memory barriers committed +system.cpu2.commit.branches 27507890 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 248812400 # Number of committed integer instructions. -system.cpu2.commit.function_calls 0 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2079616 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 245262632 # Number of committed integer instructions. +system.cpu2.commit.function_calls 414873 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2025936 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 368229083 # The number of ROB reads -system.cpu2.rob.rob_writes 564472103 # The number of ROB writes -system.cpu2.timesIdled 458685 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65782326 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4902194189 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 138012608 # Number of Instructions Simulated -system.cpu2.committedOps 272488038 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 138012608 # Number of Instructions Simulated -system.cpu2.cpi 1.130216 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.130216 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.884786 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.884786 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 511223313 # number of integer regfile reads -system.cpu2.int_regfile_writes 330894999 # number of integer regfile writes -system.cpu2.fp_regfile_reads 62522 # number of floating regfile reads -system.cpu2.fp_regfile_writes 62496 # number of floating regfile writes -system.cpu2.misc_regfile_reads 90285732 # number of misc regfile reads -system.cpu2.misc_regfile_writes 129561 # number of misc regfile writes +system.cpu2.rob.rob_reads 359289994 # The number of ROB reads +system.cpu2.rob.rob_writes 552558663 # The number of ROB writes +system.cpu2.timesIdled 454161 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65490187 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4914041775 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 136077221 # Number of Instructions Simulated +system.cpu2.committedOps 268776221 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 136077221 # Number of Instructions Simulated +system.cpu2.cpi 1.118029 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.118029 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.894431 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.894431 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 502349004 # number of integer regfile reads +system.cpu2.int_regfile_writes 325553024 # number of integer regfile writes +system.cpu2.fp_regfile_reads 62552 # number of floating regfile reads +system.cpu2.fp_regfile_writes 62544 # number of floating regfile writes +system.cpu2.misc_regfile_reads 88383748 # number of misc regfile reads +system.cpu2.misc_regfile_writes 121022 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |