diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:50:15 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:50:15 -0500 |
| commit | 29cd50e14e0709c28200bcbdbc08c1093ba300d7 (patch) | |
| tree | ce3db836e947d154cbd0e4d7e1959f7617a7cc0c /tests/long/fs | |
| parent | 7a0bf814b6eb2db57f37977a0cca6c442f957d68 (diff) | |
| download | gem5-29cd50e14e0709c28200bcbdbc08c1093ba300d7.tar.xz | |
arm, tests: Add 64-bit ARM regression tests
Diffstat (limited to 'tests/long/fs')
32 files changed, 35656 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini new file mode 100644 index 000000000..59744d039 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini @@ -0,0 +1,2431 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.physmem system.realview.vram system.realview.nvmem +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +branchPred=system.cpu0.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu +dtb=system.cpu0.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu0.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu0.tracer +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu0.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=6 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.dcache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=16 +cpu_side=system.cpu0.dcache_port +mem_side=system.cpu0.toL2Bus.slave[1] + +[system.cpu0.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[5] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[3] + +[system.cpu0.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu0.executeFuncUnits.funcUnits0 system.cpu0.executeFuncUnits.funcUnits1 system.cpu0.executeFuncUnits.funcUnits2 system.cpu0.executeFuncUnits.funcUnits3 system.cpu0.executeFuncUnits.funcUnits4 system.cpu0.executeFuncUnits.funcUnits5 system.cpu0.executeFuncUnits.funcUnits6 + +[system.cpu0.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu0.executeFuncUnits.funcUnits0.timings + +[system.cpu0.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu0.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu0.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu0.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu0.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu0.executeFuncUnits.funcUnits1.timings + +[system.cpu0.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu0.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu0.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu0.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu0.executeFuncUnits.funcUnits2.timings + +[system.cpu0.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu0.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu0.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu0.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu0.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu0.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu0.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu0.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu0.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu0.executeFuncUnits.funcUnits4.timings + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu0.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu0.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu0.executeFuncUnits.funcUnits5.timings + +[system.cpu0.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu0.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu0.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu0.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu0.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=1 +is_top_level=true +max_miss_count=0 +mshrs=2 +prefetch_on_access=false +prefetcher=Null +response_latency=1 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.icache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.cpu0.toL2Bus.slave[0] + +[system.cpu0.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=1 +sequential_access=false +size=32768 + +[system.cpu0.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu0.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[4] + +[system.cpu0.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[2] + +[system.cpu0.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu0.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu0.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu0.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu0.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu0.l2cache.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu1] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +branchPred=system.cpu1.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=1 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu +dtb=system.cpu1.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu1.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu1.tracer +workload= +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu1.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=6 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu1.dcache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=16 +cpu_side=system.cpu1.dcache_port +mem_side=system.cpu1.toL2Bus.slave[1] + +[system.cpu1.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[5] + +[system.cpu1.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[3] + +[system.cpu1.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu1.executeFuncUnits.funcUnits0 system.cpu1.executeFuncUnits.funcUnits1 system.cpu1.executeFuncUnits.funcUnits2 system.cpu1.executeFuncUnits.funcUnits3 system.cpu1.executeFuncUnits.funcUnits4 system.cpu1.executeFuncUnits.funcUnits5 system.cpu1.executeFuncUnits.funcUnits6 + +[system.cpu1.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu1.executeFuncUnits.funcUnits0.timings + +[system.cpu1.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu1.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu1.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu1.executeFuncUnits.funcUnits1.timings + +[system.cpu1.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu1.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu1.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu1.executeFuncUnits.funcUnits2.timings + +[system.cpu1.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu1.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu1.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu1.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu1.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu1.executeFuncUnits.funcUnits4.timings + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu1.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu1.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu1.executeFuncUnits.funcUnits5.timings + +[system.cpu1.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu1.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu1.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu1.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu1.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=1 +is_top_level=true +max_miss_count=0 +mshrs=2 +prefetch_on_access=false +prefetcher=Null +response_latency=1 +sequential_access=false +size=32768 +system=system +tags=system.cpu1.icache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.cpu1.toL2Bus.slave[0] + +[system.cpu1.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=1 +sequential_access=false +size=32768 + +[system.cpu1.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu1.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[4] + +[system.cpu1.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[2] + +[system.cpu1.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu1.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu1.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[1] + +[system.cpu1.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu1.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu1.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu1.l2cache.cpu_side +slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu1.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.l2c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.l2c.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr new file mode 100644 index 000000000..744db2c76 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr @@ -0,0 +1,11 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout new file mode 100644 index 000000000..b85d856c0 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout @@ -0,0 +1,17 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:35:48 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 + 0: system.cpu0.isa: ISA system set to: 0x5394b00 0x5394b00 + 0: system.cpu1.isa: ISA system set to: 0x5394b00 0x5394b00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80080000 +info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 47349475204500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt new file mode 100644 index 000000000..864e98054 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -0,0 +1,2653 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 47.349475 # Number of seconds simulated +sim_ticks 47349475204500 # Number of ticks simulated +final_tick 47349475204500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 170024 # Simulator instruction rate (inst/s) +host_op_rate 200007 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9521770968 # Simulator tick rate (ticks/s) +host_mem_usage 827688 # Number of bytes of host memory used +host_seconds 4972.76 # Real time elapsed on the host +sim_insts 845490438 # Number of instructions simulated +sim_ops 994586036 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.ide 457024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 242432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 409152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 13269720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 28432512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 254656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 419648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 10291040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 23441792 # Number of bytes read from this memory +system.physmem.bytes_read::total 77217976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3825664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 566400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4392064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 33722560 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.inst 56250828 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.inst 43534148 # Number of bytes written to this memory +system.physmem.bytes_written::total 140338128 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 7141 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 3788 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 6393 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 207361 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 444258 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3979 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 6557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 160812 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 366278 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1206567 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 526915 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.inst 881196 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.inst 680222 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2195061 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 9652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 5120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 8641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 280251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 600482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 5378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 8863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 217342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 495080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1630810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 80796 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 712206 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 144259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 1187993 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 919422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2963879 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 712206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 153911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 5120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 8641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 1468243 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 600482 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 5378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 8863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1136764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 495080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4594689 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1206567 # Number of read requests accepted +system.physmem.writeReqs 2195061 # Number of write requests accepted +system.physmem.readBursts 1206567 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2195061 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 76928704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 291584 # Total number of bytes read from write queue +system.physmem.bytesWritten 135133184 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 77217976 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 140338128 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 4556 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 83588 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 93227 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 68916 # Per bank write bursts +system.physmem.perBankRdBursts::1 78372 # Per bank write bursts +system.physmem.perBankRdBursts::2 66961 # Per bank write bursts +system.physmem.perBankRdBursts::3 74483 # Per bank write bursts +system.physmem.perBankRdBursts::4 67860 # Per bank write bursts +system.physmem.perBankRdBursts::5 84994 # Per bank write bursts +system.physmem.perBankRdBursts::6 78873 # Per bank write bursts +system.physmem.perBankRdBursts::7 74831 # Per bank write bursts +system.physmem.perBankRdBursts::8 70689 # Per bank write bursts +system.physmem.perBankRdBursts::9 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Per bank write bursts +system.physmem.perBankWrBursts::9 120303 # Per bank write bursts +system.physmem.perBankWrBursts::10 105255 # Per bank write bursts +system.physmem.perBankWrBursts::11 150368 # Per bank write bursts +system.physmem.perBankWrBursts::12 133266 # Per bank write bursts +system.physmem.perBankWrBursts::13 132701 # Per bank write bursts +system.physmem.perBankWrBursts::14 112511 # Per bank write bursts +system.physmem.perBankWrBursts::15 165684 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 47349473266500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 37 # Read request sizes (log2) +system.physmem.readPktSize::4 5 # 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incoming req see +system.physmem.wrQLenPdf::32 102758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 691339 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 306.739519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.472793 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.323128 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 329714 47.69% 47.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 128094 18.53% 66.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 46159 6.68% 72.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24419 3.53% 76.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20272 2.93% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13585 1.97% 81.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10457 1.51% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11430 1.65% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 107209 15.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 691339 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 99075 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.132152 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 222.564559 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 99072 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-30719 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 99075 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 99075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.311693 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.731664 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.258880 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 33791 34.11% 34.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 48957 49.41% 83.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 10331 10.43% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 2038 2.06% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1546 1.56% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 746 0.75% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 511 0.52% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 316 0.32% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 116 0.12% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 38 0.04% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 31 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 20 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 438 0.44% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 35 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 39 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 38 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 24 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 10 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 7 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 99075 # Writes before turning the bus around for reads +system.physmem.totQLat 32464480274 # Total ticks spent queuing +system.physmem.totMemAccLat 55002186524 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6010055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27008.47 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 45758.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.96 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.37 # Average write queue length when enqueuing +system.physmem.readRowHits 944165 # Number of row buffer hits during reads +system.physmem.writeRowHits 1677959 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.47 # Row buffer hit rate for writes +system.physmem.avgGap 13919650.61 # Average gap between requests +system.physmem.pageHitRate 79.13 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 45391806829500 # Time in different power states +system.physmem.memoryStateTime::REF 1581102900000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 376561525500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 2682083880 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2544438960 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1463438625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1388334750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 4643184000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 4732392600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 6990105600 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 6692129280 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3092637272400 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3092637272400 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1220178523320 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1215644323230 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 27339350706750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 27343328075250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 31667945314575 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 31666966966470 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.813072 # Core power per rank (mW) +system.physmem.averagePower::1 668.792410 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 1114990 # Transaction distribution +system.membus.trans_dist::ReadResp 1114990 # Transaction distribution +system.membus.trans_dist::WriteReq 37937 # Transaction distribution +system.membus.trans_dist::WriteResp 37937 # Transaction distribution +system.membus.trans_dist::Writeback 526915 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1665543 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1665543 # Transaction distribution +system.membus.trans_dist::UpgradeReq 343558 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 290459 # Transaction distribution +system.membus.trans_dist::UpgradeResp 93233 # Transaction distribution +system.membus.trans_dist::ReadExReq 145423 # Transaction distribution +system.membus.trans_dist::ReadExResp 131308 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122918 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 23584 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6789962 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6936516 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229526 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 229526 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7166042 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 47168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210268488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 210473028 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7287616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7287616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 217760644 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 556693 # Total snoops (count) +system.membus.snoop_fanout::samples 3996553 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 3996553 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 3996553 # Request fanout histogram +system.membus.reqLayer0.occupancy 106711482 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 35984 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 20060995 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 21791270978 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 13392760110 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 187374753 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.l2c.tags.replacements 893379 # number of replacements +system.l2c.tags.tagsinuse 64139.353797 # Cycle average of tags in use +system.l2c.tags.total_refs 6866398 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 953433 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 7.201762 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10411.534254 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 170.665758 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 236.653363 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5522.014615 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 25703.497535 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 145.004713 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 188.005532 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6322.307070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 15439.670958 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.158867 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002604 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003611 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.084259 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.392204 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002213 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.002869 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.096471 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.235591 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.978689 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 36012 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 260 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 23782 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 41 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 716 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1957 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 33290 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 51 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 190 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1450 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3907 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 18298 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.549500 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.362885 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 80317062 # Number of tag accesses +system.l2c.tags.data_accesses 80317062 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 7070 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4466 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 557041 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 2033838 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 7318 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4580 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 521752 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1881001 # number of ReadReq hits +system.l2c.ReadReq_hits::total 5017066 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1844732 # number of Writeback hits +system.l2c.Writeback_hits::total 1844732 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 30097 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 27244 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 57341 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 7329 # number of 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95291873740 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 428022244 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 10085462949 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 430600242 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 10431954111 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 95291873740 # number of overall MSHR miss cycles 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66717.054807 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 85735.610037 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10179.371655 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10164.217219 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10172.009239 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10202.078498 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10213.915648 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10207.679266 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 60979.791401 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60315.430582 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60657.412408 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 6929805 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 6922247 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 37937 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 37937 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1844732 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1558815 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 396880 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 304912 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 701792 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 286652 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 286652 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10302950 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9169444 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 19472394 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 332778181 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290120831 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 622899012 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1503135 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 11338555 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.010201 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.100485 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 11222888 98.98% 98.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115667 1.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 11338555 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 19325316227 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 6157500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 17505808152 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 16090621161 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40386 # Transaction distribution +system.iobus.trans_dist::ReadResp 40386 # Transaction distribution +system.iobus.trans_dist::WriteReq 136543 # Transaction distribution +system.iobus.trans_dist::WriteResp 136730 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 187 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48036 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354232 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7497086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36503000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 982100345 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 92919000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179226247 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 130284886 # Number of BP lookups +system.cpu0.branchPred.condPredicted 91971902 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5996877 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 97983342 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 71203631 # Number of BTB hits +system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.branchPred.BTBHitPct 72.669119 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15456951 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1030979 # Number of incorrect RAS predictions. +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 84560824 # DTB read hits +system.cpu0.dtb.read_misses 213472 # DTB read misses +system.cpu0.dtb.write_hits 73762718 # DTB write hits +system.cpu0.dtb.write_misses 44801 # DTB write misses +system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 35801 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1794 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7921 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 10648 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 84774296 # DTB read accesses +system.cpu0.dtb.write_accesses 73807519 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 158323542 # DTB hits +system.cpu0.dtb.misses 258273 # DTB misses +system.cpu0.dtb.accesses 158581815 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 233888906 # ITB inst hits +system.cpu0.itb.inst_misses 61464 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25786 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 208811 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 233950370 # ITB inst accesses +system.cpu0.itb.hits 233888906 # DTB hits +system.cpu0.itb.misses 61464 # DTB misses +system.cpu0.itb.accesses 233950370 # DTB accesses +system.cpu0.numCycles 883850249 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 434327088 # Number of instructions committed +system.cpu0.committedOps 509859279 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 43671037 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93815840018 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.034988 # CPI: cycles per instruction +system.cpu0.ipc 0.491403 # IPC: instructions per cycle +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 5406 # number of quiesce instructions executed +system.cpu0.tickCycles 675499590 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 208350659 # Total number of cycles that the object has spent stopped +system.cpu0.icache.tags.replacements 9024677 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.937426 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 224649292 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9025189 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.891367 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 16724996500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937426 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999878 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999878 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 476374153 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 476374153 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 224649292 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 224649292 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 224649292 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 224649292 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 224649292 # number of overall hits +system.cpu0.icache.overall_hits::total 224649292 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9025190 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9025190 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9025190 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9025190 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9025190 # number of overall misses +system.cpu0.icache.overall_misses::total 9025190 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 76329373412 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 76329373412 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 76329373412 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 76329373412 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 76329373412 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 76329373412 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 233674482 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 233674482 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 233674482 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 233674482 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 233674482 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 233674482 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038623 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.038623 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038623 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.038623 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038623 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.038623 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8457.370251 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8457.370251 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8457.370251 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8457.370251 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9025190 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9025190 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9025190 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9025190 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9025190 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9025190 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62781832574 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 62781832574 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62781832574 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 62781832574 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62781832574 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 62781832574 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713380500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713380500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6956.289294 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.trans_dist::ReadReq 16744363 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 13538941 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 16377 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 16377 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 2993146 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 4286145 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 878594 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 389729 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 340122 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 446153 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1234377 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1099479 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18154960 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15139641 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 334891 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1016427 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 34645919 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 580958656 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 555417413 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1211560 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3676024 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1141263653 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 9180766 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 27586114 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.321691 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.467125 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 18711910 67.83% 67.83% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 8874204 32.17% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 27586114 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 13279117937 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 196246989 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 13633302169 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 7744080967 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 184135419 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 557460915 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 80006652 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1538976 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75387543 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49644 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2517 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3027964 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6795468 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.tags.replacements 3295318 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16239.521092 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15183735 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 3311433 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.585246 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 14515776000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 5108.942549 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.019654 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 70.169979 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2735.324727 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8261.064181 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.311825 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003907 # Average percentage of cache occupancy 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blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 3014 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 30 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 447 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1426 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2059 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.654968 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.323547 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 302494843 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 302494843 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 445653 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140462 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 11717958 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 12304073 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 2993146 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 2993146 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 70651 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 70651 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 35155 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 35155 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 863705 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 863705 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 445653 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140462 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 12581663 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 13167778 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 445653 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140462 # number of overall hits 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SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 228005 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 228005 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13850 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10983 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 1141047 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1165880 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13850 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10983 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 1141047 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1165880 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 571410377 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 698481694 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 26359609041 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 27629501112 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 2365914343 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2365914343 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 3101977603 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3101977603 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 2176500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2176500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 9967705721 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 9967705721 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 571410377 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 698481694 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 36327314762 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 37597206833 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 571410377 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 698481694 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 36327314762 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 37597206833 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 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ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 473721015 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 620302796 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 26927532254 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 28021556065 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 473721015 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 620302796 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 26927532254 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 79252881469 # number of overall MSHR miss cycles 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miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.066552 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065356 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.624622 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.624622 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813545 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813545 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 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0.077418 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.287096 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22691.090870 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23304.110445 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 26174.068722 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 26174.068722 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17058.656283 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17058.656283 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13812.867324 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13812.867324 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 590166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590166.666667 # average SCUpgradeFailReq mshr miss latency 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mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 26174.068722 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 26068.266906 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 5337320 # number of replacements +system.cpu0.dcache.tags.tagsinuse 473.198574 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 150291577 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5337832 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.155921 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 473.198574 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.924216 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.924216 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 319289852 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 319289852 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 77767484 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77767484 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 68524145 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 68524145 # number of WriteReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 878594 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 878594 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1744720 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1744720 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1671495 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1671495 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 146291629 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 146291629 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 146291629 # number of overall hits +system.cpu0.dcache.overall_hits::total 146291629 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 3855307 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3855307 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 2180509 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2180509 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 116717 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 116717 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 188600 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 188600 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 6035816 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6035816 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 6035816 # number of overall misses +system.cpu0.dcache.overall_misses::total 6035816 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 52949262121 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 52949262121 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36682258766 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36682258766 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1582680255 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 1582680255 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3978646923 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3978646923 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 2553000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2553000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 89631520887 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 89631520887 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 89631520887 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 89631520887 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 81622791 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 81622791 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 70704654 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 70704654 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 878594 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 878594 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1861437 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1861437 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1860095 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1860095 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 152327445 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 152327445 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 152327445 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 152327445 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.047233 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.047233 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030840 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030840 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.062703 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062703 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.101393 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101393 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.039624 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.039624 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.039624 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.039624 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 13734.123410 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13734.123410 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 16822.796313 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 16822.796313 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13559.980594 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13559.980594 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21095.688881 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21095.688881 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14849.942557 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14849.942557 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 878594 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 2993146 # number of writebacks +system.cpu0.dcache.writebacks::total 2993146 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 365860 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 365860 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 900170 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 900170 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 65 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 53 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1266030 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1266030 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1266030 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1266030 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3489447 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3489447 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1279618 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1279618 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 116652 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116652 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 188547 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 188547 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4769065 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4769065 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4769065 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4769065 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 40912958493 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40912958493 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 19695838269 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19695838269 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 39725259601 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 39725259601 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1347811737 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1347811737 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3591126546 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3591126546 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2234500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2234500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 60608796762 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 60608796762 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 60608796762 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 60608796762 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2590105703 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2590105703 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2521930197 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2521930197 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 5112035900 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5112035900 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.042751 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.042751 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018098 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018098 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.062668 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062668 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.101364 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101364 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.031308 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031308 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11724.768564 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11724.768564 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 15391.967188 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15391.967188 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11554.124550 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11554.124550 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19046.320260 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19046.320260 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.branchPred.lookups 124419206 # Number of BP lookups +system.cpu1.branchPred.condPredicted 87805046 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6051921 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 92935126 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 66733716 # Number of BTB hits +system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.branchPred.BTBHitPct 71.806774 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 14888837 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1052333 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 80858392 # DTB read hits +system.cpu1.dtb.read_misses 227532 # DTB read misses +system.cpu1.dtb.write_hits 71539111 # DTB write hits +system.cpu1.dtb.write_misses 46368 # DTB write misses +system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35324 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1220 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8196 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 10514 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 81085924 # DTB read accesses +system.cpu1.dtb.write_accesses 71585479 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 152397503 # DTB hits +system.cpu1.dtb.misses 273900 # DTB misses +system.cpu1.dtb.accesses 152671403 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 221287255 # ITB inst hits +system.cpu1.itb.inst_misses 68040 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25097 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 202601 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 221355295 # ITB inst accesses +system.cpu1.itb.hits 221287255 # DTB hits +system.cpu1.itb.misses 68040 # DTB misses +system.cpu1.itb.accesses 221355295 # DTB accesses +system.cpu1.numCycles 841372178 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 411163350 # Number of instructions committed +system.cpu1.committedOps 484726757 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 42974941 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4643 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93858235376 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.046321 # CPI: cycles per instruction +system.cpu1.ipc 0.488682 # IPC: instructions per cycle +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 13250 # number of quiesce instructions executed +system.cpu1.tickCycles 646022417 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 195349761 # Total number of cycles that the object has spent stopped +system.cpu1.icache.tags.replacements 9199343 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.111645 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 211878543 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9199855 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 23.030639 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8364993861000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.111645 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990452 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990452 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 451356678 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 451356678 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 211878543 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 211878543 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 211878543 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 211878543 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 211878543 # number of overall hits +system.cpu1.icache.overall_hits::total 211878543 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 9199864 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 9199864 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 9199864 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 9199864 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 9199864 # number of overall misses +system.cpu1.icache.overall_misses::total 9199864 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 77780449816 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 77780449816 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 77780449816 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 77780449816 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 77780449816 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 77780449816 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 221078407 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 221078407 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 221078407 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 221078407 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 221078407 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 221078407 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.041614 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.041614 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.041614 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.041614 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.041614 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.041614 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8454.521699 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8454.521699 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8454.521699 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8454.521699 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8454.521699 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8454.521699 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9199864 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 9199864 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 9199864 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 9199864 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 9199864 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 9199864 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63970402202 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 63970402202 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63970402202 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 63970402202 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63970402202 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 63970402202 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8551999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8551999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8551999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8551999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.041614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.041614 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.041614 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6953.407377 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.trans_dist::ReadReq 16974832 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13523495 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 21560 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 21560 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 2756922 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 3912463 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 680221 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 382477 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337171 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 432582 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1151878 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1012928 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18399906 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13962178 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 374507 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1077414 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 33814005 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 588796992 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 509690879 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1369000 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3931224 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1103788095 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 9217690 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 27159033 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.328913 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.469818 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 18226076 67.11% 67.11% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 8932957 32.89% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 27159033 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12584209028 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 175099992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 13805070808 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 7247611234 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 204139691 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 586587181 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 79358164 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1355061 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75203006 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49096 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 3073 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2747928 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6733876 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.tags.replacements 3063828 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13784.638052 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 15005563 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 3079680 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.872442 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9994842368500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 2928.842366 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.432287 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 61.914602 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.974382 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7961.474415 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.178762 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004116 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003779 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168761 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485930 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.841348 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9851 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 102 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5899 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 232 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4639 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 3547 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1433 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 75 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 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13706.327130 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13706.327130 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 409000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 409000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 33608.899504 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33608.899504 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25748.347788 # average overall mshr miss latency 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WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.tags.replacements 4834403 # number of replacements +system.cpu1.dcache.tags.tagsinuse 460.748614 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 144950857 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4834915 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.980022 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8365240216000 # Cycle when the warmup percentage was hit. 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overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 51111445827 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 51111445827 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 34750982270 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 34750982270 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1576484749 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 1576484749 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3893749340 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3893749340 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 2823500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2823500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 85862428097 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 85862428097 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.inst 85862428097 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 85862428097 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.inst 78025612 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 78025612 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.inst 68779582 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 68779582 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 680221 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 680221 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 1738301 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1738301 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 1737042 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1737042 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 146805194 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 146805194 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 146805194 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 146805194 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046499 # miss rate for ReadReq accesses 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for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14087.463787 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14087.463787 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 17161.580613 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17161.580613 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13712.378653 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13712.378653 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 21173.073230 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21173.073230 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 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of cycles each access was blocked +system.cpu1.dcache.fast_writes 680221 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 2756922 # number of writebacks +system.cpu1.dcache.writebacks::total 2756922 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 322268 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 322268 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 829273 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 829273 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 78 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 78 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 59 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 1151541 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1151541 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 1151541 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1151541 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3305883 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3305883 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1194736 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1194736 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 114890 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 114890 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 183842 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 183842 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 4500619 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4500619 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 4500619 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4500619 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 39848912237 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39848912237 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 18776610903 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18776610903 # number of WriteReq MSHR miss cycles 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58625523140 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 58625523140 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 58625523140 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 58625523140 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3752867967 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3752867967 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3654726713 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3654726713 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 7407594680 # number of overall MSHR uncacheable cycles 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13026.102218 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 13026.102218 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13026.102218 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.tags.replacements 115612 # number of replacements +system.iocache.tags.tagsinuse 11.299913 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9121131291000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.419527 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.880386 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463720 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.242524 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706245 # Average percentage of cache occupancy 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8926 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106915 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106915 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8889 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8929 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8889 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8929 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001749 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.001749 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 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# average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 221066.414332 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 220754.547766 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 54362 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.902004 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 106728 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 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+system.iocache.ReadReq_mshr_miss_latency::realview.ide 1502702365 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1506479365 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6627847227 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6627847227 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3978000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1502702365 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1506680365 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3978000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1502702365 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1506680365 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102081.081081 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 169051.902914 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 168774.295877 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini new file mode 100644 index 000000000..f34f6e208 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini @@ -0,0 +1,1647 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload= +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 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+[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 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system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr new file mode 100644 index 000000000..744db2c76 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr @@ -0,0 +1,11 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout new file mode 100644 index 000000000..9642d869b --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout @@ -0,0 +1,16 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:29:11 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 + 0: system.cpu.isa: ISA system set to: 0x5c61b00 0x5c61b00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80080000 +info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 51727209160500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt new file mode 100644 index 000000000..19a412b67 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -0,0 +1,1323 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 51.727209 # Number of seconds simulated +sim_ticks 51727209160500 # Number of ticks simulated +final_tick 51727209160500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 180889 # Simulator instruction rate (inst/s) +host_op_rate 212546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9849373518 # Simulator tick rate (ticks/s) +host_mem_usage 656984 # Number of bytes of host memory used +host_seconds 5251.83 # Real time elapsed on the host +sim_insts 949996153 # Number of instructions simulated +sim_ops 1116252474 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.ide 424768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 725248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 1005696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 91312008 # Number of bytes read from this memory +system.physmem.bytes_read::total 93467720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9575168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9575168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 57345920 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.inst 101255460 # Number of bytes written to this memory +system.physmem.bytes_written::total 165427876 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 6637 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 11332 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 15714 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1426763 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1460446 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 896030 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.inst 1584368 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2587062 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 8212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 14021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 19442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1765261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1806935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 185109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 185109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1108622 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 131971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.inst 1957489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3198082 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1108622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 140183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 14021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 19442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3722750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5005018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1460446 # Number of read requests accepted +system.physmem.writeReqs 2587062 # Number of write requests accepted +system.physmem.readBursts 1460446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2587062 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 93277376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 191168 # Total number of bytes read from write queue +system.physmem.bytesWritten 160708736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 93467720 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 165427876 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2987 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 75973 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 39020 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 90929 # Per bank write bursts +system.physmem.perBankRdBursts::1 88965 # Per bank write bursts +system.physmem.perBankRdBursts::2 84770 # Per bank write bursts +system.physmem.perBankRdBursts::3 81753 # Per bank write bursts +system.physmem.perBankRdBursts::4 95872 # Per bank write bursts +system.physmem.perBankRdBursts::5 100020 # Per bank write bursts +system.physmem.perBankRdBursts::6 87194 # Per bank write bursts +system.physmem.perBankRdBursts::7 85191 # Per bank write bursts +system.physmem.perBankRdBursts::8 88300 # Per bank write bursts +system.physmem.perBankRdBursts::9 142631 # Per bank write bursts +system.physmem.perBankRdBursts::10 90249 # Per bank write bursts +system.physmem.perBankRdBursts::11 90988 # Per bank write bursts +system.physmem.perBankRdBursts::12 86795 # Per bank write bursts +system.physmem.perBankRdBursts::13 81108 # Per bank write bursts +system.physmem.perBankRdBursts::14 81197 # Per bank write bursts +system.physmem.perBankRdBursts::15 81497 # Per bank write bursts +system.physmem.perBankWrBursts::0 153488 # Per bank write bursts +system.physmem.perBankWrBursts::1 130402 # Per bank write bursts +system.physmem.perBankWrBursts::2 156905 # Per bank write bursts +system.physmem.perBankWrBursts::3 130743 # Per bank write bursts +system.physmem.perBankWrBursts::4 190154 # Per bank write bursts +system.physmem.perBankWrBursts::5 164896 # Per bank write bursts +system.physmem.perBankWrBursts::6 144797 # Per bank write bursts +system.physmem.perBankWrBursts::7 175639 # Per bank write bursts +system.physmem.perBankWrBursts::8 162274 # Per bank write bursts +system.physmem.perBankWrBursts::9 194391 # Per bank write bursts +system.physmem.perBankWrBursts::10 215398 # Per bank write bursts +system.physmem.perBankWrBursts::11 156932 # Per bank write bursts +system.physmem.perBankWrBursts::12 147011 # Per bank write bursts +system.physmem.perBankWrBursts::13 124629 # Per bank write bursts +system.physmem.perBankWrBursts::14 132966 # Per bank write bursts +system.physmem.perBankWrBursts::15 130449 # Per bank write bursts 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activation +system.physmem.bytesPerActivate::512-639 26784 3.43% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 18838 2.41% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14160 1.81% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 15996 2.05% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 118236 15.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 780499 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 115810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.584803 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 189.442624 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 115806 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-30719 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::49152-51199 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 115810 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 115810 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.682704 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.755419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.614982 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 58231 50.28% 50.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 24453 21.11% 71.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 18350 15.84% 87.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 9042 7.81% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1932 1.67% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 855 0.74% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 730 0.63% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 458 0.40% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 355 0.31% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 216 0.19% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 209 0.18% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 191 0.16% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 504 0.44% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 74 0.06% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 53 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 51 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 44 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 5 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 14 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 5 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 115810 # Writes before turning the bus around for reads +system.physmem.totQLat 16665773749 # Total ticks spent queuing +system.physmem.totMemAccLat 43993129999 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7287295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11434.81 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30184.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.20 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing +system.physmem.readRowHits 1137142 # Number of row buffer hits during reads +system.physmem.writeRowHits 2050889 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.67 # Row buffer hit rate for writes +system.physmem.avgGap 12780013.64 # Average gap between requests +system.physmem.pageHitRate 80.33 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49431156944750 # Time in different power states +system.physmem.memoryStateTime::REF 1727285040000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 568765880250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 2969235360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2931337080 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1620118500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1599439875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 5574566400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 5793535800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 8080715520 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 8191044000 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3378569538240 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3378569538240 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1383201002250 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1386870926445 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29822988580500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29819769348750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34603003756770 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34603725170190 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.951744 # Core power per rank (mW) +system.physmem.averagePower::1 668.965690 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 16 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 594629 # Transaction distribution +system.membus.trans_dist::ReadResp 594629 # Transaction distribution +system.membus.trans_dist::WriteReq 33870 # Transaction distribution +system.membus.trans_dist::WriteResp 33870 # Transaction distribution +system.membus.trans_dist::Writeback 896030 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1688459 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1688459 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39025 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39026 # Transaction distribution +system.membus.trans_dist::ReadExReq 901834 # Transaction distribution +system.membus.trans_dist::ReadExResp 901834 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7050430 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7180576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228843 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 228843 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7409419 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 251644332 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 251815240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7251264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7251264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 259066504 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2247 # Total snoops (count) +system.membus.snoop_fanout::samples 4033943 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 4033943 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 4033943 # Request fanout histogram +system.membus.reqLayer0.occupancy 113743500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5505500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 25619760742 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 15669502469 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186602993 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1669 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 40404 # Transaction distribution +system.iobus.trans_dist::ReadResp 40404 # Transaction distribution +system.iobus.trans_dist::WriteReq 136687 # Transaction distribution +system.iobus.trans_dist::WriteResp 136733 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 46 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354274 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492854 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 981194482 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179049007 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 259878452 # Number of BP lookups +system.cpu.branchPred.condPredicted 182434681 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12106293 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 193171007 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136122005 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 70.467099 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31463060 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2055318 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 183357098 # DTB read hits +system.cpu.dtb.read_misses 476791 # DTB read misses +system.cpu.dtb.write_hits 162738381 # DTB write hits +system.cpu.dtb.write_misses 102414 # DTB write misses +system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 47228 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 80239 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 828 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14730 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 23395 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 183833889 # DTB read accesses +system.cpu.dtb.write_accesses 162840795 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 346095479 # DTB hits +system.cpu.dtb.misses 579205 # DTB misses +system.cpu.dtb.accesses 346674684 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 453041166 # ITB inst hits +system.cpu.itb.inst_misses 137089 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 47228 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 57684 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 391598 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 453178255 # ITB inst accesses +system.cpu.itb.hits 453041166 # DTB hits +system.cpu.itb.misses 137089 # DTB misses +system.cpu.itb.accesses 453178255 # DTB accesses +system.cpu.numCycles 2529291390 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 949996153 # Number of instructions committed +system.cpu.committedOps 1116252474 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97459423 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7746 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100926289028 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.662423 # CPI: cycles per instruction +system.cpu.ipc 0.375598 # IPC: instructions per cycle +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 16606 # number of quiesce instructions executed +system.cpu.tickCycles 1758931949 # Number of cycles that the object actually ticked +system.cpu.idleCycles 770359441 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 24421267 # number of replacements +system.cpu.icache.tags.tagsinuse 511.933272 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 428216370 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24421779 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.534201 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20287456250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.933272 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 477059947 # Number of tag accesses +system.cpu.icache.tags.data_accesses 477059947 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 428216370 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 428216370 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 428216370 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 428216370 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 428216370 # number of overall hits +system.cpu.icache.overall_hits::total 428216370 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24421789 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24421789 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24421789 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24421789 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24421789 # number of overall misses +system.cpu.icache.overall_misses::total 24421789 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 323902842267 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 323902842267 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 323902842267 # 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miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73013.138455 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73103.103621 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78365.006177 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77181.366934 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73013.138455 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73103.103621 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 896030 # number of writebacks +system.cpu.l2cache.writebacks::total 896030 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 11332 # 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uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8007389750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 5176574500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176574500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 13183964250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13183964250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011753 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.054601 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014793 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015050 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.772307 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.772307 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.380309 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.380309 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011753 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.054601 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040062 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.039412 # 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miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10015.186499 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.186499 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59479.473034 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59479.473034 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65925.630957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64757.286496 # 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WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 11147587 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.959699 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 329635231 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11148099 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.568739 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. 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183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6530998375 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6530998375 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1476815114 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1480559114 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1476815114 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1480559114 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 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+type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +LFSTSize=1024 +LQEntries=16 +LSQCheckLoads=true +LSQDepCheckShift=0 +SQEntries=16 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=system.cpu.checker +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=2 +decodeWidth=3 +dispatchWidth=6 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=16 +fetchQueueSize=32 +fetchToDecodeDelay=3 +fetchTrapLatency=1 +fetchWidth=3 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=32 +numPhysCCRegs=640 +numPhysFloatRegs=192 +numPhysIntRegs=128 +numROBEntries=40 +numRobs=1 +numThreads=1 +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=1 +renameToROBDelay=1 +renameWidth=3 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload= +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=2048 +BTBTagSize=18 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=bi-mode + +[system.cpu.checker] +type=O3Checker +children=dstage2_mmu dtb isa istage2_mmu itb tracer +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.checker.dstage2_mmu +dtb=system.cpu.checker.dtb +eventq_index=0 +exitOnError=false +function_trace=false +function_trace_start=0 +interrupts=Null +isa=system.cpu.checker.isa +istage2_mmu=system.cpu.checker.istage2_mmu +itb=system.cpu.checker.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.checker.tracer +updateOnError=true +warnOnlyOnLoadError=true +workload= + +[system.cpu.checker.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb +tlb=system.cpu.checker.dtb + +[system.cpu.checker.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker + +[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[9] + +[system.cpu.checker.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.checker.dtb.walker + +[system.cpu.checker.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[7] + +[system.cpu.checker.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.checker.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb +tlb=system.cpu.checker.itb + +[system.cpu.checker.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker + +[system.cpu.checker.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[8] + +[system.cpu.checker.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.checker.itb.walker + +[system.cpu.checker.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[6] + +[system.cpu.checker.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 opList2 +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +issueLat=12 +opClass=IntDiv +opLat=12 + +[system.cpu.fuPool.FUList1.opList2] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IprAccess +opLat=3 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList + +[system.cpu.fuPool.FUList2.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList + +[system.cpu.fuPool.FUList3.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemWrite +opLat=2 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 + +[system.cpu.fuPool.FUList4.opList00] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAdd +opLat=4 + +[system.cpu.fuPool.FUList4.opList01] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAddAcc +opLat=4 + +[system.cpu.fuPool.FUList4.opList02] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAlu +opLat=4 + +[system.cpu.fuPool.FUList4.opList03] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCmp +opLat=4 + +[system.cpu.fuPool.FUList4.opList04] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCvt +opLat=3 + +[system.cpu.fuPool.FUList4.opList05] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMisc +opLat=3 + +[system.cpu.fuPool.FUList4.opList06] +type=OpDesc +eventq_index=0 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+issueLat=33 +opClass=FloatSqrt +opLat=33 + +[system.cpu.fuPool.FUList4.opList25] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr new file mode 100644 index 000000000..8d34f421c --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr @@ -0,0 +1,91 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: 13842443212000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13881966762000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13882255463000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13882829689000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13883384376000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13883639881500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13885195478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14119823023500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14121701098000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14127958169500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14128186290500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14128405933500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14128812861500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14129226204500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14167422773000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14205629937000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14448292905000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14448293175500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14456513700500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14456513960000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14464465597000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14464465877500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14464466467500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14464466743000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14464466981000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14472409559000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14472410152500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14472410415000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14472410653000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14472410900000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14477663411000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14483940515000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14483940774000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14493678366500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14504940200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14504941281500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14504941528000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14514859454000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14514859717500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14530591953000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14530592212000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14535730342000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14535730633500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14535731223500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14535731486000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14535731724000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14542816759000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14542817022500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14553011613000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14553012206500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14553012482000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14553012757000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14553013043000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14617580022000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14617580304000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14677231930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14677232200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14798881767000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14798974404500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14798974754500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799704795000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799705056000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42 +warn: 14799705260500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799777436500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14799777691500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799777962500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 +warn: 14799778533000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799778788500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14799779012000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799779301000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799779810000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799780873500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799781372500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14799781674500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14848040219000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: 14848040537000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14848040839000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14848041113000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14848041396500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14848041675500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout new file mode 100644 index 000000000..4029bb1c2 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout @@ -0,0 +1,17 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:38:57 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 + 0: system.cpu.checker.isa: ISA system set to: 0x48ecb00 0x48ecb00 + 0: system.cpu.isa: ISA system set to: 0x48ecb00 0x48ecb00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80080000 +info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 51557114994500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt new file mode 100644 index 000000000..173ad2168 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -0,0 +1,1771 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 51.557115 # Number of seconds simulated +sim_ticks 51557114994500 # Number of ticks simulated +final_tick 51557114994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 81227 # Simulator instruction rate (inst/s) +host_op_rate 95475 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3758004040 # Simulator tick rate (ticks/s) +host_mem_usage 668380 # Number of bytes of host memory used +host_seconds 13719.28 # Real time elapsed on the host +sim_insts 1114380469 # Number of instructions simulated +sim_ops 1309844804 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.ide 437568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1002304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 1237760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6145632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 128560840 # Number of bytes read from this memory +system.physmem.bytes_read::total 137384104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6145632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6145632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 102180288 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 102783780 # Number of bytes written to this memory +system.physmem.bytes_written::total 211790564 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 6837 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 15661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 19340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 111978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2008776 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2162592 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1596567 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 1608248 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3311479 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 8487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 19441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 24008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 119200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2493562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2664697 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 119200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 119200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1981885 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 132406 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1993591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4107882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1981885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 140894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 19441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 24008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 119200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4487152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6772580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2162592 # Number of read requests accepted +system.physmem.writeReqs 3311479 # Number of write requests accepted +system.physmem.readBursts 2162592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 3311479 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 138204608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 201280 # Total number of bytes read from write queue +system.physmem.bytesWritten 207618304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 137384104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 211790564 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 3145 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 67428 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 48470 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 140382 # Per bank write bursts +system.physmem.perBankRdBursts::1 139333 # Per bank write bursts +system.physmem.perBankRdBursts::2 140658 # Per bank write bursts +system.physmem.perBankRdBursts::3 133921 # Per bank write bursts +system.physmem.perBankRdBursts::4 130324 # Per bank write bursts +system.physmem.perBankRdBursts::5 134612 # Per bank write bursts +system.physmem.perBankRdBursts::6 126217 # Per bank write bursts +system.physmem.perBankRdBursts::7 133097 # Per bank write bursts +system.physmem.perBankRdBursts::8 129592 # Per bank write bursts +system.physmem.perBankRdBursts::9 157619 # Per bank write bursts +system.physmem.perBankRdBursts::10 133394 # Per bank write bursts +system.physmem.perBankRdBursts::11 133867 # Per bank write bursts +system.physmem.perBankRdBursts::12 132326 # Per bank write bursts +system.physmem.perBankRdBursts::13 132284 # Per bank write bursts +system.physmem.perBankRdBursts::14 133117 # Per bank write bursts +system.physmem.perBankRdBursts::15 128704 # Per bank write bursts +system.physmem.perBankWrBursts::0 201659 # Per bank write bursts +system.physmem.perBankWrBursts::1 203665 # Per bank write bursts +system.physmem.perBankWrBursts::2 231223 # Per bank write bursts +system.physmem.perBankWrBursts::3 188549 # Per bank write bursts +system.physmem.perBankWrBursts::4 224931 # Per bank write bursts +system.physmem.perBankWrBursts::5 188791 # Per bank write bursts +system.physmem.perBankWrBursts::6 176287 # Per bank write bursts +system.physmem.perBankWrBursts::7 226882 # Per bank write bursts +system.physmem.perBankWrBursts::8 203233 # Per bank write bursts +system.physmem.perBankWrBursts::9 233524 # Per bank write bursts +system.physmem.perBankWrBursts::10 253232 # Per bank write bursts +system.physmem.perBankWrBursts::11 198347 # Per bank write bursts +system.physmem.perBankWrBursts::12 181957 # Per bank write bursts +system.physmem.perBankWrBursts::13 175879 # Per bank write bursts +system.physmem.perBankWrBursts::14 180282 # Per bank write bursts +system.physmem.perBankWrBursts::15 175595 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 190 # Number of times write queue was full causing retry +system.physmem.totGap 51557113761500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 13 # Read request sizes (log2) +system.physmem.readPktSize::4 21272 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 2141307 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 1 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 3308906 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1296550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 764534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 68768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 55343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 88539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 132669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 172060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 179259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 199827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 201826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 215089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 217686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 234764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 216813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 209096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 190795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 202440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 157954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 153989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 157951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 145311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 7805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 5695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 3461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 474 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1034839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 334.179783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.532509 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.014667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 392208 37.90% 37.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 234584 22.67% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87901 8.49% 69.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 49413 4.77% 73.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38348 3.71% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26689 2.58% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21988 2.12% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25501 2.46% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 158207 15.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1034839 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 135592 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.925969 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 128.724301 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 135587 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-43007 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 135592 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 135592 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.924981 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.930688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.164557 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 101303 74.71% 74.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 7599 5.60% 80.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 12845 9.47% 89.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 3908 2.88% 92.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 2324 1.71% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 925 0.68% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 2932 2.16% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1250 0.92% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 889 0.66% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 249 0.18% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 327 0.24% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 193 0.14% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 473 0.35% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 16 0.01% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 22 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 28 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 17 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 31 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 89 0.07% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 56 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 42 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 15 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 15 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 6 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 5 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 5 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 135592 # Writes before turning the bus around for reads +system.physmem.totQLat 43990891280 # Total ticks spent queuing +system.physmem.totMemAccLat 84480522530 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10797235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20371.37 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 39121.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing +system.physmem.readRowHits 1747291 # Number of row buffer hits during reads +system.physmem.writeRowHits 2621349 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes +system.physmem.avgGap 9418422.55 # Average gap between requests +system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49290195125250 # Time in different power states +system.physmem.memoryStateTime::REF 1721605340000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 545313634750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3951453240 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3871929600 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2156050875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2112660000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 8412588600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 8431020000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 10640075760 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 10381277520 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3367460045040 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3367460045040 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1383947967870 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1368871606665 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29720278968750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29733503847000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34496847150135 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34494632385825 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.099654 # Core power per rank (mW) +system.physmem.averagePower::1 669.056696 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 657217 # Transaction distribution +system.membus.trans_dist::ReadResp 657217 # Transaction distribution +system.membus.trans_dist::WriteReq 33865 # Transaction distribution +system.membus.trans_dist::WriteResp 33865 # Transaction distribution +system.membus.trans_dist::Writeback 1596567 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1712339 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1712339 # Transaction distribution +system.membus.trans_dist::UpgradeReq 48473 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 48476 # Transaction distribution +system.membus.trans_dist::ReadExReq 1541174 # Transaction distribution +system.membus.trans_dist::ReadExResp 1541174 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9221519 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9351669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229018 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 229018 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9580687 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341910604 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 342081160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7264064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 349345224 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2022 # Total snoops (count) +system.membus.snoop_fanout::samples 5500895 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 5500895 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 5500895 # Request fanout histogram +system.membus.reqLayer0.occupancy 109641999 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5450500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 32462148974 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 21571101815 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186532342 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1669 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 40379 # Transaction distribution +system.iobus.trans_dist::ReadResp 40379 # Transaction distribution +system.iobus.trans_dist::WriteReq 136716 # Transaction distribution +system.iobus.trans_dist::WriteResp 136733 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 17 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492654 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 981079506 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179002658 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 291488483 # Number of BP lookups +system.cpu.branchPred.condPredicted 200150149 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13608043 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 209143322 # Number of BTB lookups +system.cpu.branchPred.BTBHits 138326751 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 66.139693 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37688944 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 403819 # Number of incorrect RAS predictions. +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.inst_hits 0 # ITB inst hits +system.cpu.checker.dtb.inst_misses 0 # ITB inst misses +system.cpu.checker.dtb.read_hits 206311750 # DTB read hits +system.cpu.checker.dtb.read_misses 258027 # DTB read misses +system.cpu.checker.dtb.write_hits 190103200 # DTB write hits +system.cpu.checker.dtb.write_misses 94684 # DTB write misses +system.cpu.checker.dtb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dtb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 89489 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dtb.prefetch_faults 10233 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dtb.perms_faults 24751 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 206569777 # DTB read accesses +system.cpu.checker.dtb.write_accesses 190197884 # DTB write accesses +system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dtb.hits 396414950 # DTB hits +system.cpu.checker.dtb.misses 352711 # DTB misses +system.cpu.checker.dtb.accesses 396767661 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.inst_hits 1114925280 # ITB inst hits +system.cpu.checker.itb.inst_misses 131008 # ITB inst misses +system.cpu.checker.itb.read_hits 0 # DTB read hits +system.cpu.checker.itb.read_misses 0 # DTB read misses +system.cpu.checker.itb.write_hits 0 # DTB write hits +system.cpu.checker.itb.write_misses 0 # DTB write misses +system.cpu.checker.itb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.itb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 61860 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.itb.read_accesses 0 # DTB read accesses +system.cpu.checker.itb.write_accesses 0 # DTB write accesses +system.cpu.checker.itb.inst_accesses 1115056288 # ITB inst accesses +system.cpu.checker.itb.hits 1114925280 # DTB hits +system.cpu.checker.itb.misses 131008 # DTB misses +system.cpu.checker.itb.accesses 1115056288 # DTB accesses +system.cpu.checker.numCycles 1310563748 # number of cpu cycles simulated +system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 220000246 # DTB read hits +system.cpu.dtb.read_misses 1007031 # DTB read misses +system.cpu.dtb.write_hits 193886106 # DTB write hits +system.cpu.dtb.write_misses 416122 # DTB write misses +system.cpu.dtb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 89690 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 112 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15179 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 87251 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 221007277 # DTB read accesses +system.cpu.dtb.write_accesses 194302228 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 413886352 # DTB hits +system.cpu.dtb.misses 1423153 # DTB misses +system.cpu.dtb.accesses 415309505 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 465588468 # ITB inst hits +system.cpu.itb.inst_misses 176797 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 22 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 127936 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2418 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 63536 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 462381 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 465765265 # ITB inst accesses +system.cpu.itb.hits 465588468 # DTB hits +system.cpu.itb.misses 176797 # DTB misses +system.cpu.itb.accesses 465765265 # DTB accesses +system.cpu.numCycles 2146849645 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 791511347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1301628389 # Number of instructions fetch has processed +system.cpu.fetch.Branches 291488483 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 176015695 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1268750537 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29307286 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4254748 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 12217982 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1219824 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 381 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 465107423 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6746831 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 53918 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2092636388 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.729302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.142136 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1367675983 65.36% 65.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 280886167 13.42% 78.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 86945610 4.15% 82.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 357128628 17.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 2092636388 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.135775 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.606297 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 614820490 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 852644163 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 531180111 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 83391963 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10599661 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41490545 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4112846 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1415541998 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32718079 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10599661 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 678805488 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 83662136 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 556428904 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 549849830 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 213290369 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1391734034 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 7977079 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7435136 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 893230 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1023922 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 127479585 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 25199 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1342075875 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2217645602 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1652184740 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1639045 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1263873564 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78202308 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44203192 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39719264 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 172796539 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 223511224 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 198396121 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12647992 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11061331 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1338396177 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 44508712 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1370133902 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4153047 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65240654 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41320787 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 373617 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2092636388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.654741 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.915536 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1237717942 59.15% 59.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 455529583 21.77% 80.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 292996726 14.00% 94.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96986296 4.63% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9377226 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28615 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2092636388 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 74528454 34.28% 34.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90672 0.04% 34.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26772 0.01% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 287 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 58830485 27.06% 61.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83911289 38.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 945793660 69.03% 69.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2946266 0.22% 69.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 129775 0.01% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 114397 0.01% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 224851656 16.41% 85.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 196298100 14.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1370133902 # Type of FU issued +system.cpu.iq.rate 0.638207 # Inst issue rate +system.cpu.iq.fu_busy_cnt 217387959 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.158662 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5052021388 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1447405501 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1347303683 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2423809 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 923681 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 885699 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1585997449 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1524411 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5766333 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 16996131 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24128 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 185382 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8259714 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 3623609 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3385962 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 10599661 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11961718 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7304667 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1383179145 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 223511224 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 198396121 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39177517 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 185228 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6936317 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 185382 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4274350 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5730421 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10004771 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1356817685 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 220004444 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11924579 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 274256 # number of nop insts executed +system.cpu.iew.exec_refs 413901554 # number of memory reference insts executed +system.cpu.iew.exec_branches 257473473 # Number of branches executed +system.cpu.iew.exec_stores 193897110 # Number of stores executed +system.cpu.iew.exec_rate 0.632004 # Inst execution rate +system.cpu.iew.wb_sent 1349182874 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1348189382 # cumulative count of insts written-back +system.cpu.iew.wb_producers 579023420 # num instructions producing a value +system.cpu.iew.wb_consumers 949767765 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.627985 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.609647 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitSquashedInsts 62443917 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 44135095 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9554061 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2078483160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.630193 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.269789 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1396354428 67.18% 67.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 397736022 19.14% 86.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 152396085 7.33% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44287772 2.13% 95.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35996912 1.73% 97.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18656723 0.90% 98.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10905184 0.52% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5449343 0.26% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16700691 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 2078483160 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1114380469 # Number of instructions committed +system.cpu.commit.committedOps 1309844804 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 396651499 # Number of memory references committed +system.cpu.commit.loads 206515092 # Number of loads committed +system.cpu.commit.membars 9189565 # Number of memory barriers committed +system.cpu.commit.branches 249089949 # Number of branches committed +system.cpu.commit.fp_insts 873640 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1196978104 # Number of committed integer instructions. +system.cpu.commit.function_calls 31078874 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 910428363 69.51% 69.51% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2554988 0.20% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 104143 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 105769 0.01% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 206515092 15.77% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 190136407 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1309844804 # Class of committed instruction +system.cpu.commit.bw_lim_events 16700691 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 3424556806 # The number of ROB reads +system.cpu.rob.rob_writes 2758622493 # The number of ROB writes +system.cpu.timesIdled 9031521 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 54213257 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100967380384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1114380469 # Number of Instructions Simulated +system.cpu.committedOps 1309844804 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.926496 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.926496 # CPI: Total CPI of All Threads +system.cpu.ipc 0.519077 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.519077 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1611998606 # number of integer regfile reads +system.cpu.int_regfile_writes 948639329 # number of integer regfile writes +system.cpu.fp_regfile_reads 1420015 # number of floating regfile reads +system.cpu.fp_regfile_writes 765124 # number of floating regfile writes +system.cpu.cc_regfile_reads 315259155 # number of cc regfile reads +system.cpu.cc_regfile_writes 316098925 # number of cc regfile writes +system.cpu.misc_regfile_reads 6952427793 # number of misc regfile reads +system.cpu.misc_regfile_writes 45059384 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 28539920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28531649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33865 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33865 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 9369509 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1712344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1605675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 61529 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 61535 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3074731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3074731 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33703094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37825776 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 810571 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3115869 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 75455310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1077469744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1502191576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2724416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10868120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2593253856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 644632 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 42703026 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9.002705 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.051942 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 42587504 99.73% 99.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 115522 0.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 42703026 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32333793873 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 871500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 25296093441 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 19876823538 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 472614279 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 1760067316 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.icache.tags.replacements 16829629 # number of replacements +system.cpu.icache.tags.tagsinuse 511.959617 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 447510611 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16830141 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.589831 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 12236526000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.959617 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 481916487 # Number of tag accesses +system.cpu.icache.tags.data_accesses 481916487 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 447510611 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 447510611 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 447510611 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 447510611 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 447510611 # number of overall hits +system.cpu.icache.overall_hits::total 447510611 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17575514 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17575514 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17575514 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17575514 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17575514 # number of overall misses +system.cpu.icache.overall_misses::total 17575514 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 231527181766 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 231527181766 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 231527181766 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 231527181766 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 231527181766 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 231527181766 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465086125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465086125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465086125 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465086125 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465086125 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465086125 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.037790 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.037790 # miss rate for ReadReq accesses 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was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 920 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 12.047826 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 745151 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 745151 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 745151 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 745151 # number of demand (read+write) MSHR hits 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of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 191394786019 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191394786019 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 191394786019 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1413030250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1413030250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1413030250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 1413030250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036188 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.036188 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.036188 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.993939 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11371.993939 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11371.993939 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11371.993939 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.993939 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.993939 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 1866229 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64521.528187 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 35312731 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1928499 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.310993 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 13813873928000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 34323.724648 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 307.320059 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.834309 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7078.453286 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 22362.195885 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.523738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004689 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006864 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.108009 # Average percentage of cache occupancy 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LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.082493 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082493 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087311 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087311 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16000.556505 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16000.556505 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53861.197196 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53861.197196 # average WriteReq miss latency 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+system.cpu.dcache.blocked::no_mshrs 2284719 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.772084 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 1605675 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 9369509 # number of writebacks +system.cpu.dcache.writebacks::total 9369509 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5628309 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5628309 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15829986 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15829986 # number of WriteReq MSHR hits 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cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 104997 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 104997 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250741484767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 250741484767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 282353153264 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 282353153264 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729434750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729434750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587276983 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587276983 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316711733 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316711733 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035271 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035271 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.017034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.017034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813798 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813798 # mshr miss rate for SoftPFReq accesses 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average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47510.555303 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47510.555303 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15305.942177 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15305.942177 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13181.068347 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13181.068347 # average LoadLockedReq mshr miss latency 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number of overall miss cycles +system.iocache.overall_miss_latency::total 1935281843 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106681 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106681 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses 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+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149918.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218926.114036 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 218637.609379 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 147150 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 218601.812154 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 147150 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 218601.812154 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 53350 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.717668 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses 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miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3806000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1470987863 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1474793863 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3806000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1470987863 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1474793863 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166911.138432 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 166622.696384 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 17164 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini new file mode 100644 index 000000000..7c36695c6 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini @@ -0,0 +1,2245 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.realview.nvmem system.physmem system.realview.vram +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=DerivO3CPU +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +LFSTSize=1024 +LQEntries=16 +LSQCheckLoads=true +LSQDepCheckShift=0 +SQEntries=16 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu0.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=2 +decodeWidth=3 +dispatchWidth=6 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu +dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=16 +fetchQueueSize=32 +fetchToDecodeDelay=3 +fetchTrapLatency=1 +fetchWidth=3 +forwardComSize=5 +fuPool=system.cpu0.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +issueToExecuteDelay=1 +issueWidth=8 +istage2_mmu=system.cpu0.istage2_mmu +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=32 +numPhysCCRegs=640 +numPhysFloatRegs=192 +numPhysIntRegs=128 +numROBEntries=40 +numRobs=1 +numThreads=1 +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=1 +renameToROBDelay=1 +renameWidth=3 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu0.tracer +trapLatency=13 +wbWidth=8 +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.branchPred] +type=BranchPredictor +BTBEntries=2048 +BTBTagSize=18 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=bi-mode + +[system.cpu0.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=6 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.dcache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=16 +cpu_side=system.cpu0.dcache_port +mem_side=system.cpu0.toL2Bus.slave[1] + +[system.cpu0.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[5] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[3] + +[system.cpu0.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 +FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 +eventq_index=0 + +[system.cpu0.fuPool.FUList0] +type=FUDesc +children=opList +count=2 +eventq_index=0 +opList=system.cpu0.fuPool.FUList0.opList + +[system.cpu0.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu0.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 opList2 +count=1 +eventq_index=0 +opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 system.cpu0.fuPool.FUList1.opList2 + +[system.cpu0.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu0.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +issueLat=12 +opClass=IntDiv +opLat=12 + +[system.cpu0.fuPool.FUList1.opList2] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IprAccess +opLat=3 + +[system.cpu0.fuPool.FUList2] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu0.fuPool.FUList2.opList + +[system.cpu0.fuPool.FUList2.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=2 + +[system.cpu0.fuPool.FUList3] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu0.fuPool.FUList3.opList + +[system.cpu0.fuPool.FUList3.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemWrite +opLat=2 + +[system.cpu0.fuPool.FUList4] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=2 +eventq_index=0 +opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 + +[system.cpu0.fuPool.FUList4.opList00] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAdd +opLat=4 + +[system.cpu0.fuPool.FUList4.opList01] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAddAcc +opLat=4 + +[system.cpu0.fuPool.FUList4.opList02] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAlu +opLat=4 + +[system.cpu0.fuPool.FUList4.opList03] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCmp +opLat=4 + +[system.cpu0.fuPool.FUList4.opList04] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCvt +opLat=3 + +[system.cpu0.fuPool.FUList4.opList05] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMisc +opLat=3 + +[system.cpu0.fuPool.FUList4.opList06] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMult +opLat=5 + +[system.cpu0.fuPool.FUList4.opList07] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMultAcc +opLat=5 + +[system.cpu0.fuPool.FUList4.opList08] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShift +opLat=3 + +[system.cpu0.fuPool.FUList4.opList09] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShiftAcc +opLat=3 + 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+opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu0.fuPool.FUList4.opList19] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatSqrt +opLat=9 + +[system.cpu0.fuPool.FUList4.opList20] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatAdd +opLat=5 + +[system.cpu0.fuPool.FUList4.opList21] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCmp +opLat=5 + +[system.cpu0.fuPool.FUList4.opList22] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCvt +opLat=5 + +[system.cpu0.fuPool.FUList4.opList23] +type=OpDesc +eventq_index=0 +issueLat=9 +opClass=FloatDiv +opLat=9 + +[system.cpu0.fuPool.FUList4.opList24] +type=OpDesc +eventq_index=0 +issueLat=33 +opClass=FloatSqrt +opLat=33 + +[system.cpu0.fuPool.FUList4.opList25] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu0.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=1 +is_top_level=true +max_miss_count=0 +mshrs=2 +prefetch_on_access=false +prefetcher=Null +response_latency=1 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.icache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.cpu0.toL2Bus.slave[0] + +[system.cpu0.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=1 +sequential_access=false +size=32768 + +[system.cpu0.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu0.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[4] + +[system.cpu0.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[2] + +[system.cpu0.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu0.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu0.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu0.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu0.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu0.l2cache.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu1] +type=DerivO3CPU +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +LFSTSize=1024 +LQEntries=16 +LSQCheckLoads=true +LSQDepCheckShift=0 +SQEntries=16 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu1.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=1 +decodeToFetchDelay=1 +decodeToRenameDelay=2 +decodeWidth=3 +dispatchWidth=6 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu +dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=16 +fetchQueueSize=32 +fetchToDecodeDelay=3 +fetchTrapLatency=1 +fetchWidth=3 +forwardComSize=5 +fuPool=system.cpu1.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu1.interrupts +isa=system.cpu1.isa +issueToExecuteDelay=1 +issueWidth=8 +istage2_mmu=system.cpu1.istage2_mmu +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=32 +numPhysCCRegs=640 +numPhysFloatRegs=192 +numPhysIntRegs=128 +numROBEntries=40 +numRobs=1 +numThreads=1 +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=1 +renameToROBDelay=1 +renameWidth=3 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu1.tracer +trapLatency=13 +wbWidth=8 +workload= +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.branchPred] +type=BranchPredictor +BTBEntries=2048 +BTBTagSize=18 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=bi-mode + +[system.cpu1.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=6 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu1.dcache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=16 +cpu_side=system.cpu1.dcache_port +mem_side=system.cpu1.toL2Bus.slave[1] + +[system.cpu1.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[5] + +[system.cpu1.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[3] + +[system.cpu1.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 +FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 +eventq_index=0 + +[system.cpu1.fuPool.FUList0] +type=FUDesc +children=opList +count=2 +eventq_index=0 +opList=system.cpu1.fuPool.FUList0.opList + +[system.cpu1.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu1.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 opList2 +count=1 +eventq_index=0 +opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2 + +[system.cpu1.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu1.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +issueLat=12 +opClass=IntDiv +opLat=12 + +[system.cpu1.fuPool.FUList1.opList2] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IprAccess +opLat=3 + +[system.cpu1.fuPool.FUList2] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu1.fuPool.FUList2.opList + +[system.cpu1.fuPool.FUList2.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=2 + +[system.cpu1.fuPool.FUList3] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu1.fuPool.FUList3.opList + +[system.cpu1.fuPool.FUList3.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemWrite +opLat=2 + +[system.cpu1.fuPool.FUList4] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=2 +eventq_index=0 +opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 + +[system.cpu1.fuPool.FUList4.opList00] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAdd +opLat=4 + +[system.cpu1.fuPool.FUList4.opList01] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAddAcc +opLat=4 + +[system.cpu1.fuPool.FUList4.opList02] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAlu +opLat=4 + +[system.cpu1.fuPool.FUList4.opList03] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCmp +opLat=4 + +[system.cpu1.fuPool.FUList4.opList04] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCvt +opLat=3 + +[system.cpu1.fuPool.FUList4.opList05] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMisc +opLat=3 + +[system.cpu1.fuPool.FUList4.opList06] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMult +opLat=5 + +[system.cpu1.fuPool.FUList4.opList07] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMultAcc +opLat=5 + +[system.cpu1.fuPool.FUList4.opList08] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShift +opLat=3 + +[system.cpu1.fuPool.FUList4.opList09] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShiftAcc +opLat=3 + +[system.cpu1.fuPool.FUList4.opList10] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdSqrt +opLat=9 + +[system.cpu1.fuPool.FUList4.opList11] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAdd +opLat=5 + +[system.cpu1.fuPool.FUList4.opList12] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAlu +opLat=5 + +[system.cpu1.fuPool.FUList4.opList13] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCmp +opLat=3 + +[system.cpu1.fuPool.FUList4.opList14] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCvt +opLat=3 + +[system.cpu1.fuPool.FUList4.opList15] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatDiv +opLat=3 + +[system.cpu1.fuPool.FUList4.opList16] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMisc +opLat=3 + +[system.cpu1.fuPool.FUList4.opList17] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMult +opLat=3 + +[system.cpu1.fuPool.FUList4.opList18] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu1.fuPool.FUList4.opList19] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatSqrt +opLat=9 + +[system.cpu1.fuPool.FUList4.opList20] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatAdd +opLat=5 + +[system.cpu1.fuPool.FUList4.opList21] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCmp +opLat=5 + +[system.cpu1.fuPool.FUList4.opList22] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCvt +opLat=5 + +[system.cpu1.fuPool.FUList4.opList23] +type=OpDesc +eventq_index=0 +issueLat=9 +opClass=FloatDiv +opLat=9 + +[system.cpu1.fuPool.FUList4.opList24] +type=OpDesc +eventq_index=0 +issueLat=33 +opClass=FloatSqrt +opLat=33 + +[system.cpu1.fuPool.FUList4.opList25] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu1.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=1 +is_top_level=true +max_miss_count=0 +mshrs=2 +prefetch_on_access=false +prefetcher=Null +response_latency=1 +sequential_access=false +size=32768 +system=system +tags=system.cpu1.icache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.cpu1.toL2Bus.slave[0] + +[system.cpu1.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=1 +sequential_access=false +size=32768 + +[system.cpu1.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu1.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[4] + +[system.cpu1.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[2] + +[system.cpu1.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu1.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu1.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[1] + +[system.cpu1.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu1.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu1.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu1.l2cache.cpu_side +slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu1.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.l2c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.l2c.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr new file mode 100644 index 000000000..bbb1cd360 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr @@ -0,0 +1,12 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: allocating bonus target for snoop +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout new file mode 100644 index 000000000..c9871ea6d --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout @@ -0,0 +1,17 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 11:56:54 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 + 0: system.cpu0.isa: ISA system set to: 0x5878b00 0x5878b00 + 0: system.cpu1.isa: ISA system set to: 0x5878b00 0x5878b00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80080000 +info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 47379674621500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt new file mode 100644 index 000000000..a72ace5ed --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -0,0 +1,3471 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 47.379675 # Number of seconds simulated +sim_ticks 47379674621500 # Number of ticks simulated +final_tick 47379674621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 109387 # Simulator instruction rate (inst/s) +host_op_rate 128661 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5550125892 # Simulator tick rate (ticks/s) +host_mem_usage 850512 # Number of bytes of host memory used +host_seconds 8536.68 # Real time elapsed on the host +sim_insts 933798389 # Number of instructions simulated +sim_ops 1098335322 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.ide 472128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 353088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 523648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1152800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 18354072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 38298624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 338240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 462784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 532064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12967328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 29162240 # Number of bytes read from this memory +system.physmem.bytes_read::total 102617016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1152800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 532064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1684864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 56488832 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 66623564 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 34275268 # Number of bytes written to this memory +system.physmem.bytes_written::total 164218256 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 7377 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 5517 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8182 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 33965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 286804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 598416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 5285 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 7231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 8357 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 202629 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 455660 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1619423 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 882638 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 1043270 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 535552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2568188 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 9965 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 7452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 11052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 24331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 387383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 808334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 7139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 9768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 11230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 273690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 615501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2165845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 24331 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 35561 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1192259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 144167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 1406163 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 723417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3466006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1192259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 154132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 7452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 11052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 24331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1793546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 808334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 7139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 9768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 11230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 997107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 615501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5631851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1619423 # Number of read requests accepted +system.physmem.writeReqs 2568188 # Number of write requests accepted +system.physmem.readBursts 1619423 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2568188 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 103371328 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 271744 # Total number of bytes read from write queue +system.physmem.bytesWritten 158872640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 102617016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 164218256 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 4246 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 85771 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 103144 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 111705 # Per bank write bursts +system.physmem.perBankRdBursts::1 107185 # Per bank write bursts +system.physmem.perBankRdBursts::2 95216 # Per bank write bursts +system.physmem.perBankRdBursts::3 93593 # Per bank write bursts +system.physmem.perBankRdBursts::4 97040 # Per bank write bursts +system.physmem.perBankRdBursts::5 109538 # Per bank write bursts +system.physmem.perBankRdBursts::6 103640 # Per bank write bursts +system.physmem.perBankRdBursts::7 104459 # Per bank write bursts +system.physmem.perBankRdBursts::8 87345 # Per bank write bursts +system.physmem.perBankRdBursts::9 119689 # Per bank write bursts +system.physmem.perBankRdBursts::10 87550 # Per bank write bursts +system.physmem.perBankRdBursts::11 102455 # Per bank write bursts +system.physmem.perBankRdBursts::12 98167 # Per bank write bursts +system.physmem.perBankRdBursts::13 96293 # Per bank write bursts +system.physmem.perBankRdBursts::14 97699 # Per bank write bursts +system.physmem.perBankRdBursts::15 103603 # Per bank write bursts +system.physmem.perBankWrBursts::0 151797 # Per bank write bursts +system.physmem.perBankWrBursts::1 157102 # Per bank write bursts +system.physmem.perBankWrBursts::2 173467 # Per bank write bursts +system.physmem.perBankWrBursts::3 129226 # Per bank write bursts +system.physmem.perBankWrBursts::4 217724 # Per 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write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 3546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3135 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::63 674 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 968355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 270.813741 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.322670 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.242545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 500729 51.71% 51.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 182951 18.89% 70.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 62910 6.50% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 30320 3.13% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 27676 2.86% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15651 1.62% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 12433 1.28% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 15606 1.61% 87.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 120079 12.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 968355 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 90300 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.886467 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 201.343157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 90297 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 90300 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 90300 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.490421 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 23.640759 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.748039 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 56859 62.97% 62.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 8057 8.92% 71.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 12273 13.59% 85.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 3990 4.42% 89.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 1898 2.10% 92.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 944 1.05% 93.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 2681 2.97% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1258 1.39% 97.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 729 0.81% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 233 0.26% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 328 0.36% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 174 0.19% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 473 0.52% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 16 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 44 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 33 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 16 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 34 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 77 0.09% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 57 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 40 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 21 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 22 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 90300 # Writes before turning the bus around for reads +system.physmem.totQLat 65880977516 # Total ticks spent queuing +system.physmem.totMemAccLat 96165546266 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8075885000 # Total ticks spent in databus transfers +system.physmem.avgQLat 40788.70 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 59538.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.47 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 3.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing +system.physmem.readRowHits 1266207 # Number of row buffer hits during reads +system.physmem.writeRowHits 1862998 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.05 # Row buffer hit rate for writes +system.physmem.avgGap 11314248.90 # Average gap between requests +system.physmem.pageHitRate 76.37 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 45458713155000 # Time in different power states +system.physmem.memoryStateTime::REF 1582111440000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 338849669500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3771472320 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3549283920 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2057847000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1936613250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 6414501600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 6183847800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 8526034080 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 7559820720 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3094609976640 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3094609976640 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1215510046335 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1201972779180 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 27361567580250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 27373442376000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 31692457458225 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 31689254697510 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.904083 # Core power per rank (mW) +system.physmem.averagePower::1 668.836485 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 1503713 # Transaction distribution +system.membus.trans_dist::ReadResp 1503713 # Transaction distribution +system.membus.trans_dist::WriteReq 38586 # Transaction distribution +system.membus.trans_dist::WriteResp 38586 # Transaction distribution +system.membus.trans_dist::Writeback 882638 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1682947 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1682947 # Transaction distribution +system.membus.trans_dist::UpgradeReq 373970 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 331267 # Transaction distribution +system.membus.trans_dist::UpgradeResp 103150 # Transaction distribution +system.membus.trans_dist::ReadExReq 170539 # Transaction distribution +system.membus.trans_dist::ReadExResp 155861 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26002 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 8087433 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 8236597 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 229762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 8466359 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156191 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 259532552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 259741319 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7302720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 267044039 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 618323 # Total snoops (count) +system.membus.snoop_fanout::samples 4885385 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 4885385 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 4885385 # Request fanout histogram +system.membus.reqLayer0.occupancy 98770920 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 21644945 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 25191464236 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 16556458898 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 187451430 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.l2c.tags.replacements 1387044 # number of replacements +system.l2c.tags.tagsinuse 64427.808632 # Cycle average of tags in use +system.l2c.tags.total_refs 7620997 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1449367 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.258155 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10003.170740 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 188.441651 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.424548 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 921.507825 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8419.959281 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24297.060802 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 189.151688 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 259.454485 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 442.813505 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5057.928398 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14404.895708 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.152636 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002875 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003714 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.014061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.128478 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370744 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002886 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003959 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.006757 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.077178 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.219801 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983090 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33631 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 302 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 28390 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 86 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 2393 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1787 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29347 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 16 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 216 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2265 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4264 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 21604 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.513168 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004608 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.433197 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 91165244 # Number of tag accesses +system.l2c.tags.data_accesses 91165244 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 7553 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4301 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 170694 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 696092 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1825935 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 8223 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5157 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 162945 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 691200 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1816536 # number of ReadReq hits +system.l2c.ReadReq_hits::total 5388636 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2284318 # number of Writeback hits +system.l2c.Writeback_hits::total 2284318 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 28567 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 31425 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 59992 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 8944 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 7440 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16384 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 53362 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 53750 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107112 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 7553 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4301 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 170694 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 749454 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 1825935 # number of demand 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+system.l2c.demand_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 7757807 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7750243 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38586 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38586 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2284318 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1682954 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1576219 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 430271 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 347651 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 777922 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 191 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 316482 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 316482 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11788342 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9897130 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 21685472 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 381410986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320139805 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 701550791 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1633796 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 12761522 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.009063 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.094770 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 12645858 99.09% 99.09% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115664 0.91% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 12761522 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 21862906503 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 6130500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 19509958221 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 17925237290 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40417 # Transaction distribution +system.iobus.trans_dist::ReadResp 40417 # Transaction distribution +system.iobus.trans_dist::WriteReq 136643 # Transaction distribution +system.iobus.trans_dist::WriteResp 136782 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 139 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354398 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7497229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 982013630 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179230570 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 146587108 # Number of BP lookups +system.cpu0.branchPred.condPredicted 96932064 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7164901 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 103453764 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 67642054 # Number of BTB hits +system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.branchPred.BTBHitPct 65.383850 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20270932 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 203679 # Number of incorrect RAS predictions. +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 106134781 # DTB read hits +system.cpu0.dtb.read_misses 438400 # DTB read misses +system.cpu0.dtb.write_hits 87107060 # DTB write hits +system.cpu0.dtb.write_misses 166320 # DTB write misses +system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 41289 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 449 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7213 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 39737 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 106573181 # DTB read accesses +system.cpu0.dtb.write_accesses 87273380 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 193241841 # DTB hits +system.cpu0.dtb.misses 604720 # DTB misses +system.cpu0.dtb.accesses 193846561 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 230537480 # ITB inst hits +system.cpu0.itb.inst_misses 86000 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29668 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 226388 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 230623480 # ITB inst accesses +system.cpu0.itb.hits 230537480 # DTB hits +system.cpu0.itb.misses 86000 # DTB misses +system.cpu0.itb.accesses 230623480 # DTB accesses +system.cpu0.numCycles 786965482 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.fetch.icacheStallCycles 90387711 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 647691070 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 146587108 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 87912986 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 665690431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15471710 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1846295 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 143165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6476529 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 786234 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 320116 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 230311190 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1742140 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 773386336 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.980975 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.219702 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 409957196 53.01% 53.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 140998975 18.23% 71.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 49617031 6.42% 77.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 172813134 22.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 773386336 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.186269 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.823023 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 108593313 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 378356513 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 240969730 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 39977542 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5489238 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 21224089 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2292433 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 668689408 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 25030555 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5489238 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 146312922 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 57383456 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 250430469 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 242520551 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 71249700 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 650266707 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6336504 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 9477139 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 381865 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 840506 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 33815177 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 14484 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 619540415 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1001273329 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 768127423 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 806411 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 558016180 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 61524234 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16309942 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14158531 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 81487680 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 106551444 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90697387 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9851628 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8566406 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 626998472 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16435650 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 631073777 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2910747 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 54340762 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 37568320 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 303534 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 773386336 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.815988 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.066561 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 429333552 55.51% 55.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 143479671 18.55% 74.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 122471651 15.84% 89.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 69760577 9.02% 98.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8335355 1.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5527 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 773386336 # Number of insts issued each cycle +system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 65856729 45.73% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 73447 0.05% 45.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 22232 0.02% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 47 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 37876967 26.30% 72.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 40192311 27.91% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 431505224 68.38% 68.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1606072 0.25% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 80666 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 12 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 46680 0.01% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 109370672 17.33% 85.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88464450 14.02% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::total 631073777 # Type of FU issued +system.cpu0.iq.rate 0.801908 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 144021733 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228217 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2181305203 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 697468177 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 613392938 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1161167 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 463347 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 426941 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 774373560 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 721950 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2923759 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.squashedLoads 13150556 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17424 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 157648 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6172607 # Number of stores squashed +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.rescheduledLoads 2931375 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4759724 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewSquashCycles 5489238 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8266633 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 4717216 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 643560247 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 106551444 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90697387 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13867290 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 61805 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4582618 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 157648 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2155844 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3101202 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5257046 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 622852330 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 106129153 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7624905 # Number of squashed instructions skipped in execute +system.cpu0.iew.exec_swp 0 # number of swp insts executed +system.cpu0.iew.exec_nop 126125 # number of nop insts executed +system.cpu0.iew.exec_refs 193235409 # number of memory reference insts executed +system.cpu0.iew.exec_branches 117777762 # Number of branches executed +system.cpu0.iew.exec_stores 87106256 # Number of stores executed +system.cpu0.iew.exec_rate 0.791461 # Inst execution rate +system.cpu0.iew.wb_sent 614619625 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 613819879 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 298670143 # num instructions producing a value +system.cpu0.iew.wb_consumers 489758313 # num instructions consuming a value +system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.wb_rate 0.779983 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609832 # average fanout of values written-back +system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.commit.commitSquashedInsts 50622338 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16132116 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4918284 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 763797135 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.766621 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.569865 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 508551807 66.58% 66.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 131505056 17.22% 83.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 56862924 7.44% 91.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18814885 2.46% 93.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13980697 1.83% 95.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9342143 1.22% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6309382 0.83% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 4063980 0.53% 98.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14366261 1.88% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 763797135 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 498729441 # Number of instructions committed +system.cpu0.commit.committedOps 585543302 # Number of ops (including micro ops) committed +system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.refs 177925668 # Number of memory references committed +system.cpu0.commit.loads 93400888 # Number of loads committed +system.cpu0.commit.membars 4075726 # Number of memory barriers committed +system.cpu0.commit.branches 111746625 # Number of branches committed +system.cpu0.commit.fp_insts 417930 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 537600399 # Number of committed integer instructions. +system.cpu0.commit.function_calls 15117239 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 406177320 69.37% 69.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1336444 0.23% 69.60% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 63141 0.01% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 40729 0.01% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 93400888 15.95% 85.56% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84524780 14.44% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 585543302 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14366261 # number cycles where commit BW limit reached +system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.rob.rob_reads 1380974813 # The number of ROB reads +system.cpu0.rob.rob_writes 1281884282 # The number of ROB writes +system.cpu0.timesIdled 846185 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 13579146 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93972383800 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 498729441 # Number of Instructions Simulated +system.cpu0.committedOps 585543302 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.577941 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.577941 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.633737 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.633737 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 735405419 # number of integer regfile reads +system.cpu0.int_regfile_writes 437369435 # number of integer regfile writes +system.cpu0.fp_regfile_reads 697220 # number of floating regfile reads +system.cpu0.fp_regfile_writes 340900 # number of floating regfile writes +system.cpu0.cc_regfile_reads 134840784 # number of cc regfile reads +system.cpu0.cc_regfile_writes 135500502 # number of cc regfile writes +system.cpu0.misc_regfile_reads 3071585466 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16203449 # number of misc regfile writes +system.cpu0.toL2Bus.trans_dist::ReadReq 15637085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 12009481 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33046 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33046 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3548344 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 4365503 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1683195 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 1040668 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 461767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 386684 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 535373 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1436156 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1297014 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 13051451 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18246800 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419537 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1341455 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 33059243 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 416613216 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 664873226 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1541384 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4934904 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1087962730 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 9586812 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 27467610 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.337349 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.472805 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 18201451 66.27% 66.27% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 9266159 33.73% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 27467610 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 13754094390 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 197445482 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 9792438220 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 9396795912 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 228193109 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 726243001 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.icache.tags.replacements 6503720 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.971418 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 223511778 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6504232 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.364054 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8400074750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.971418 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999944 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 184 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 467078613 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 467078613 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 223511778 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 223511778 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 223511778 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 223511778 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 223511778 # number of overall hits +system.cpu0.icache.overall_hits::total 223511778 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6775226 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6775226 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6775226 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6775226 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6775226 # number of overall misses +system.cpu0.icache.overall_misses::total 6775226 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 58809305620 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 58809305620 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 58809305620 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 58809305620 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 58809305620 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 58809305620 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 230287004 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 230287004 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 230287004 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 230287004 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 230287004 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 230287004 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029421 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029421 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029421 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029421 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029421 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029421 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8680.050764 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8680.050764 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8680.050764 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8680.050764 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8680.050764 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8680.050764 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4711788 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 167 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 607280 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.758839 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 167 # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 270621 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 270621 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 270621 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 270621 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 270621 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 270621 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6504605 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6504605 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6504605 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6504605 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6504605 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6504605 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 47647231055 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 47647231055 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 47647231055 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 47647231055 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 47647231055 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 47647231055 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699559498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699559498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028246 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028246 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028246 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7325.153650 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7325.153650 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7325.153650 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 59245032 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2351166 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 52469358 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1249562 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 200789 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2974157 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4925432 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.tags.replacements 3747306 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16276.136731 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 13593053 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 3763332 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.611973 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 6997709500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4266.822439 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 59.073583 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 61.998615 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 875.814301 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3003.067946 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8009.359846 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.260426 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003606 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003784 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.053455 # 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ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.118006 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.524845 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.524845 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.818029 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.818029 # mshr miss rate for SCUpgradeReq accesses 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0.026536 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066288 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.028093 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.251089 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.354862 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 30124.578689 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29676.550699 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 35601.440437 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.943421 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17421.943421 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13837.367604 # average SCUpgradeReq mshr miss latency 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uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 6421778 # number of replacements +system.cpu0.dcache.tags.tagsinuse 503.783649 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 165065902 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6422290 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.702032 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.783649 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983952 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.983952 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 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demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 250277240285 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 250277240285 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 250277240285 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 93611830 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 93611830 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81283078 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81283078 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 970949 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 970949 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1040668 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1040668 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2243371 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2243371 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2201427 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2201427 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 174894908 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 174894908 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 175865857 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 175865857 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078321 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.078321 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.094839 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.094839 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.762231 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.762231 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131400 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131400 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097254 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097254 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085998 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.085998 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089731 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.089731 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15694.567485 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15694.567485 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17539.488938 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17539.488938 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14327.343814 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14327.343814 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21181.002233 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21181.002233 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16640.152162 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16640.152162 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15859.755849 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15859.755849 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 17082084 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 19003690 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 950552 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 748671 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.970699 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 25.383232 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 1040668 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 3548346 # number of writebacks +system.cpu0.dcache.writebacks::total 3548346 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3808172 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3808172 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6155071 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6155071 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 150940 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 150940 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9963243 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9963243 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9963243 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9963243 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3523593 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3523593 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1532184 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1532184 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 733570 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 733570 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 143839 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 143839 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 214091 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 214091 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5055777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5055777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5789347 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5789347 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48006705459 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48006705459 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27570008615 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27570008615 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18661725527 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18661725527 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 57519686561 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 57519686561 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1764532424 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1764532424 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4095364784 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4095364784 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4027500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4027500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75576714074 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 75576714074 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94238439601 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 94238439601 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5807383412 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5807383412 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5600359921 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5600359921 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11407743333 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11407743333 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037640 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037640 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018850 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018850 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.755519 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755519 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064117 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064117 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097251 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097251 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028908 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028908 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032919 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032919 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13624.361684 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13624.361684 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17993.928024 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17993.928024 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25439.597485 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25439.597485 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12267.413038 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12267.413038 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19129.084287 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19129.084287 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14948.585366 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14948.585366 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16277.904849 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16277.904849 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.branchPred.lookups 126883394 # Number of BP lookups +system.cpu1.branchPred.condPredicted 85166335 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6223569 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 90014178 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 58475937 # Number of BTB hits +system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.branchPred.BTBHitPct 64.963029 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16774062 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 171946 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 93423769 # DTB read hits +system.cpu1.dtb.read_misses 385141 # DTB read misses +system.cpu1.dtb.write_hits 77506370 # DTB write hits +system.cpu1.dtb.write_misses 166753 # DTB write misses +system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 38053 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 411 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6413 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 42956 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 93808910 # DTB read accesses +system.cpu1.dtb.write_accesses 77673123 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 170930139 # DTB hits +system.cpu1.dtb.misses 551894 # DTB misses +system.cpu1.dtb.accesses 171482033 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 200532583 # ITB inst hits +system.cpu1.itb.inst_misses 85074 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26827 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 221691 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 200617657 # ITB inst accesses +system.cpu1.itb.hits 200532583 # DTB hits +system.cpu1.itb.misses 85074 # DTB misses +system.cpu1.itb.accesses 200617657 # DTB accesses +system.cpu1.numCycles 671498045 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.fetch.icacheStallCycles 76057268 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 563958948 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 126883394 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 75249999 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 570112426 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13401984 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1796129 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 140886 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6366912 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 711415 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 284551 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 200289545 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1511940 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28568 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 662170579 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.001134 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.225253 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 344731960 52.06% 52.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 123888404 18.71% 70.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 41617512 6.29% 77.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 151932703 22.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 662170579 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.188956 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.839852 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 93652150 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 319101856 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 208055943 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 36600277 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4760353 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17735520 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1981049 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 585316730 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21686226 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4760353 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 127273008 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 44978505 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 215016897 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 210494675 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 59647141 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 569572737 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5483527 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8310630 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 236317 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 296206 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 25698514 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 13591 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 543172602 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 884661173 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 673765883 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 933137 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 489609146 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 53563450 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15680851 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13859127 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 73666324 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 93680638 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 80687792 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8658535 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7660349 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 547737456 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15869030 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 553093233 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2542275 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 47705580 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 32628806 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 263861 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 662170579 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.835273 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.067651 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 358036858 54.07% 54.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 130663379 19.73% 73.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 105371554 15.91% 89.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 60712008 9.17% 98.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7383178 1.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3602 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 662170579 # Number of insts issued each cycle +system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 55137578 43.73% 43.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 43337 0.03% 43.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 11462 0.01% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 21 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 33948572 26.92% 70.70% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 36949037 29.30% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 376818141 68.13% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1181294 0.21% 68.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 70304 0.01% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 78003 0.01% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.37% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 96248927 17.40% 85.77% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 78696516 14.23% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::total 553093233 # Type of FU issued +system.cpu1.iq.rate 0.823671 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 126090007 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227972 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1895671563 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 610922154 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 537423673 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1317762 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 530370 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 489519 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 678367586 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 815653 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2464833 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.squashedLoads 11666973 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 15967 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 141534 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5620813 # Number of stores squashed +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.rescheduledLoads 2485085 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4066782 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewSquashCycles 4760353 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6088373 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2643428 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 563729528 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 93680638 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 80687792 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13644540 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 61293 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2520664 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 141534 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1916152 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2651693 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4567845 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 545961284 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 93419699 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6590982 # Number of squashed instructions skipped in execute +system.cpu1.iew.exec_swp 0 # number of swp insts executed +system.cpu1.iew.exec_nop 123042 # number of nop insts executed +system.cpu1.iew.exec_refs 170926883 # number of memory reference insts executed +system.cpu1.iew.exec_branches 102016204 # Number of branches executed +system.cpu1.iew.exec_stores 77507184 # Number of stores executed +system.cpu1.iew.exec_rate 0.813050 # Inst execution rate +system.cpu1.iew.wb_sent 538581721 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 537913192 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 259879872 # num instructions producing a value +system.cpu1.iew.wb_consumers 425846883 # num instructions consuming a value +system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.wb_rate 0.801064 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610266 # average fanout of values written-back +system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.commit.commitSquashedInsts 44555907 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15605169 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4282930 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 653744993 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.784392 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.576833 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 427404365 65.38% 65.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 119117281 18.22% 83.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 49133324 7.52% 91.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16524443 2.53% 93.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11998035 1.84% 95.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8093886 1.24% 96.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5471403 0.84% 97.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3473274 0.53% 98.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12528982 1.92% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::total 653744993 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 435068948 # Number of instructions committed +system.cpu1.commit.committedOps 512792020 # Number of ops (including micro ops) committed +system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu1.commit.refs 157080643 # Number of memory references committed +system.cpu1.commit.loads 82013664 # Number of loads committed +system.cpu1.commit.membars 3580423 # Number of memory barriers committed +system.cpu1.commit.branches 96770677 # Number of branches committed +system.cpu1.commit.fp_insts 477739 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 470356347 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12430117 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 354618766 69.15% 69.15% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 966577 0.19% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 56200 0.01% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 69792 0.01% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 82013664 15.99% 85.36% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 75066979 14.64% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 512792020 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12528982 # number cycles where commit BW limit reached +system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu1.rob.rob_reads 1194813735 # The number of ROB reads +system.cpu1.rob.rob_writes 1123082959 # The number of ROB writes +system.cpu1.timesIdled 724798 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 9327466 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94087851225 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 435068948 # Number of Instructions Simulated +system.cpu1.committedOps 512792020 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.543429 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.543429 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.647908 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.647908 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 645605353 # number of integer regfile reads +system.cpu1.int_regfile_writes 381721004 # number of integer regfile writes +system.cpu1.fp_regfile_reads 775313 # number of floating regfile reads +system.cpu1.fp_regfile_writes 445860 # number of floating regfile writes +system.cpu1.cc_regfile_reads 118711593 # number of cc regfile reads +system.cpu1.cc_regfile_writes 119446570 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2680324006 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15740060 # number of misc regfile writes +system.cpu1.toL2Bus.trans_dist::ReadReq 14195138 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10319504 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5540 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5540 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3043633 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 4072942 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1683351 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 535551 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 440112 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 381311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 495883 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1326326 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1162072 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11031290 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15072798 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 408972 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1223990 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27737050 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352998000 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 552975725 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1478304 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4387432 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 911839461 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 10107713 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 25138246 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.388398 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.487386 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 15374612 61.16% 61.16% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 9763634 38.84% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 25138246 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 11278575992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 196968741 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 8281966249 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 7967439656 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 225433169 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 677266087 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.icache.tags.replacements 5515063 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.927395 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 194540892 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5515575 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 35.271190 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8512592975000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.927395 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980327 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980327 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 406089111 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 406089111 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 194540892 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 194540892 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 194540892 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 194540892 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 194540892 # number of overall hits +system.cpu1.icache.overall_hits::total 194540892 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5745874 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5745874 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5745874 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5745874 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5745874 # number of overall misses +system.cpu1.icache.overall_misses::total 5745874 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 49972720911 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 49972720911 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 49972720911 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 49972720911 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 49972720911 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 49972720911 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 200286766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 200286766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 200286766 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 200286766 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 200286766 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 200286766 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028688 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.028688 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028688 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.028688 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028688 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.028688 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8697.148756 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8697.148756 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8697.148756 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8697.148756 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 4058036 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 525950 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.715631 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 230295 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 230295 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 230295 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 230295 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 230295 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 230295 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5515579 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5515579 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5515579 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5515579 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5515579 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5515579 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 40507461081 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 40507461081 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 40507461081 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 40507461081 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 40507461081 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 40507461081 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6176248 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6176248 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6176248 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6176248 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027538 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027538 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027538 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7344.190171 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7344.190171 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7344.190171 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 50505684 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2064047 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 44628493 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 907161 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 133845 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2772138 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4283124 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.tags.replacements 3436745 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13730.844001 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 11600969 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 3452900 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 3.359776 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9794240275500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4681.996556 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.505551 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 81.585621 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 599.676687 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2582.188700 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5714.890886 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.285766 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004303 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004980 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036601 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.157604 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.348809 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.838064 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9001 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7069 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 110 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 838 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3805 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2947 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1301 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 786 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3475 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2116 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 647 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.549377 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.431458 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 248779915 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 248779915 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 532626 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 172045 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5284751 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2703668 # number of ReadReq hits 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+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028800 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.068143 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.030928 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.286050 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.127912 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.587027 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.587027 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.837195 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.837195 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.196584 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.196584 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028800 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.068143 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030928 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.265165 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135000 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028800 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068143 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030928 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.265165 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.382456 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26775.298889 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26588.275709 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 32053.702935 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17563.550939 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17563.550939 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13637.442900 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13637.442900 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183352.941176 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183352.941176 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36902.824973 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36902.824973 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28138.464180 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30671.695797 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.tags.replacements 5270583 # number of replacements +system.cpu1.dcache.tags.tagsinuse 418.735038 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 145844611 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5271093 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.668761 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8472891797000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 418.735038 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.817842 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.817842 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 326008687 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 326008687 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 76031229 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76031229 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 65289331 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 65289331 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171825 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 171825 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 535551 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 535551 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1744878 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1744878 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734724 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1734724 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 141320560 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 141320560 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 141492385 # number of overall hits +system.cpu1.dcache.overall_hits::total 141492385 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6360074 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6360074 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7315323 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7315323 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 690767 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 690767 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 239985 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 239985 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 206300 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 206300 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13675397 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13675397 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 14366164 # number of overall misses +system.cpu1.dcache.overall_misses::total 14366164 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96502365280 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 96502365280 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 122289774326 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 122289774326 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3384586861 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3384586861 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4391846948 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4391846948 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4067000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4067000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 218792139606 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 218792139606 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 218792139606 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 218792139606 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82391303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82391303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 72604654 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 72604654 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 862592 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 862592 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 535551 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 535551 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1984863 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1984863 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1941024 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1941024 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 154995957 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 154995957 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 155858549 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 155858549 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077194 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.077194 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.100756 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.100756 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.800804 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.800804 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120908 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120908 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106284 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088231 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.088231 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092174 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.092174 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15173.151331 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15173.151331 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16716.934348 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16716.934348 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14103.326712 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14103.326712 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21288.642501 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21288.642501 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15998.960733 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15998.960733 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15229.684111 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15229.684111 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 8615413 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 17976416 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 462301 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 741969 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.635938 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 24.227988 # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 535551 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 3043634 # number of writebacks +system.cpu1.dcache.writebacks::total 3043634 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3366977 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3366977 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5934775 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5934775 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 123858 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 123858 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9301752 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9301752 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9301752 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9301752 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2993097 # number of ReadReq MSHR misses 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4362891 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5053582 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5053582 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38940153004 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38940153004 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23265516814 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23265516814 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16955467787 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16955467787 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 29882890933 # number of WriteInvalidateReq MSHR miss cycles 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was blocked +system.iocache.fast_writes 106728 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8889 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8929 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 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miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 101918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170934.708179 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 170648.624356 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 14096 # number of quiesce instructions executed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 4921 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini new file mode 100644 index 000000000..53191049f --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini @@ -0,0 +1,1554 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.realview.nvmem system.physmem system.realview.vram +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +LFSTSize=1024 +LQEntries=16 +LSQCheckLoads=true +LSQDepCheckShift=0 +SQEntries=16 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=2 +decodeWidth=3 +dispatchWidth=6 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=16 +fetchQueueSize=32 +fetchToDecodeDelay=3 +fetchTrapLatency=1 +fetchWidth=3 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=32 +numPhysCCRegs=640 +numPhysFloatRegs=192 +numPhysIntRegs=128 +numROBEntries=40 +numRobs=1 +numThreads=1 +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=1 +renameToROBDelay=1 +renameWidth=3 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload= +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=2048 +BTBTagSize=18 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=bi-mode + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 opList2 +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +issueLat=12 +opClass=IntDiv +opLat=12 + +[system.cpu.fuPool.FUList1.opList2] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IprAccess +opLat=3 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList + +[system.cpu.fuPool.FUList2.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList + +[system.cpu.fuPool.FUList3.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemWrite +opLat=2 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 + +[system.cpu.fuPool.FUList4.opList00] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAdd +opLat=4 + +[system.cpu.fuPool.FUList4.opList01] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAddAcc +opLat=4 + +[system.cpu.fuPool.FUList4.opList02] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAlu +opLat=4 + +[system.cpu.fuPool.FUList4.opList03] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCmp +opLat=4 + +[system.cpu.fuPool.FUList4.opList04] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCvt +opLat=3 + +[system.cpu.fuPool.FUList4.opList05] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMisc +opLat=3 + +[system.cpu.fuPool.FUList4.opList06] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMult +opLat=5 + +[system.cpu.fuPool.FUList4.opList07] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMultAcc +opLat=5 + +[system.cpu.fuPool.FUList4.opList08] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShift +opLat=3 + +[system.cpu.fuPool.FUList4.opList09] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShiftAcc +opLat=3 + +[system.cpu.fuPool.FUList4.opList10] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdSqrt +opLat=9 + +[system.cpu.fuPool.FUList4.opList11] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAdd +opLat=5 + +[system.cpu.fuPool.FUList4.opList12] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAlu +opLat=5 + +[system.cpu.fuPool.FUList4.opList13] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCmp +opLat=3 + +[system.cpu.fuPool.FUList4.opList14] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCvt +opLat=3 + +[system.cpu.fuPool.FUList4.opList15] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatDiv +opLat=3 + +[system.cpu.fuPool.FUList4.opList16] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMisc +opLat=3 + +[system.cpu.fuPool.FUList4.opList17] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMult +opLat=3 + +[system.cpu.fuPool.FUList4.opList18] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList4.opList19] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatSqrt +opLat=9 + +[system.cpu.fuPool.FUList4.opList20] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatAdd +opLat=5 + +[system.cpu.fuPool.FUList4.opList21] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCmp +opLat=5 + +[system.cpu.fuPool.FUList4.opList22] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCvt +opLat=5 + +[system.cpu.fuPool.FUList4.opList23] +type=OpDesc +eventq_index=0 +issueLat=9 +opClass=FloatDiv +opLat=9 + +[system.cpu.fuPool.FUList4.opList24] +type=OpDesc +eventq_index=0 +issueLat=33 +opClass=FloatSqrt +opLat=33 + +[system.cpu.fuPool.FUList4.opList25] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simerr new file mode 100644 index 000000000..744db2c76 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simerr @@ -0,0 +1,11 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout new file mode 100644 index 000000000..ade67f17c --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout @@ -0,0 +1,16 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 10:37:59 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 + 0: system.cpu.isa: ISA system set to: 0x43dfb00 0x43dfb00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80080000 +info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 51557114994500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt new file mode 100644 index 000000000..d5d5bafb9 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -0,0 +1,1680 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 51.557115 # Number of seconds simulated +sim_ticks 51557114994500 # Number of ticks simulated +final_tick 51557114994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 111994 # Simulator instruction rate (inst/s) +host_op_rate 131638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5181426993 # Simulator tick rate (ticks/s) +host_mem_usage 668412 # Number of bytes of host memory used +host_seconds 9950.37 # Real time elapsed on the host +sim_insts 1114380469 # Number of instructions simulated +sim_ops 1309844804 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.ide 437568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1002304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 1237760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6145632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 128560840 # Number of bytes read from this memory +system.physmem.bytes_read::total 137384104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6145632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6145632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 102180288 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 102783780 # Number of bytes written to this memory +system.physmem.bytes_written::total 211790564 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 6837 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 15661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 19340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 111978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2008776 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2162592 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1596567 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 1608248 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3311479 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 8487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 19441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 24008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 119200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2493562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2664697 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 119200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 119200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1981885 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 132406 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1993591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4107882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1981885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 140894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 19441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 24008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 119200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4487152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6772580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2162592 # Number of read requests accepted +system.physmem.writeReqs 3311479 # Number of write requests accepted +system.physmem.readBursts 2162592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 3311479 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 138204608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 201280 # Total number of bytes read from write queue +system.physmem.bytesWritten 207618304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 137384104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 211790564 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 3145 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 67428 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 48470 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 140382 # Per bank write bursts +system.physmem.perBankRdBursts::1 139333 # Per bank write bursts +system.physmem.perBankRdBursts::2 140658 # Per bank write bursts +system.physmem.perBankRdBursts::3 133921 # Per bank write bursts +system.physmem.perBankRdBursts::4 130324 # Per bank write bursts +system.physmem.perBankRdBursts::5 134612 # Per bank write bursts +system.physmem.perBankRdBursts::6 126217 # Per bank write bursts +system.physmem.perBankRdBursts::7 133097 # Per bank write bursts +system.physmem.perBankRdBursts::8 129592 # Per bank write bursts +system.physmem.perBankRdBursts::9 157619 # Per bank write bursts +system.physmem.perBankRdBursts::10 133394 # Per bank write bursts +system.physmem.perBankRdBursts::11 133867 # Per bank write bursts +system.physmem.perBankRdBursts::12 132326 # Per bank write bursts +system.physmem.perBankRdBursts::13 132284 # Per bank write bursts +system.physmem.perBankRdBursts::14 133117 # Per bank write bursts +system.physmem.perBankRdBursts::15 128704 # Per bank write bursts +system.physmem.perBankWrBursts::0 201659 # Per bank write bursts +system.physmem.perBankWrBursts::1 203665 # Per bank write bursts +system.physmem.perBankWrBursts::2 231223 # Per bank write bursts +system.physmem.perBankWrBursts::3 188549 # Per bank write bursts +system.physmem.perBankWrBursts::4 224931 # Per bank write bursts +system.physmem.perBankWrBursts::5 188791 # Per bank write bursts +system.physmem.perBankWrBursts::6 176287 # Per bank write bursts +system.physmem.perBankWrBursts::7 226882 # Per bank write bursts +system.physmem.perBankWrBursts::8 203233 # Per bank write bursts +system.physmem.perBankWrBursts::9 233524 # Per bank write bursts +system.physmem.perBankWrBursts::10 253232 # Per bank write bursts +system.physmem.perBankWrBursts::11 198347 # Per bank write bursts +system.physmem.perBankWrBursts::12 181957 # Per bank write bursts +system.physmem.perBankWrBursts::13 175879 # Per bank write bursts +system.physmem.perBankWrBursts::14 180282 # Per bank write bursts +system.physmem.perBankWrBursts::15 175595 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 190 # Number of times write queue was full causing retry +system.physmem.totGap 51557113761500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 13 # Read request sizes (log2) +system.physmem.readPktSize::4 21272 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 2141307 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 1 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 3308906 # Write request sizes (log2) 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activation +system.physmem.bytesPerActivate::640-767 26689 2.58% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21988 2.12% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25501 2.46% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 158207 15.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1034839 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 135592 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.925969 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 128.724301 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 135587 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-43007 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 135592 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 135592 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.924981 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.930688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.164557 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 101303 74.71% 74.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 7599 5.60% 80.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 12845 9.47% 89.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 3908 2.88% 92.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 2324 1.71% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 925 0.68% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 2932 2.16% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1250 0.92% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 889 0.66% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 249 0.18% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 327 0.24% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 193 0.14% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 473 0.35% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 16 0.01% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 22 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 28 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 17 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 31 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 89 0.07% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 56 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 42 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 15 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 15 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 6 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 5 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 5 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 135592 # Writes before turning the bus around for reads +system.physmem.totQLat 43990891280 # Total ticks spent queuing +system.physmem.totMemAccLat 84480522530 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10797235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20371.37 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 39121.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing +system.physmem.readRowHits 1747291 # Number of row buffer hits during reads +system.physmem.writeRowHits 2621349 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes +system.physmem.avgGap 9418422.55 # Average gap between requests +system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49290195125250 # Time in different power states +system.physmem.memoryStateTime::REF 1721605340000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 545313634750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3951453240 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3871929600 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2156050875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2112660000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 8412588600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 8431020000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 10640075760 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 10381277520 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3367460045040 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3367460045040 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1383947967870 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1368871606665 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29720278968750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29733503847000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34496847150135 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34494632385825 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.099654 # Core power per rank (mW) +system.physmem.averagePower::1 669.056696 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 657217 # Transaction distribution +system.membus.trans_dist::ReadResp 657217 # Transaction distribution +system.membus.trans_dist::WriteReq 33865 # Transaction distribution +system.membus.trans_dist::WriteResp 33865 # Transaction distribution +system.membus.trans_dist::Writeback 1596567 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1712339 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1712339 # Transaction distribution +system.membus.trans_dist::UpgradeReq 48473 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 48476 # Transaction distribution +system.membus.trans_dist::ReadExReq 1541174 # Transaction distribution +system.membus.trans_dist::ReadExResp 1541174 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9221519 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9351669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229018 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 229018 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9580687 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341910604 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 342081160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7264064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 349345224 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2022 # Total snoops (count) +system.membus.snoop_fanout::samples 5500895 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 5500895 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 5500895 # Request fanout histogram +system.membus.reqLayer0.occupancy 109641999 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5450500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 32462148974 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 21571101815 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186532342 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1669 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 40379 # Transaction distribution +system.iobus.trans_dist::ReadResp 40379 # Transaction distribution +system.iobus.trans_dist::WriteReq 136716 # Transaction distribution +system.iobus.trans_dist::WriteResp 136733 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 17 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492654 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 981079506 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179002658 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 291488483 # Number of BP lookups +system.cpu.branchPred.condPredicted 200150149 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13608043 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 209143322 # Number of BTB lookups +system.cpu.branchPred.BTBHits 138326751 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 66.139693 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37688944 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 403819 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 220000246 # DTB read hits +system.cpu.dtb.read_misses 1007031 # DTB read misses +system.cpu.dtb.write_hits 193886106 # DTB write hits +system.cpu.dtb.write_misses 416122 # DTB write misses +system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 63968 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 89690 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 112 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15179 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 87251 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 221007277 # DTB read accesses +system.cpu.dtb.write_accesses 194302228 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 413886352 # DTB hits +system.cpu.dtb.misses 1423153 # DTB misses +system.cpu.dtb.accesses 415309505 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 465588468 # ITB inst hits +system.cpu.itb.inst_misses 176797 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 63968 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 63536 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 462381 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 465765265 # ITB inst accesses +system.cpu.itb.hits 465588468 # DTB hits +system.cpu.itb.misses 176797 # DTB misses +system.cpu.itb.accesses 465765265 # DTB accesses +system.cpu.numCycles 2146849645 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 791511347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1301628389 # Number of instructions fetch has processed +system.cpu.fetch.Branches 291488483 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 176015695 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1268750537 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29307286 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4254748 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 12217982 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1219824 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 381 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 465107423 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6746831 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 53918 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2092636388 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.729302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.142136 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1367675983 65.36% 65.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 280886167 13.42% 78.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 86945610 4.15% 82.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 357128628 17.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 2092636388 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.135775 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.606297 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 614820490 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 852644163 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 531180111 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 83391963 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10599661 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41490545 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4112846 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1415541998 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32718079 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10599661 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 678805488 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 83662136 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 556428904 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 549849830 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 213290369 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1391734034 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 7977079 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7435136 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 893230 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1023922 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 127479585 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 25199 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1342075875 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2217645602 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1652184740 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1639045 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1263873564 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78202308 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44203192 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39719264 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 172796539 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 223511224 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 198396121 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12647992 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11061331 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1338396177 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 44508712 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1370133902 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4153047 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65240654 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41320787 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 373617 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2092636388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.654741 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.915536 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1237717942 59.15% 59.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 455529583 21.77% 80.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 292996726 14.00% 94.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96986296 4.63% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9377226 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28615 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2092636388 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 74528454 34.28% 34.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90672 0.04% 34.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26772 0.01% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 287 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 58830485 27.06% 61.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83911289 38.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 945793660 69.03% 69.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2946266 0.22% 69.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 129775 0.01% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 114397 0.01% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 224851656 16.41% 85.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 196298100 14.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1370133902 # Type of FU issued +system.cpu.iq.rate 0.638207 # Inst issue rate +system.cpu.iq.fu_busy_cnt 217387959 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.158662 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5052021388 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1447405501 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1347303683 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2423809 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 923681 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 885699 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1585997449 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1524411 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5766333 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 16996131 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24128 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 185382 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8259714 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 3623609 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3385962 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 10599661 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11961718 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7304667 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1383179145 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 223511224 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 198396121 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39177517 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 185228 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6936317 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 185382 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4274350 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5730421 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10004771 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1356817685 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 220004444 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11924579 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 274256 # number of nop insts executed +system.cpu.iew.exec_refs 413901554 # number of memory reference insts executed +system.cpu.iew.exec_branches 257473473 # Number of branches executed +system.cpu.iew.exec_stores 193897110 # Number of stores executed +system.cpu.iew.exec_rate 0.632004 # Inst execution rate +system.cpu.iew.wb_sent 1349182874 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1348189382 # cumulative count of insts written-back +system.cpu.iew.wb_producers 579023420 # num instructions producing a value +system.cpu.iew.wb_consumers 949767765 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.627985 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.609647 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitSquashedInsts 62443917 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 44135095 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9554061 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2078483160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.630193 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.269789 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1396354428 67.18% 67.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 397736022 19.14% 86.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 152396085 7.33% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44287772 2.13% 95.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35996912 1.73% 97.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18656723 0.90% 98.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10905184 0.52% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5449343 0.26% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16700691 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 2078483160 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1114380469 # Number of instructions committed +system.cpu.commit.committedOps 1309844804 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 396651499 # Number of memory references committed +system.cpu.commit.loads 206515092 # Number of loads committed +system.cpu.commit.membars 9189565 # Number of memory barriers committed +system.cpu.commit.branches 249089949 # Number of branches committed +system.cpu.commit.fp_insts 873640 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1196978104 # Number of committed integer instructions. +system.cpu.commit.function_calls 31078874 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 910428363 69.51% 69.51% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2554988 0.20% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 104143 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 105769 0.01% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.72% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 206515092 15.77% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 190136407 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1309844804 # Class of committed instruction +system.cpu.commit.bw_lim_events 16700691 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 3424556806 # The number of ROB reads +system.cpu.rob.rob_writes 2758622493 # The number of ROB writes +system.cpu.timesIdled 9031521 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 54213257 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100967380384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1114380469 # Number of Instructions Simulated +system.cpu.committedOps 1309844804 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.926496 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.926496 # CPI: Total CPI of All Threads +system.cpu.ipc 0.519077 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.519077 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1611998606 # number of integer regfile reads +system.cpu.int_regfile_writes 948639021 # number of integer regfile writes +system.cpu.fp_regfile_reads 1420015 # number of floating regfile reads +system.cpu.fp_regfile_writes 765124 # number of floating regfile writes +system.cpu.cc_regfile_reads 315259155 # number of cc regfile reads +system.cpu.cc_regfile_writes 316098925 # number of cc regfile writes +system.cpu.misc_regfile_reads 6952427793 # number of misc regfile reads +system.cpu.misc_regfile_writes 45059384 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 28539920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28531649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33865 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33865 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 9369509 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1712344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1605675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 61529 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 61535 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3074731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3074731 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33703094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37825776 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 810571 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3115869 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 75455310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1077469744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1502191576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2724416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10868120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2593253856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 644632 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 42703026 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.002705 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.051942 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 42587504 99.73% 99.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115522 0.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 42703026 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32333793873 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 871500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 25296093441 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 19876823538 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 472614279 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 1760067316 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.icache.tags.replacements 16829629 # number of replacements +system.cpu.icache.tags.tagsinuse 511.959617 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 447510611 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16830141 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.589831 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 12236526000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.959617 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 481916487 # Number of tag accesses +system.cpu.icache.tags.data_accesses 481916487 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 447510611 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 447510611 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 447510611 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 447510611 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 447510611 # number of overall hits +system.cpu.icache.overall_hits::total 447510611 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17575514 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17575514 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17575514 # number of demand (read+write) misses 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accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465086125 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465086125 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465086125 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465086125 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.037790 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.037790 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.037790 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.037790 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.037790 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.037790 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13173.280836 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13173.280836 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13173.280836 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13173.280836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13173.280836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13173.280836 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 11084 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 920 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 12.047826 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 745151 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 745151 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 745151 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 745151 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 745151 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 745151 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16830363 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16830363 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16830363 # number of demand (read+write) MSHR misses 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of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1413030250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1413030250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 1413030250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036188 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.036188 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.036188 # mshr miss rate for overall accesses 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blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7078.453286 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 22362.195885 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.523738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004689 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006864 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.108009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.341220 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.984520 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 496 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61774 # Occupied blocks per task id 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of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1532929 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 1342854 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 321211 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 16739434 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 10483585 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 28887084 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 1342854 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 321211 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 16739434 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 10483585 # number of overall hits +system.cpu.l2cache.overall_hits::total 28887084 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 15661 # number of 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mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were 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LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5398366 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5335209 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5335209 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 384045565 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 384045565 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 386583444 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 386583444 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063294 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.063294 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103541 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.103541 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816476 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.816476 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.101960 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.101960 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.082493 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082493 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087311 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087311 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16000.556505 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16000.556505 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53861.197196 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53861.197196 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15672.030311 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15672.030311 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38669.285110 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38669.285110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36295.361841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36295.361841 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 38319499 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2284719 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.772084 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 1605675 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 9369509 # number of writebacks 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(read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 10204619 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 12269939 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 12269939 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 102477717871 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 102477717871 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 148263766896 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 148263766896 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 31611668497 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 31611668497 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 59007365277 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 59007365277 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3751055249 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3751055249 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 104997 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 104997 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250741484767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 250741484767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 282353153264 # number of overall MSHR miss cycles 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miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031739 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031739 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.142272 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.142272 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47510.555303 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47510.555303 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15305.942177 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15305.942177 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency 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miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.tags.replacements 115458 # number of replacements +system.iocache.tags.tagsinuse 10.450727 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 13090278324000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.528058 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.922669 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220504 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432667 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653170 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 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106681 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106681 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000159 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000159 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149918.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218926.114036 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 218637.609379 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 147150 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 218601.812154 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 147150 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 218601.812154 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 53350 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.717668 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3623000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1470987863 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1474610863 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6546677301 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6546677301 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3806000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1470987863 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1474793863 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3806000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1470987863 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1474793863 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166911.138432 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 166622.696384 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 17164 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini new file mode 100644 index 000000000..810832a32 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini @@ -0,0 +1,1890 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=atomic +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=AtomicSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu +dtb=system.cpu0.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu0.tracer +width=1 +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[3] + +[system.cpu0.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu0.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] + +[system.cpu0.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu1] +type=TimingSimpleCPU +children=dstage2_mmu dtb isa istage2_mmu itb tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu +dtb=system.cpu1.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=Null +isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=true +system=system +tracer=system.cpu1.tracer +workload= + +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu1.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu1.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu1.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu1.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu2] +type=DerivO3CPU +children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu2.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu2.dstage2_mmu +dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu2.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=Null +isa=system.cpu2.isa +issueToExecuteDelay=1 +issueWidth=8 +istage2_mmu=system.cpu2.istage2_mmu +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=true +system=system +tracer=system.cpu2.tracer +trapLatency=13 +wbWidth=8 +workload= + +[system.cpu2.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu2.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb +tlb=system.cpu2.dtb + +[system.cpu2.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu2.dstage2_mmu.stage2_tlb.walker + +[system.cpu2.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu2.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu2.dtb.walker + +[system.cpu2.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu2.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 + +[system.cpu2.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu2.fuPool.FUList0.opList + +[system.cpu2.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu2.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 + +[system.cpu2.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu2.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu2.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 + +[system.cpu2.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu2.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu2.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu2.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +eventq_index=0 +opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 + +[system.cpu2.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu2.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu2.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu2.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +eventq_index=0 +opList=system.cpu2.fuPool.FUList4.opList + +[system.cpu2.fuPool.FUList4.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu2.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 + +[system.cpu2.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu2.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu2.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu2.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu2.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu2.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu2.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu2.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu2.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu2.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu2.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu2.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +eventq_index=0 +opList=system.cpu2.fuPool.FUList6.opList + +[system.cpu2.fuPool.FUList6.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu2.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +eventq_index=0 +opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 + +[system.cpu2.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu2.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu2.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu2.fuPool.FUList8.opList + +[system.cpu2.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu2.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu2.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu2.istage2_mmu.stage2_tlb +tlb=system.cpu2.itb + +[system.cpu2.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu2.istage2_mmu.stage2_tlb.walker + +[system.cpu2.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu2.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu2.itb.walker + +[system.cpu2.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu2.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.l2c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.l2c.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr new file mode 100644 index 000000000..5d5102fce --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr @@ -0,0 +1,687 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout new file mode 100644 index 000000000..622975a2a --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 11:58:52 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x563eb00 0x563eb00 + 0: system.cpu1.isa: ISA system set to: 0x563eb00 0x563eb00 + 0: system.cpu2.isa: ISA system set to: 0x563eb00 0x563eb00 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt new file mode 100644 index 000000000..dc447388d --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -0,0 +1,2373 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 51.274675 # Number of seconds simulated +sim_ticks 51274674635500 # Number of ticks simulated +final_tick 51274674635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 308954 # Simulator instruction rate (inst/s) +host_op_rate 363040 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18009090527 # Simulator tick rate (ticks/s) +host_mem_usage 661116 # Number of bytes of host memory used +host_seconds 2847.16 # Real time elapsed on the host +sim_insts 879639951 # Number of instructions simulated +sim_ops 1033631621 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.ide 391104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 245504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 412480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2683060 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 32648008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 82560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 137216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 615744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8957184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 211392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 332480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 2079744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 22931008 # Number of bytes read from this memory +system.physmem.bytes_read::total 71727484 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2683060 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 615744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 2079744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5378548 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 40940416 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 59033572 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 12553152 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 28525952 # Number of bytes written to this memory +system.physmem.bytes_written::total 147879588 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 6111 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 3836 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 6445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 82330 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 510138 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2144 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9621 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 139956 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 3303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 5195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 32496 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 358297 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1161162 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 639694 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 924651 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 196143 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 445718 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2312870 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 7628 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 4788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 8045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 52327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 636728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2676 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 12009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 174690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 4123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 6484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 40561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 447219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1398887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 52327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 12009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 40561 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 104897 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 798453 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 133136 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 1151320 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 244822 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 556336 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2884067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 798453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 140763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 8045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 52327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1788048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 12009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 419512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 4123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 6484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 40561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1003555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4282954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 556099 # Number of read requests accepted +system.physmem.writeReqs 996967 # Number of write requests accepted +system.physmem.readBursts 556099 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 996967 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 35500160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 90176 # Total number of bytes read from write queue +system.physmem.bytesWritten 61170112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 35590336 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 63805888 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1409 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 41184 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 18778 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 32891 # Per bank write bursts +system.physmem.perBankRdBursts::1 34922 # Per bank write bursts +system.physmem.perBankRdBursts::2 33947 # Per bank write bursts +system.physmem.perBankRdBursts::3 34663 # Per bank write bursts +system.physmem.perBankRdBursts::4 34185 # Per bank write bursts +system.physmem.perBankRdBursts::5 37826 # Per bank write bursts +system.physmem.perBankRdBursts::6 34767 # Per bank write bursts +system.physmem.perBankRdBursts::7 37084 # Per bank write bursts +system.physmem.perBankRdBursts::8 34802 # Per bank write bursts +system.physmem.perBankRdBursts::9 37662 # Per bank write bursts +system.physmem.perBankRdBursts::10 34607 # Per bank write bursts +system.physmem.perBankRdBursts::11 34013 # Per bank write bursts +system.physmem.perBankRdBursts::12 33947 # Per bank write bursts +system.physmem.perBankRdBursts::13 34396 # Per bank write bursts +system.physmem.perBankRdBursts::14 33124 # Per bank write bursts +system.physmem.perBankRdBursts::15 31854 # Per bank write bursts +system.physmem.perBankWrBursts::0 51538 # Per bank write bursts +system.physmem.perBankWrBursts::1 50883 # Per bank write bursts +system.physmem.perBankWrBursts::2 55756 # Per bank write bursts +system.physmem.perBankWrBursts::3 53410 # Per bank write bursts +system.physmem.perBankWrBursts::4 72819 # Per bank write bursts +system.physmem.perBankWrBursts::5 60009 # Per bank write bursts +system.physmem.perBankWrBursts::6 50793 # Per bank write bursts +system.physmem.perBankWrBursts::7 81282 # Per bank write bursts +system.physmem.perBankWrBursts::8 66815 # Per bank write bursts +system.physmem.perBankWrBursts::9 79578 # Per bank write bursts +system.physmem.perBankWrBursts::10 79171 # Per bank write bursts +system.physmem.perBankWrBursts::11 57649 # Per bank write bursts +system.physmem.perBankWrBursts::12 53518 # Per bank write bursts +system.physmem.perBankWrBursts::13 50714 # Per bank write bursts +system.physmem.perBankWrBursts::14 46719 # Per bank write bursts +system.physmem.perBankWrBursts::15 45129 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 45 # Number of times write queue was full causing retry +system.physmem.totGap 51273477930500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 556099 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 996967 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 389698 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 112133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 262 # What read 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an incoming req see +system.physmem.wrQLenPdf::57 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 114 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 313965 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.901429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.041097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.087880 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 132720 42.27% 42.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 70601 22.49% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 25843 8.23% 72.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12745 4.06% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9334 2.97% 80.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6247 1.99% 82.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5388 1.72% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6641 2.12% 85.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 44446 14.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 313965 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 40272 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.773590 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 142.393884 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 40271 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 40272 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 40272 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.733189 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.769670 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.088668 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 6 0.01% 0.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 2 0.00% 0.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.01% 0.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 68 0.17% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 21743 53.99% 54.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 7529 18.70% 72.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 844 2.10% 74.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 2202 5.47% 80.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3572 8.87% 89.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 961 2.39% 91.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 568 1.41% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 548 1.36% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 664 1.65% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 107 0.27% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 86 0.21% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 131 0.33% 96.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 645 1.60% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 191 0.47% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 148 0.37% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 110 0.27% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 71 0.18% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 17 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 8 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 9 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 40272 # Writes before turning the bus around for reads +system.physmem.totQLat 10784853014 # Total ticks spent queuing +system.physmem.totMemAccLat 21185290514 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2773450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19443.03 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 38193.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.69 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.69 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.24 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.01 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.80 # Average write queue length when enqueuing +system.physmem.readRowHits 423817 # Number of row buffer hits during reads +system.physmem.writeRowHits 772691 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.41 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.84 # Row buffer hit rate for writes +system.physmem.avgGap 33014358.65 # Average gap between requests +system.physmem.pageHitRate 79.21 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49344562776500 # Time in different power states +system.physmem.memoryStateTime::REF 1712173840000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 217931188500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 1214869320 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 1158706080 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 662875125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 632230500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 2186223000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 2140359000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 3087655200 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 3105818640 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3349012031040 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3349012031040 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1215657712530 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1211135236200 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29698434260250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29702401344750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34270255626465 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34269585726210 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.366215 # Core power per rank (mW) +system.physmem.averagePower::1 668.353150 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 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occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 6001066379 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 87450398 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.l2c.tags.replacements 829792 # number of replacements +system.l2c.tags.tagsinuse 64538.969055 # Cycle average of tags in use +system.l2c.tags.total_refs 28099922 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 891020 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 31.536803 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 13806560382000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35856.169681 # Average occupied blocks per requestor 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number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 884253000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1618942500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 2503195500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 835101000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1639869500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2474970500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1719354000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 3258812000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4978166000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.017627 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.042827 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004693 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.042141 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.008545 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.035732 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005614 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.049858 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.010018 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767997 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.750458 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.395159 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.314262 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.324337 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.157675 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.017627 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.042827 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004693 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.105625 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.008545 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.035732 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005614 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.110330 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.022675 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.017627 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.042827 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004693 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.105625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.008545 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.035732 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005614 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.110330 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.022675 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61167.004469 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61511.345597 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65805.130755 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70136.036427 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 67215.681681 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10023.131191 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10016.664704 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58833.836567 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75771.932576 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70773.308494 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61167.004469 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59652.855525 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65805.130755 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73786.183105 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69336.318663 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61167.004469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59652.855525 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65805.130755 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73786.183105 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69336.318663 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 18 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1669 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 22792948 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 22787515 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33772 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33772 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 6807908 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1600102 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1563939 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 46847 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46853 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2088945 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2088945 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29041280 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27958653 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 843900 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1753644 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 59597477 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 926729300 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1105413310 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3095064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6286720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2041524394 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 368391 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 33333670 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003466 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.058768 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 33218144 99.65% 99.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115526 0.35% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 33333670 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 25204206978 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 1129500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 35295410102 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 21026275011 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 267100118 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 646797339 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40334 # Transaction distribution +system.iobus.trans_dist::ReadResp 40334 # Transaction distribution +system.iobus.trans_dist::WriteReq 136600 # Transaction distribution +system.iobus.trans_dist::WriteResp 66161 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 65 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 70504 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48070 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353998 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48090 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156082 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334296 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334296 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492464 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 17794000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 9530000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 91000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 16563000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 71000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 339092871 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 44416000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 84714602 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 144000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 79163453 # DTB read hits +system.cpu0.dtb.read_misses 85617 # DTB read misses +system.cpu0.dtb.write_hits 72660708 # DTB write hits +system.cpu0.dtb.write_misses 28291 # DTB write misses +system.cpu0.dtb.flush_tlb 1291 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 21000 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 522 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 52340 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 3792 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 9968 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 79249070 # DTB read accesses +system.cpu0.dtb.write_accesses 72688999 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 151824161 # DTB hits +system.cpu0.dtb.misses 113908 # DTB misses +system.cpu0.dtb.accesses 151938069 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 424925918 # ITB inst hits +system.cpu0.itb.inst_misses 64800 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 1291 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 21000 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 522 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 37053 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 424990718 # ITB inst accesses +system.cpu0.itb.hits 424925918 # DTB hits +system.cpu0.itb.misses 64800 # DTB misses +system.cpu0.itb.accesses 424990718 # DTB accesses +system.cpu0.numCycles 511314689 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 424739937 # Number of instructions committed +system.cpu0.committedOps 499770936 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 458702697 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 419703 # Number of float alu accesses +system.cpu0.num_func_calls 25504192 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 64716286 # number of instructions that are conditional controls +system.cpu0.num_int_insts 458702697 # number of integer instructions +system.cpu0.num_fp_insts 419703 # number of float instructions +system.cpu0.num_int_register_reads 675611920 # number of times the integer registers were read +system.cpu0.num_int_register_writes 364415309 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 677474 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 352628 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 112049346 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 111774000 # number of times the CC registers were written +system.cpu0.num_mem_refs 151917751 # number of memory refs +system.cpu0.num_load_insts 79236622 # Number of load instructions +system.cpu0.num_store_insts 72681129 # Number of store instructions +system.cpu0.num_idle_cycles 499253695.584872 # Number of idle cycles +system.cpu0.num_busy_cycles 12060993.415128 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023588 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976412 # Percentage of idle cycles +system.cpu0.Branches 94879530 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 346985072 69.39% 69.39% # Class of executed instruction +system.cpu0.op_class::IntMult 1058214 0.21% 69.60% # Class of executed instruction +system.cpu0.op_class::IntDiv 47254 0.01% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 51204 0.01% 69.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.62% # Class of executed instruction +system.cpu0.op_class::MemRead 79236622 15.85% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 72681129 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 500059496 # Class of executed instruction +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 16293 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 14476947 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.977197 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 610391871 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14477459 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 42.161533 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8950087250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 497.229242 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 6.558404 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 8.189551 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.971151 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.012809 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.015995 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 639762187 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 639762187 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 418346381 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 129402990 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 62642500 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 610391871 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 418346381 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 129402990 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 62642500 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 610391871 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 418346381 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 129402990 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 62642500 # number of overall hits +system.cpu0.icache.overall_hits::total 610391871 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6638991 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 2049875 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 6203870 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14892736 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6638991 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 2049875 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 6203870 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14892736 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6638991 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 2049875 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 6203870 # number of overall misses +system.cpu0.icache.overall_misses::total 14892736 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 27332922248 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 82496329525 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 109829251773 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 27332922248 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 82496329525 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 109829251773 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 27332922248 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 82496329525 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 109829251773 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 424985372 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 131452865 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 68846370 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 625284607 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 424985372 # number of demand (read+write) accesses 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+system.cpu0.icache.ReadReq_miss_rate::total 0.023818 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015622 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015594 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.090112 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023818 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015622 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015594 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.090112 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023818 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13333.945849 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13297.559350 # average ReadReq miss latency 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access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.396073 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 415156 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 415156 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 415156 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 415156 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 415156 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 415156 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2049875 # number of ReadReq MSHR misses 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mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11332.252333 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11643.599580 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11562.178939 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11332.252333 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11643.599580 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11562.178939 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 10128409 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999720 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 303013393 # Total number of references to valid blocks. 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512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 1287987504 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1287987504 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 73967004 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 23189496 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 58636674 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 155793174 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 68735212 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 21073027 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 49137576 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 138945815 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 193443 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 57150 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 141238 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 391831 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 922078 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 196143 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data 445718 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 1563939 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1801315 # number of LoadLockedReq hits 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# number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1116910 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 8906291 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13625635 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4230016 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1304471 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 9355236 # number of overall misses +system.cpu0.dcache.overall_misses::total 14889723 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 12447991000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 82795568309 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 95243559309 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 10567240491 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 177246244923 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 187813485414 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 612526750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 3159923284 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3772450034 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 26501 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 90002 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 116503 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 23015231491 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 260041813232 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 283057044723 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 23015231491 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 260041813232 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 283057044723 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 76483286 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 23985701 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 63254681 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 163723668 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 69821364 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 21393732 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 53425860 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 144640956 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 821025 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 244711 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 590183 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1655919 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 922078 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 196143 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data 445718 # number of WriteInvalidateReq accesses(hits+misses) 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for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.072087 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.155353 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.096390 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000002 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024623 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024613 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.076331 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.044187 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028751 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028592 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.079775 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.048028 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15634.153265 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17928.852925 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12009.788963 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32950.033492 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 41332.674077 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 32977.846451 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14009.897990 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14111.273145 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9874.101985 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26501 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 18000.400000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19417.166667 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20606.164768 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 29197.542864 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20773.860794 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17643.344690 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27796.392655 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19010.229050 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 21434212 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 26746 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1267990 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 380 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.904086 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 70.384211 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 1563939 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 6807908 # number of writebacks +system.cpu0.dcache.writebacks::total 6807908 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 948 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 2610303 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 2611251 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4360 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 3551132 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3555492 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9967 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 136103 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 146070 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 5308 # number of demand (read+write) MSHR hits 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+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 187487 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 441899 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 629386 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 33754 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 87826 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121580 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 1111602 # number of demand (read+write) MSHR misses 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+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38222185199 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2771251250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 9108575422 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 11879826672 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 6372956000 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data 16470207883 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 22843163883 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 406720000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1117052111 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1523772111 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 24499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 79998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 104497 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 20570998009 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 59374795283 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 79945793292 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 23342249259 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 68483370705 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 91825619964 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 959248000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1745955500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2705203500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 898794000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1756075958 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2654869958 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1858042000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3502031458 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5360073458 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033155 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031740 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017120 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014787 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013648 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007228 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.766157 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.748749 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.380083 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055654 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060930 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.030674 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024496 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023456 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.012480 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028474 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027106 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.014444 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13564.597042 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15408.779055 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14885.547139 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30927.175264 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 39001.498893 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36558.411875 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14781.031485 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20612.346762 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18875.263625 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12049.534870 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12718.922768 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12533.082012 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 24499 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15999.600000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17416.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18505.722380 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21694.423549 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20773.391119 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17968.167892 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21543.997771 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20506.599466 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 24842678 # DTB read hits +system.cpu1.dtb.read_misses 30288 # DTB read misses +system.cpu1.dtb.write_hits 22204387 # DTB write hits +system.cpu1.dtb.write_misses 9453 # DTB write misses +system.cpu1.dtb.flush_tlb 1282 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 6426 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 22120 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1240 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 2953 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 24872966 # DTB read accesses +system.cpu1.dtb.write_accesses 22213840 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 47047065 # DTB hits +system.cpu1.dtb.misses 39741 # DTB misses +system.cpu1.dtb.accesses 47086806 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 131452865 # ITB inst hits +system.cpu1.itb.inst_misses 23431 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 1282 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 6426 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 16167 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 131476296 # ITB inst accesses +system.cpu1.itb.hits 131452865 # DTB hits +system.cpu1.itb.misses 23431 # DTB misses +system.cpu1.itb.accesses 131476296 # DTB accesses +system.cpu1.numCycles 1282114185 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 131358204 # Number of instructions committed +system.cpu1.committedOps 154205938 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 141499337 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 128756 # Number of float alu accesses +system.cpu1.num_func_calls 7727196 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 20146536 # number of instructions that are conditional controls +system.cpu1.num_int_insts 141499337 # number of integer instructions +system.cpu1.num_fp_insts 128756 # number of float instructions +system.cpu1.num_int_register_reads 205950168 # number of times the integer registers were read +system.cpu1.num_int_register_writes 112374883 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 204901 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 115300 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 34581843 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 34518712 # number of times the CC registers were written +system.cpu1.num_mem_refs 47044288 # number of memory refs +system.cpu1.num_load_insts 24842081 # Number of load instructions +system.cpu1.num_store_insts 22202207 # Number of store instructions +system.cpu1.num_idle_cycles 1255604442.364680 # Number of idle cycles +system.cpu1.num_busy_cycles 26509742.635320 # Number of busy cycles +system.cpu1.not_idle_fraction 0.020677 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.979323 # Percentage of idle cycles +system.cpu1.Branches 29364446 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 106871098 69.26% 69.26% # Class of executed instruction +system.cpu1.op_class::IntMult 352774 0.23% 69.49% # Class of executed instruction +system.cpu1.op_class::IntDiv 14834 0.01% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 17563 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::MemRead 24842081 16.10% 85.61% # Class of executed instruction +system.cpu1.op_class::MemWrite 22202207 14.39% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 154300599 # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu2.branchPred.lookups 95476448 # Number of BP lookups +system.cpu2.branchPred.condPredicted 64928073 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 4299413 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 64784895 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 46332623 # Number of BTB hits +system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.branchPred.BTBHitPct 71.517632 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 12285804 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 131917 # Number of incorrect RAS predictions. +system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu2.dtb.inst_hits 0 # ITB inst hits +system.cpu2.dtb.inst_misses 0 # ITB inst misses +system.cpu2.dtb.read_hits 77077341 # DTB read hits +system.cpu2.dtb.read_misses 441139 # DTB read misses +system.cpu2.dtb.write_hits 58693711 # DTB write hits +system.cpu2.dtb.write_misses 191612 # DTB write misses +system.cpu2.dtb.flush_tlb 1283 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva_asid 14423 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 383 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 37244 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 88 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 5986 # Number of TLB faults due to prefetch +system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.dtb.perms_faults 37589 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 77518480 # DTB read accesses +system.cpu2.dtb.write_accesses 58885323 # DTB write accesses +system.cpu2.dtb.inst_accesses 0 # ITB inst accesses +system.cpu2.dtb.hits 135771052 # DTB hits +system.cpu2.dtb.misses 632751 # DTB misses +system.cpu2.dtb.accesses 136403803 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu2.itb.inst_hits 69012170 # ITB inst hits +system.cpu2.itb.inst_misses 76652 # ITB inst misses +system.cpu2.itb.read_hits 0 # DTB read hits +system.cpu2.itb.read_misses 0 # DTB read misses +system.cpu2.itb.write_hits 0 # DTB write hits +system.cpu2.itb.write_misses 0 # DTB write misses +system.cpu2.itb.flush_tlb 1283 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva_asid 14423 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 383 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 28880 # Number of entries that have been flushed from TLB +system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.itb.perms_faults 143189 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.read_accesses 0 # DTB read accesses +system.cpu2.itb.write_accesses 0 # DTB write accesses +system.cpu2.itb.inst_accesses 69088822 # ITB inst accesses +system.cpu2.itb.hits 69012170 # DTB hits +system.cpu2.itb.misses 76652 # DTB misses +system.cpu2.itb.accesses 69088822 # DTB accesses +system.cpu2.numCycles 465978411 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.fetch.icacheStallCycles 177853142 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 424737263 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 95476448 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 58618427 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 260785808 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 9691059 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 1879827 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 8981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 2007 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 3759830 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 120446 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 3389 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 68846411 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 2635973 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 29904 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 449258797 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.104850 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.350365 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 344689329 76.72% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 13175573 2.93% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 13441142 2.99% 82.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 9727641 2.17% 84.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 19687409 4.38% 89.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 6520571 1.45% 90.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 7057131 1.57% 92.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 6252659 1.39% 93.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 28707342 6.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 449258797 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.204895 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.911496 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 145040906 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 213951941 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 77038080 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 9368936 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 3856816 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 14196524 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 1002861 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 463271274 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 3090116 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 3856816 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 150407499 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 19371841 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 168106415 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 80889236 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 26624521 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 452059055 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 70033 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 1786376 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 1304038 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 13315771 # Number of times rename has blocked due to SQ full +system.cpu2.rename.FullRegisterEvents 3626 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 431846627 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 688168989 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 533483946 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 696961 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 360553438 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 71293189 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 9871202 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 8455912 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 51921554 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 73490892 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 61773042 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 9381483 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 10099562 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 429589038 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 9855415 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 428971223 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 602179 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 55645947 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 38557670 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 233014 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 449258797 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.954842 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.673453 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 283324312 63.06% 63.06% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 67630078 15.05% 78.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 31491211 7.01% 85.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 22481401 5.00% 90.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 17057859 3.80% 93.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 11702074 2.60% 96.53% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 7876083 1.75% 98.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 4650016 1.04% 99.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 3045763 0.68% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 449258797 # Number of insts issued each cycle +system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2154851 25.07% 25.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 17173 0.20% 25.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 1684 0.02% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 3571205 41.55% 66.84% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 2850152 33.16% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 289729991 67.54% 67.54% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 1034875 0.24% 67.78% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 48976 0.01% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 286 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 48552 0.01% 67.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 78627004 18.33% 86.13% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 59481539 13.87% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::total 428971223 # Type of FU issued +system.cpu2.iq.rate 0.920582 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 8595065 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.020036 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 1315569237 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 495173501 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 412035990 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 829250 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 394091 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 358547 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 437122606 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 443682 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 3384290 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.squashedLoads 12185839 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 16415 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 485486 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 6512236 # Number of stores squashed +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.rescheduledLoads 2660066 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 6807125 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu2.iew.iewSquashCycles 3856816 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10978406 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 6986714 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 439540206 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 1332617 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 73490892 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 61773042 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 8263038 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 174452 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 6729882 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 485486 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 1971342 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1708494 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3679836 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 423953682 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 77064700 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 4393197 # Number of squashed instructions skipped in execute +system.cpu2.iew.exec_swp 0 # number of swp insts executed +system.cpu2.iew.exec_nop 95753 # number of nop insts executed +system.cpu2.iew.exec_refs 135758319 # number of memory reference insts executed +system.cpu2.iew.exec_branches 78468818 # Number of branches executed +system.cpu2.iew.exec_stores 58693619 # Number of stores executed +system.cpu2.iew.exec_rate 0.909814 # Inst execution rate +system.cpu2.iew.wb_sent 413267935 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 412394537 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 203830371 # num instructions producing a value +system.cpu2.iew.wb_consumers 353623803 # num instructions consuming a value +system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu2.iew.wb_rate 0.885008 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.576405 # average fanout of values written-back +system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu2.commit.commitSquashedInsts 59831265 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 9622401 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 3310537 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 439132239 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.864557 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.865641 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 302394835 68.86% 68.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 65341940 14.88% 83.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 24189817 5.51% 89.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 10943430 2.49% 91.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 7703754 1.75% 93.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 4855013 1.11% 94.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 4328620 0.99% 95.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 2957558 0.67% 96.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 16417272 3.74% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 439132239 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 323541810 # Number of instructions committed +system.cpu2.commit.committedOps 379654747 # Number of ops (including micro ops) committed +system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu2.commit.refs 116565859 # Number of memory references committed +system.cpu2.commit.loads 61305053 # Number of loads committed +system.cpu2.commit.membars 2541238 # Number of memory barriers committed +system.cpu2.commit.branches 72175443 # Number of branches committed +system.cpu2.commit.fp_insts 344817 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 348881889 # Number of committed integer instructions. +system.cpu2.commit.function_calls 9429592 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 262221519 69.07% 69.07% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 789172 0.21% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 36211 0.01% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 41986 0.01% 69.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 61305053 16.15% 85.44% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 55260806 14.56% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 379654747 # Class of committed instruction +system.cpu2.commit.bw_lim_events 16417272 # number cycles where commit BW limit reached +system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu2.rob.rob_reads 859553355 # The number of ROB reads +system.cpu2.rob.rob_writes 889110894 # The number of ROB writes +system.cpu2.timesIdled 2948522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 16719614 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 99518769709 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 323541810 # Number of Instructions Simulated +system.cpu2.committedOps 379654747 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.440242 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.440242 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.694328 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.694328 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 498743361 # number of integer regfile reads +system.cpu2.int_regfile_writes 295064264 # number of integer regfile writes +system.cpu2.fp_regfile_reads 684469 # number of floating regfile reads +system.cpu2.fp_regfile_writes 420852 # number of floating regfile writes +system.cpu2.cc_regfile_reads 90009576 # number of cc regfile reads +system.cpu2.cc_regfile_writes 90769749 # number of cc regfile writes +system.cpu2.misc_regfile_reads 1656723881 # number of misc regfile reads +system.cpu2.misc_regfile_writes 9715045 # number of misc regfile writes +system.iocache.tags.replacements 115464 # number of replacements +system.iocache.tags.tagsinuse 10.421560 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115480 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 13085874574509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.547265 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.874295 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221704 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429643 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651348 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 1040224 # Number of tag accesses +system.iocache.tags.data_accesses 1040224 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8819 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8856 # number of ReadReq misses +system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses +system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 65 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 65 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8819 # number of demand (read+write) misses +system.iocache.demand_misses::total 8859 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ethernet 40 # number of overall misses +system.iocache.overall_misses::realview.ide 8819 # number of overall misses +system.iocache.overall_misses::total 8859 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 2752000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1272471430 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1275223430 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 2752000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1272471430 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1275223430 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 2752000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1272471430 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1275223430 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8819 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8856 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106729 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106729 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8819 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8859 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8819 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8859 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000609 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000609 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 74378.378378 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 144287.496315 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 143995.418925 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 68800 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 144287.496315 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 143946.656508 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 68800 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 144287.496315 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 143946.656508 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 36080 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3735 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.659973 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 16 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 5668 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 5684 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 16 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 5668 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 5684 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ethernet 16 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 5668 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 5684 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1920000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 977655446 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 979575446 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2261356027 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2261356027 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 1920000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 977655446 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 979575446 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 1920000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 977655446 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 979575446 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 0.432432 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.642703 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.641825 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.642703 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.641607 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.642703 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.641607 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 120000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 172486.846507 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 172339.100281 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 172486.846507 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 172339.100281 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 172486.846507 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 172339.100281 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.kern.inst.arm 0 # number of arm instructions executed +system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini new file mode 100644 index 000000000..c85927ad5 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini @@ -0,0 +1,2121 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.realview.vram system.physmem system.realview.nvmem +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=DerivO3CPU +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu0.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu +dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu0.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +issueToExecuteDelay=1 +issueWidth=8 +istage2_mmu=system.cpu0.istage2_mmu +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu0.tracer +trapLatency=13 +wbWidth=8 +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu0.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[3] + +[system.cpu0.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 + +[system.cpu0.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu0.fuPool.FUList0.opList + +[system.cpu0.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu0.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 + +[system.cpu0.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu0.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu0.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 + +[system.cpu0.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu0.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu0.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu0.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +eventq_index=0 +opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 + +[system.cpu0.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu0.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu0.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu0.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +eventq_index=0 +opList=system.cpu0.fuPool.FUList4.opList + +[system.cpu0.fuPool.FUList4.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu0.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 + +[system.cpu0.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu0.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu0.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu0.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu0.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +issueLat=1 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+sequential_access=false +size=32768 + +[system.cpu0.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu0.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] + +[system.cpu0.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu1] +type=DerivO3CPU +children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu1.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu +dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu1.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=Null +isa=system.cpu1.isa +issueToExecuteDelay=1 +issueWidth=8 +istage2_mmu=system.cpu1.istage2_mmu +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=true +system=system +tracer=system.cpu1.tracer +trapLatency=13 +wbWidth=8 +workload= + +[system.cpu1.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 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+[system.cpu1.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu1.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +eventq_index=0 +opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 + +[system.cpu1.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu1.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu1.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu1.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +eventq_index=0 +opList=system.cpu1.fuPool.FUList4.opList + +[system.cpu1.fuPool.FUList4.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu1.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 + +[system.cpu1.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdAdd +opLat=1 + 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+[system.cpu1.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu1.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu1.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu1.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu1.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu1.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu1.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu1.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu1.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu1.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu1.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +eventq_index=0 +opList=system.cpu1.fuPool.FUList6.opList + +[system.cpu1.fuPool.FUList6.opList] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu1.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +eventq_index=0 +opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 + +[system.cpu1.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu1.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu1.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu1.fuPool.FUList8.opList + +[system.cpu1.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu1.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu1.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu1.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.l2c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.l2c.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr new file mode 100644 index 000000000..c5b003261 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr @@ -0,0 +1,463 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout new file mode 100644 index 000000000..0143bb788 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout @@ -0,0 +1,11 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 15:46:15 +gem5 started Oct 29 2014 19:59:19 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x42b8b00 0x42b8b00 + 0: system.cpu1.isa: ISA system set to: 0x42b8b00 0x42b8b00 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt new file mode 100644 index 000000000..b5546b4d2 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -0,0 +1,2420 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 51.316753 # Number of seconds simulated +sim_ticks 51316753294500 # Number of ticks simulated +final_tick 51316753294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 136598 # Simulator instruction rate (inst/s) +host_op_rate 160520 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7792719388 # Simulator tick rate (ticks/s) +host_mem_usage 670460 # Number of bytes of host memory used +host_seconds 6585.22 # Real time elapsed on the host +sim_insts 899526584 # Number of instructions simulated +sim_ops 1057057755 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.ide 436032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 324288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 511488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3575488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35714136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 305664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 479488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3431104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 34340592 # Number of bytes read from this memory +system.physmem.bytes_read::total 79118280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3575488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3431104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7006592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 46041344 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 50417380 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 49769472 # Number of bytes written to this memory +system.physmem.bytes_written::total 153054692 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 6813 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 5067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 7992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 55867 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 558041 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4776 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 7492 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 53611 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 536577 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1236236 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 719396 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 790023 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 777648 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2393731 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 8497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 6319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 9967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69675 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 695955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 5956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 9344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 66861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 669189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1541763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69675 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 66861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 136536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 897199 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 133027 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 982474 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 969848 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2982548 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 897199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 141524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 6319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 9967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1678429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 5956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 9344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 66861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1639037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4524311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1236236 # Number of read requests accepted +system.physmem.writeReqs 2393731 # Number of write requests accepted +system.physmem.readBursts 1236236 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2393731 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 78915968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 203136 # Total number of bytes read from write queue +system.physmem.bytesWritten 148972800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 79118280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 153054692 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 3174 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 66016 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 38473 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 78969 # Per bank write bursts +system.physmem.perBankRdBursts::1 76054 # Per bank write bursts +system.physmem.perBankRdBursts::2 70113 # Per bank write bursts +system.physmem.perBankRdBursts::3 71416 # Per bank write bursts +system.physmem.perBankRdBursts::4 73251 # Per bank write bursts +system.physmem.perBankRdBursts::5 79391 # Per bank write bursts +system.physmem.perBankRdBursts::6 70957 # Per bank write bursts +system.physmem.perBankRdBursts::7 70585 # Per bank write bursts +system.physmem.perBankRdBursts::8 72320 # Per bank write bursts +system.physmem.perBankRdBursts::9 103108 # Per bank write bursts +system.physmem.perBankRdBursts::10 75527 # Per bank write bursts +system.physmem.perBankRdBursts::11 73923 # Per bank write bursts +system.physmem.perBankRdBursts::12 74067 # Per bank write bursts +system.physmem.perBankRdBursts::13 84199 # Per bank write bursts +system.physmem.perBankRdBursts::14 79405 # Per bank write bursts +system.physmem.perBankRdBursts::15 79777 # Per bank write bursts +system.physmem.perBankWrBursts::0 143281 # Per bank write bursts +system.physmem.perBankWrBursts::1 127790 # Per bank write bursts +system.physmem.perBankWrBursts::2 148899 # Per bank write bursts +system.physmem.perBankWrBursts::3 137605 # Per bank write bursts +system.physmem.perBankWrBursts::4 197374 # Per bank write bursts +system.physmem.perBankWrBursts::5 124383 # Per bank write bursts +system.physmem.perBankWrBursts::6 109194 # Per bank write bursts +system.physmem.perBankWrBursts::7 129383 # Per bank write bursts +system.physmem.perBankWrBursts::8 151210 # Per bank write bursts +system.physmem.perBankWrBursts::9 186118 # Per bank write bursts +system.physmem.perBankWrBursts::10 208778 # Per bank write bursts +system.physmem.perBankWrBursts::11 141342 # Per bank write bursts +system.physmem.perBankWrBursts::12 123729 # Per bank write bursts +system.physmem.perBankWrBursts::13 141617 # Per bank write bursts +system.physmem.perBankWrBursts::14 124170 # Per bank write bursts +system.physmem.perBankWrBursts::15 132827 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 128 # Number of times write queue was full causing retry +system.physmem.totGap 51316752176000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 13 # Read request sizes (log2) +system.physmem.readPktSize::4 2 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1236221 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write 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15.173946 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 173.903253 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 81255 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 81261 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 81261 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 28.644737 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 24.485973 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.407420 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 56 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 139 0.17% 0.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 47231 58.12% 58.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 7834 9.64% 68.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 13023 16.03% 84.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 3682 4.53% 88.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 2148 2.64% 91.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 950 1.17% 92.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 2747 3.38% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1058 1.30% 97.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 767 0.94% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 240 0.30% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 341 0.42% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 185 0.23% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 486 0.60% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 8 0.01% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 31 0.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 23 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 18 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 31 0.04% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 73 0.09% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 62 0.08% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 51 0.06% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 8 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 17 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 17 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 9 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 7 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 81261 # Writes before turning the bus around for reads +system.physmem.totQLat 27538646010 # Total ticks spent queuing +system.physmem.totMemAccLat 50658558510 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6165310000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22333.55 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 41083.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.42 # Average write queue length when enqueuing +system.physmem.readRowHits 964323 # Number of row buffer hits during reads +system.physmem.writeRowHits 1918333 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.41 # Row buffer hit rate for writes +system.physmem.avgGap 14136974.85 # Average gap between requests +system.physmem.pageHitRate 80.96 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49243370940756 # Time in different power states +system.physmem.memoryStateTime::REF 1713579140000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 359802419244 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 2507478120 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2618973000 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1368167625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1429003125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 4607662800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 5010142800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 7244050320 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 7839445680 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3351760797840 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3351760797840 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1283842483380 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1294175764575 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29663873874750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29654809593000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34315204514835 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34317643720020 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.694001 # Core power per rank (mW) +system.physmem.averagePower::1 668.741533 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 2212 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 1408 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 2176 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 22 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 27 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 43 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 27 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 42 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 532705 # Transaction distribution +system.membus.trans_dist::ReadResp 532705 # Transaction distribution +system.membus.trans_dist::WriteReq 33859 # Transaction distribution +system.membus.trans_dist::WriteResp 33859 # Transaction distribution +system.membus.trans_dist::Writeback 719396 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1671762 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1671762 # Transaction distribution +system.membus.trans_dist::UpgradeReq 38473 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 38479 # Transaction distribution +system.membus.trans_dist::ReadExReq 739347 # Transaction distribution +system.membus.trans_dist::ReadExResp 739347 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) 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miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69490.587522 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65332.835824 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68762.503120 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 68171.426205 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10027.818041 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.023282 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.869565 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75638.343667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76875.600564 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76246.636268 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64880.809955 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73632.337498 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65332.835824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74260.183414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 73112.083134 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64880.809955 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73632.337498 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65332.835824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74260.183414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 73112.083134 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 18 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1669 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 25440595 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25432319 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33859 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33859 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7101304 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1671768 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1565098 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 50543 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 14 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 50557 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2138912 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2138912 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32275606 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29216023 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 915477 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2586660 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 64993766 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1032811840 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1154800272 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3083944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8731728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2199427784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 664547 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 36349119 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003178 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.056284 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 36233600 99.68% 99.68% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115519 0.32% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 36349119 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 52855909091 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 2566500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 72684313037 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 43208232692 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 533902381 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1509803178 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40375 # Transaction distribution +system.iobus.trans_dist::ReadResp 40375 # Transaction distribution +system.iobus.trans_dist::WriteReq 136543 # Transaction distribution +system.iobus.trans_dist::WriteResp 136733 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 190 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354216 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492622 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 981411596 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 178989221 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 132719565 # Number of BP lookups +system.cpu0.branchPred.condPredicted 89993236 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5932836 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 90710148 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 64716268 # Number of BTB hits +system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.branchPred.BTBHitPct 71.344022 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17452568 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 191045 # Number of incorrect RAS predictions. +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 106360367 # DTB read hits +system.cpu0.dtb.read_misses 615971 # DTB read misses +system.cpu0.dtb.write_hits 81393112 # DTB write hits +system.cpu0.dtb.write_misses 266071 # DTB write misses +system.cpu0.dtb.flush_tlb 1087 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 22107 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 543 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56260 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 229 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9041 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 57266 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 106976338 # DTB read accesses +system.cpu0.dtb.write_accesses 81659183 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 187753479 # DTB hits +system.cpu0.dtb.misses 882042 # DTB misses +system.cpu0.dtb.accesses 188635521 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 95391690 # ITB inst hits +system.cpu0.itb.inst_misses 104013 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 1087 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 22107 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 543 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 41837 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 207435 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 95495703 # ITB inst accesses +system.cpu0.itb.hits 95391690 # DTB hits +system.cpu0.itb.misses 104013 # DTB misses +system.cpu0.itb.accesses 95495703 # DTB accesses +system.cpu0.numCycles 684418323 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.fetch.icacheStallCycles 248384937 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 589536301 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 132719565 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 82168836 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 395321090 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13514905 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2556917 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 20977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 5408 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5551519 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 175554 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 1648 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 95166614 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3687085 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 41415 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 658775231 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.047637 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.297009 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 512971129 77.87% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18432133 2.80% 80.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18348661 2.79% 83.45% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13411814 2.04% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28741584 4.36% 89.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 9038627 1.37% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9794305 1.49% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8428424 1.28% 93.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 39608554 6.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 658775231 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.193916 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.861368 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 200994103 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 333361407 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105045785 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 14028144 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5343793 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19697248 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1433030 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 641923192 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4435962 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5343793 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 208785389 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 28964603 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 262496699 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111103202 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 42079210 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 626316852 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 80050 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2362679 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1879089 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 21911490 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 5199 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 599577423 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 966250594 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 740756106 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 877957 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 502593400 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96984018 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15462984 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13497488 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 79320336 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 100980804 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 85727659 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13927717 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14882282 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 593862929 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15564372 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 595387827 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 831090 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 76362787 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 53001437 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 356285 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 658775231 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.903780 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.628017 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 423143545 64.23% 64.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 100533840 15.26% 79.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43588427 6.62% 86.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 31078402 4.72% 90.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 23328962 3.54% 94.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 15913876 2.42% 96.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 10814135 1.64% 98.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6320463 0.96% 99.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4053581 0.62% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 658775231 # Number of insts issued each cycle +system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2985575 25.28% 25.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 23079 0.20% 25.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 3324 0.03% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5019003 42.51% 68.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3776946 31.99% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 402885613 67.67% 67.67% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1422777 0.24% 67.91% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 64552 0.01% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 67 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 58868 0.01% 67.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.93% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 108485553 18.22% 86.15% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82470396 13.85% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::total 595387827 # Type of FU issued +system.cpu0.iq.rate 0.869918 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11807929 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019832 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1861125914 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 685987174 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 571772727 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1063990 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 505463 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 456200 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 606627126 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 568629 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4761213 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.squashedLoads 16799552 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 22497 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 714171 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 9156054 # Number of stores squashed +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.rescheduledLoads 3900719 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 9933744 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewSquashCycles 5343793 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15674856 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 11567544 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 609566615 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1794840 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 100980804 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 85727659 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13194913 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 258499 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 11189475 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 714171 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2685620 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2322794 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5008414 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 588648436 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 106351748 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5872018 # Number of squashed instructions skipped in execute +system.cpu0.iew.exec_swp 0 # number of swp insts executed +system.cpu0.iew.exec_nop 139314 # number of nop insts executed +system.cpu0.iew.exec_refs 187749395 # number of memory reference insts executed +system.cpu0.iew.exec_branches 108957932 # Number of branches executed +system.cpu0.iew.exec_stores 81397647 # Number of stores executed +system.cpu0.iew.exec_rate 0.860071 # Inst execution rate +system.cpu0.iew.wb_sent 573457881 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 572228927 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 281462520 # num instructions producing a value +system.cpu0.iew.wb_consumers 488752044 # num instructions consuming a value +system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.wb_rate 0.836081 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575880 # average fanout of values written-back +system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.commit.commitSquashedInsts 82137816 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15208087 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4518905 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 644781794 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.817863 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.810443 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 449449526 69.71% 69.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 97358122 15.10% 84.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33578375 5.21% 90.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 14917712 2.31% 92.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10631887 1.65% 93.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6530680 1.01% 94.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5822825 0.90% 95.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3984235 0.62% 96.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22508432 3.49% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 644781794 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 448706085 # Number of instructions committed +system.cpu0.commit.committedOps 527343007 # Number of ops (including micro ops) committed +system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.refs 160752856 # Number of memory references committed +system.cpu0.commit.loads 84181251 # Number of loads committed +system.cpu0.commit.membars 3744837 # Number of memory barriers committed +system.cpu0.commit.branches 100346754 # Number of branches committed +system.cpu0.commit.fp_insts 436641 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 484032213 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13338237 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 365400890 69.29% 69.29% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1092025 0.21% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 47793 0.01% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 49443 0.01% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84181251 15.96% 85.48% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 76571605 14.52% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 527343007 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22508432 # number cycles where commit BW limit reached +system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.rob.rob_reads 1227661689 # The number of ROB reads +system.cpu0.rob.rob_writes 1232973286 # The number of ROB writes +system.cpu0.timesIdled 4104064 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25643092 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 54070741689 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 448706085 # Number of Instructions Simulated +system.cpu0.committedOps 527343007 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.525315 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.525315 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.655602 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.655602 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 693970255 # number of integer regfile reads +system.cpu0.int_regfile_writes 408353798 # number of integer regfile writes +system.cpu0.fp_regfile_reads 822679 # number of floating regfile reads +system.cpu0.fp_regfile_writes 492268 # number of floating regfile writes +system.cpu0.cc_regfile_reads 125884227 # number of cc regfile reads +system.cpu0.cc_regfile_writes 126919674 # number of cc regfile writes +system.cpu0.misc_regfile_reads 2342378074 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15341166 # number of misc regfile writes +system.cpu0.icache.tags.replacements 16116656 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.960235 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 173052626 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16117168 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.737161 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 11668105000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 286.930366 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 225.029869 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.560411 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.439511 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 206428941 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 206428941 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 86457913 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 86594713 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 173052626 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 86457913 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 86594713 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 173052626 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 86457913 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 86594713 # number of overall hits +system.cpu0.icache.overall_hits::total 173052626 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 8696178 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 8562854 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 17259032 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 8696178 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 8562854 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 17259032 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 8696178 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 8562854 # number of overall misses +system.cpu0.icache.overall_misses::total 17259032 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 115519417356 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 113985057745 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 229504475101 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 115519417356 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 113985057745 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 229504475101 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 115519417356 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 113985057745 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 229504475101 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 95154091 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 95157567 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 190311658 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 95154091 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 95157567 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 190311658 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 95154091 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 95157567 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 190311658 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.091390 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089986 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.090688 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.091390 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089986 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.090688 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.091390 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089986 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.090688 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13283.929717 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13311.573191 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13297.644683 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13283.929717 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13311.573191 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13297.644683 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13283.929717 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13311.573191 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13297.644683 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 66644 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 6194 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 10.759445 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 579009 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 562740 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 1141749 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 579009 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 562740 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 1141749 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 579009 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 562740 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 1141749 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8117169 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8000114 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 16117283 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8117169 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 8000114 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 16117283 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8117169 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 8000114 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 16117283 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94378713924 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 93158518069 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 187537231993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94378713924 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 93158518069 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 187537231993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94378713924 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 93158518069 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 187537231993 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 916338250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 595537750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1511876000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 916338250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 595537750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1511876000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.084072 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084689 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.084072 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.084689 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.084072 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.084689 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11627.048042 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11644.648822 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11635.784517 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11627.048042 # average overall mshr miss latency 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# miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17935.056532 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17601.895815 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17769.581072 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42830.825920 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 43446.252488 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43132.197558 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14191.494983 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14370.668955 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14280.149748 # average LoadLockedReq miss latency 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number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 25624743279 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29043542969 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 28669048764 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 57712591733 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1626539446 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1632214456 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3258753902 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 137497 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 93497 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 230994 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 89507595408 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 87428463442 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 176936058850 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 102801556910 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 99759245219 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 202560802129 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3260677254 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2455829253 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5716506507 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3279198543 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2300797457 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5579996000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6539875797 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4756626710 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11296502507 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033263 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032366 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032813 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015059 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014700 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.755601 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758360 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756955 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059522 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060299 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059905 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024887 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024068 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024476 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028855 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027884 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028368 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15462.887815 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15452.055657 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15457.526908 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40555.548912 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41159.303892 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40851.286367 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20112.349754 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19285.529383 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19705.808199 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12808.304888 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13049.155402 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12927.818140 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15277.444444 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18699.400000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16499.571429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22449.342881 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22505.203842 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22476.910456 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22117.008154 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22050.184269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22084.047493 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.branchPred.lookups 132695624 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90331188 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5850625 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91191115 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 65101533 # Number of BTB hits +system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.branchPred.BTBHitPct 71.390215 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17167330 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 185817 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 106438912 # DTB read hits +system.cpu1.dtb.read_misses 617019 # DTB read misses +system.cpu1.dtb.write_hits 81859907 # DTB write hits +system.cpu1.dtb.write_misses 262953 # DTB write misses +system.cpu1.dtb.flush_tlb 1095 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 21187 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 524 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 54609 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 175 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8788 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 55422 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 107055931 # DTB read accesses +system.cpu1.dtb.write_accesses 82122860 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 188298819 # DTB hits +system.cpu1.dtb.misses 879972 # DTB misses +system.cpu1.dtb.accesses 189178791 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 95390425 # ITB inst hits +system.cpu1.itb.inst_misses 103002 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 1095 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 21187 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 524 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40480 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 202732 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 95493427 # ITB inst accesses +system.cpu1.itb.hits 95390425 # DTB hits +system.cpu1.itb.misses 103002 # DTB misses +system.cpu1.itb.accesses 95493427 # DTB accesses +system.cpu1.numCycles 672741965 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.fetch.icacheStallCycles 246640136 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 590780429 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 132695624 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 82268863 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 386429410 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13305333 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2543340 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 19984 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 4103 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5378147 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 163710 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 1900 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 95165721 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3597908 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 39974 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 647833125 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.067316 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.314702 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 501796172 77.46% 77.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18436133 2.85% 80.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18485753 2.85% 83.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13501389 2.08% 85.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28566375 4.41% 89.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9032490 1.39% 91.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9749840 1.50% 92.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8516033 1.31% 93.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 39748940 6.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 647833125 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.197246 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.878168 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 200194473 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 322668892 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 105843727 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13827399 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5296426 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19681907 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1375410 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 644487824 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4238266 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5296426 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 207887374 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 28633275 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 252987067 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 111782593 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 41244065 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 628972841 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 101309 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2336709 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1765264 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 21471594 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 4932 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 601986706 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 968135800 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 743741537 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 921788 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 504541868 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 97444838 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15091316 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13114684 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 77880403 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 101483347 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 86159667 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13596196 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14436334 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 596800589 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15137564 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 597335702 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 820098 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 76624490 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53348640 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 353802 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 647833125 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.922052 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.644482 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 412924221 63.74% 63.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 99304245 15.33% 79.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43461350 6.71% 85.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31157407 4.81% 90.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23474401 3.62% 94.21% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16043027 2.48% 96.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 10934122 1.69% 98.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6355751 0.98% 99.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4178601 0.65% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 647833125 # Number of insts issued each cycle +system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3005947 25.29% 25.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 24266 0.20% 25.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2049 0.02% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 4 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4972015 41.83% 67.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3881824 32.66% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 404183986 67.66% 67.66% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1499549 0.25% 67.92% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 69544 0.01% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 173 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 16 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.93% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 70359 0.01% 67.94% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 108574781 18.18% 86.12% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 82937260 13.88% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::total 597335702 # Type of FU issued +system.cpu1.iq.rate 0.887912 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11886105 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019899 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1854102856 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 688730877 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 574087973 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1107876 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 525044 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 478100 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 608629489 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 592317 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4742542 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.squashedLoads 16809176 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 22821 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 704571 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 9065130 # Number of stores squashed +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.rescheduledLoads 3904838 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 9464363 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewSquashCycles 5296426 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 15503911 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 11248845 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 612073318 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1785807 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 101483347 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 86159667 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12828539 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 251466 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 10878256 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 704571 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2684400 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2302903 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4987303 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 590552056 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 106426998 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 5916414 # Number of squashed instructions skipped in execute +system.cpu1.iew.exec_swp 0 # number of swp insts executed +system.cpu1.iew.exec_nop 135165 # number of nop insts executed +system.cpu1.iew.exec_refs 188286771 # number of memory reference insts executed +system.cpu1.iew.exec_branches 109138667 # Number of branches executed +system.cpu1.iew.exec_stores 81859773 # Number of stores executed +system.cpu1.iew.exec_rate 0.877828 # Inst execution rate +system.cpu1.iew.wb_sent 575751009 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 574566073 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 283200911 # num instructions producing a value +system.cpu1.iew.wb_consumers 491579029 # num instructions consuming a value +system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.wb_rate 0.854066 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.576105 # average fanout of values written-back +system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.commit.commitSquashedInsts 82275122 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14783762 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4494113 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 633863514 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.835692 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.830647 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 439265925 69.30% 69.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 95913161 15.13% 84.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33589452 5.30% 89.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15187737 2.40% 92.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10634281 1.68% 93.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6553980 1.03% 94.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5971917 0.94% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 4055542 0.64% 96.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22691519 3.58% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::total 633863514 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 450820499 # Number of instructions committed +system.cpu1.commit.committedOps 529714748 # Number of ops (including micro ops) committed +system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu1.commit.refs 161768708 # Number of memory references committed +system.cpu1.commit.loads 84674171 # Number of loads committed +system.cpu1.commit.membars 3651509 # Number of memory barriers committed +system.cpu1.commit.branches 100548022 # Number of branches committed +system.cpu1.commit.fp_insts 459048 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 486295386 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13182426 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 366696799 69.23% 69.23% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1136926 0.21% 69.44% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 51579 0.01% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 60694 0.01% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 84674171 15.98% 85.45% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 77094537 14.55% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 529714748 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22691519 # number cycles where commit BW limit reached +system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu1.rob.rob_reads 1219313535 # The number of ROB reads +system.cpu1.rob.rob_writes 1237971918 # The number of ROB writes +system.cpu1.timesIdled 4075861 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 24908840 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 47205322910 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 450820499 # Number of Instructions Simulated +system.cpu1.committedOps 529714748 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.492261 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.492261 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.670124 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.670124 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 696110289 # number of integer regfile reads +system.cpu1.int_regfile_writes 410149745 # number of integer regfile writes +system.cpu1.fp_regfile_reads 853704 # number of floating regfile reads +system.cpu1.fp_regfile_writes 525664 # number of floating regfile writes +system.cpu1.cc_regfile_reads 126283635 # number of cc regfile reads +system.cpu1.cc_regfile_writes 127381072 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2332819849 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14911197 # number of misc regfile writes +system.iocache.tags.replacements 115453 # number of replacements +system.iocache.tags.tagsinuse 10.425607 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 13088656983000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544416 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.881191 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221526 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430074 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651600 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 1041134 # Number of tag accesses +system.iocache.tags.data_accesses 1041134 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses +system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses +system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 190 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 190 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8809 # number of demand (read+write) misses +system.iocache.demand_misses::total 8849 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ethernet 40 # number of overall misses +system.iocache.overall_misses::realview.ide 8809 # number of overall misses +system.iocache.overall_misses::total 8849 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5533000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1914739091 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1920272091 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5872000 # number of demand (read+write) miss cycles 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106854 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106854 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8809 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8849 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8809 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8849 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001778 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.001778 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149540.540541 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 217361.685889 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217078.011644 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 146800 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 217361.685889 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 217042.726975 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 146800 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 217361.685889 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 217042.726975 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 52653 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.590710 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8809 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8846 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8809 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8849 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8809 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8849 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3609000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1456535121 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1460144121 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6643047696 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6643047696 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3792000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1456535121 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1460327121 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3792000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1456535121 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1460327121 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97540.540541 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165346.250539 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 165062.640855 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94800 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 165346.250539 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165027.361397 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94800 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 165346.250539 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165027.361397 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 16389 # number of quiesce instructions executed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini new file mode 100644 index 000000000..6cf886297 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini @@ -0,0 +1,1361 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.realview.nvmem system.physmem system.realview.vram +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=TimingSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu +dtb=system.cpu0.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu0.tracer +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[3] + +[system.cpu0.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu0.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] + +[system.cpu0.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu1] +type=TimingSimpleCPU +children=dstage2_mmu dtb isa istage2_mmu itb tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu +dtb=system.cpu1.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=Null +isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=true +system=system +tracer=system.cpu1.tracer +workload= + +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu1.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu1.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu1.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu1.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.l2c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.l2c.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr new file mode 100644 index 000000000..35422844e --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr @@ -0,0 +1,1747 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR 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does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR 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User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR 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User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout new file mode 100644 index 000000000..7aed49fb9 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout @@ -0,0 +1,11 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 09:18:22 +gem5 started Oct 29 2014 13:24:01 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x5b6db00 0x5b6db00 + 0: system.cpu1.isa: ISA system set to: 0x5b6db00 0x5b6db00 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt new file mode 100644 index 000000000..3f21941cc --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -0,0 +1,1861 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 51.861029 # Number of seconds simulated +sim_ticks 51861029093000 # Number of ticks simulated +final_tick 51861029093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 655308 # Simulator instruction rate (inst/s) +host_op_rate 770071 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39176575505 # Simulator tick rate (ticks/s) +host_mem_usage 667356 # Number of bytes of host memory used +host_seconds 1323.78 # Real time elapsed on the host +sim_insts 867480679 # Number of instructions simulated +sim_ops 1019401547 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.ide 385536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 227072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 396672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2360360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 30329136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 251456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 422720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2259596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 29551000 # Number of bytes read from this memory +system.physmem.bytes_read::total 66183548 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2360360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2259596 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4619956 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 36744512 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 49590532 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 50357856 # Number of bytes written to this memory +system.physmem.bytes_written::total 143519396 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 6024 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 3548 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 6198 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 64295 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 473896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 6605 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 48299 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 461744 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1074538 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 574133 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 774853 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 789092 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2244742 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 7434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 4378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 7649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 45513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 584816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 8151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 569811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1276171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 45513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43570 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 708519 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 131631 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 956220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 971015 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2767384 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 708519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 139065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 7649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 45513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1541035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 8151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1540827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4043555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1074538 # Number of read requests accepted +system.physmem.writeReqs 2244742 # Number of write requests accepted +system.physmem.readBursts 1074538 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2244742 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 68582272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 188160 # Total number of bytes read from write queue +system.physmem.bytesWritten 138957696 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 66183548 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 143519396 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2940 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 73507 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 34757 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 71255 # Per bank write bursts +system.physmem.perBankRdBursts::1 63640 # Per bank write bursts +system.physmem.perBankRdBursts::2 66612 # Per bank write bursts +system.physmem.perBankRdBursts::3 61740 # Per bank write bursts +system.physmem.perBankRdBursts::4 60545 # Per bank write bursts +system.physmem.perBankRdBursts::5 71198 # Per bank write bursts +system.physmem.perBankRdBursts::6 58053 # Per bank write bursts +system.physmem.perBankRdBursts::7 57022 # Per bank write bursts +system.physmem.perBankRdBursts::8 61158 # Per bank write bursts +system.physmem.perBankRdBursts::9 112029 # Per bank write bursts +system.physmem.perBankRdBursts::10 66876 # Per bank write bursts +system.physmem.perBankRdBursts::11 66235 # Per bank write bursts +system.physmem.perBankRdBursts::12 62785 # Per bank write bursts +system.physmem.perBankRdBursts::13 68778 # Per bank write bursts +system.physmem.perBankRdBursts::14 63805 # Per bank write bursts +system.physmem.perBankRdBursts::15 59867 # Per bank write bursts +system.physmem.perBankWrBursts::0 127784 # Per bank write bursts +system.physmem.perBankWrBursts::1 113302 # Per bank write bursts +system.physmem.perBankWrBursts::2 227736 # Per bank write bursts +system.physmem.perBankWrBursts::3 110987 # Per bank write bursts +system.physmem.perBankWrBursts::4 128170 # Per bank write bursts +system.physmem.perBankWrBursts::5 133310 # Per bank write bursts +system.physmem.perBankWrBursts::6 113658 # Per bank write bursts +system.physmem.perBankWrBursts::7 104648 # Per bank write bursts +system.physmem.perBankWrBursts::8 114567 # Per bank write bursts +system.physmem.perBankWrBursts::9 129854 # Per bank write bursts +system.physmem.perBankWrBursts::10 127393 # Per bank write bursts +system.physmem.perBankWrBursts::11 118149 # Per bank write bursts +system.physmem.perBankWrBursts::12 133562 # Per bank write bursts +system.physmem.perBankWrBursts::13 181801 # Per bank write bursts +system.physmem.perBankWrBursts::14 180172 # Per bank write bursts +system.physmem.perBankWrBursts::15 126121 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 51861026536500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 43101 # Read request sizes (log2) +system.physmem.readPktSize::3 13 # Read request sizes (log2) +system.physmem.readPktSize::4 2 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1031422 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 1 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) 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What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1640 # What 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queue length does an incoming req see +system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 38 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 634955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.856851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.109909 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.606066 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251774 39.65% 39.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 143572 22.61% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53819 8.48% 70.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28426 4.48% 75.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19160 3.02% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14370 2.26% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10671 1.68% 82.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11114 1.75% 83.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 102049 16.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 634955 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 109417 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 9.793551 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 155.538286 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 109409 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-6143 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::18432-20479 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 109417 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 109417 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.843480 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.459226 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 5.174824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 51 0.05% 0.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 17 0.02% 0.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 14 0.01% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 145 0.13% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 52162 47.67% 47.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 51235 46.83% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 1984 1.81% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1760 1.61% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 951 0.87% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 159 0.15% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 147 0.13% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 71 0.06% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 99 0.09% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.02% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 21 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 18 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 372 0.34% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 33 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 39 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 36 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 9 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 9 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 109417 # Writes before turning the bus around for reads +system.physmem.totQLat 11994975500 # Total ticks spent queuing +system.physmem.totMemAccLat 32087438000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5357990000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11193.54 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29943.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 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rank (pJ) +system.physmem.actEnergy::1 2424960720 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1296046125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1323143250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 3978491400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 4379902800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 6866175600 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 7203291120 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3387310158960 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3387310158960 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1391264257590 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1403130352860 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61368.888124 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61488.721934 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61808.552748 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.024727 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.852093 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.444487 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59385.087720 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58837.681366 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 59118.625213 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64077.156144 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64393.877057 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61448.385359 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 60179.213802 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64551.094426 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61368.888124 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59716.297036 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60144.719509 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64077.156144 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64393.877057 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61448.385359 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 60179.213802 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64551.094426 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61368.888124 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59716.297036 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60144.719509 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 18 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1669 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 21596881 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 21588675 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33873 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33873 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 6657868 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1668053 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1561372 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 44174 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 44175 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2054795 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2054795 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 27631338 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27242891 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 786774 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1184296 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 56845299 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 881615316 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1077879160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2651280 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3722288 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 1965868044 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 493907 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 31944858 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003617 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.060036 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 31829300 99.64% 99.64% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115558 0.36% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 31944858 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 48864007000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 3007500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 62042103256 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 39821087024 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 456077500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 719536250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40403 # Transaction distribution +system.iobus.trans_dist::ReadResp 40403 # Transaction distribution +system.iobus.trans_dist::WriteReq 136728 # Transaction distribution +system.iobus.trans_dist::WriteResp 136733 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 5 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 981115277 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179046791 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 81298671 # DTB read hits +system.cpu0.dtb.read_misses 94598 # DTB read misses +system.cpu0.dtb.write_hits 74077534 # DTB write hits +system.cpu0.dtb.write_misses 29691 # DTB write misses +system.cpu0.dtb.flush_tlb 51863 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 19908 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 526 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 72449 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 4385 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 9644 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 81393269 # DTB read accesses +system.cpu0.dtb.write_accesses 74107225 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 155376205 # DTB hits +system.cpu0.dtb.misses 124289 # DTB misses +system.cpu0.dtb.accesses 155500494 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 433719693 # ITB inst hits +system.cpu0.itb.inst_misses 76771 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 51863 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 19908 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 526 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 53078 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 433796464 # ITB inst accesses +system.cpu0.itb.hits 433719693 # DTB hits +system.cpu0.itb.misses 76771 # DTB misses +system.cpu0.itb.accesses 433796464 # DTB accesses +system.cpu0.numCycles 51861670459 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 433465167 # Number of instructions committed +system.cpu0.committedOps 509426348 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 467950836 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 437595 # Number of float alu accesses +system.cpu0.num_func_calls 25817816 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 66030471 # number of instructions that are conditional controls +system.cpu0.num_int_insts 467950836 # number of integer instructions +system.cpu0.num_fp_insts 437595 # number of float instructions +system.cpu0.num_int_register_reads 681169150 # number of times the integer registers were read +system.cpu0.num_int_register_writes 371166205 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 709571 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 361724 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 113513031 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 113190912 # number of times the CC registers were written +system.cpu0.num_mem_refs 155365727 # number of memory refs +system.cpu0.num_load_insts 81295009 # Number of load instructions +system.cpu0.num_store_insts 74070718 # Number of store instructions +system.cpu0.num_idle_cycles 50261080538.032112 # Number of idle cycles +system.cpu0.num_busy_cycles 1600589920.967886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030863 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969137 # Percentage of idle cycles +system.cpu0.Branches 96751437 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 353168573 69.29% 69.29% # Class of executed instruction +system.cpu0.op_class::IntMult 1074186 0.21% 69.50% # Class of executed instruction +system.cpu0.op_class::IntDiv 48850 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 52802 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::MemRead 81295009 15.95% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 74070718 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 509710139 # Class of executed instruction +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 16204 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 13772027 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.894677 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 854244882 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13772539 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 62.025229 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 31522505250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 257.415454 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 254.479223 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.502765 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.497030 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999794 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 881789970 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 881789970 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 426831583 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 427413299 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 854244882 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 426831583 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 427413299 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 854244882 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 426831583 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 427413299 # number of overall hits +system.cpu0.icache.overall_hits::total 854244882 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6888110 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 6884434 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 13772544 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6888110 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 6884434 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 13772544 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6888110 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 6884434 # number of overall misses +system.cpu0.icache.overall_misses::total 13772544 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92034347501 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 91949004755 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 183983352256 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 92034347501 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 91949004755 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 183983352256 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 92034347501 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 91949004755 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 183983352256 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 433719693 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 434297733 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 868017426 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 433719693 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 434297733 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 868017426 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 433719693 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 434297733 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 868017426 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015881 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015852 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015867 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015881 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015852 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015867 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015881 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015852 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015867 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13361.335330 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13356.073245 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13358.704990 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13361.335330 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13356.073245 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13358.704990 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13361.335330 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13356.073245 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13358.704990 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6888110 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6884434 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 13772544 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6888110 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 6884434 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 13772544 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6888110 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 6884434 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 13772544 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 78245563999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 78167770745 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 156413334744 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 78245563999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 78167770745 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 156413334744 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 78245563999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 78167770745 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 156413334744 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1919614500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 912090000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2831704500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1919614500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 912090000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 2831704500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015881 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015852 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015867 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015881 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015852 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.015867 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015881 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015852 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.015867 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11359.511390 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11354.277018 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11356.894902 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11359.511390 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11354.277018 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11356.894902 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11359.511390 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11354.277018 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11356.894902 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 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+system.cpu0.dcache.tags.avg_refs 30.590507 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3092948250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 231.008949 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 280.960750 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.451189 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.548751 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per 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300287158 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150745154 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 151155540 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 301900694 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032269 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032696 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.032483 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014966 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014744 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.014855 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.763110 # miss rate for SoftPFReq accesses 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0.028015 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028061 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028038 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15814.645087 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15859.003827 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15837.031986 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 33150.063365 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32313.199090 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 32734.814354 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14134.142108 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14395.484168 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14264.010214 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26501 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20953.638863 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20621.136573 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20786.658245 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17878.178294 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17672.228332 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17774.978500 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 1561372 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 6657868 # number of writebacks +system.cpu0.dcache.writebacks::total 6657868 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 2373 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2635 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 5008 # 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ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014832 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014706 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762894 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.756761 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759849 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059686 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058128 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058906 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023953 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024081 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024017 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027935 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027965 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027950 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13760.451596 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13798.852093 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13779.830690 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31087.495244 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30276.252568 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30685.397593 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15177.486404 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15260.974681 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15218.777808 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12055.040696 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12230.837216 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12141.873909 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24499 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18867.875352 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18533.420400 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18699.966333 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18324.815005 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18063.990320 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18194.153896 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 81731723 # DTB read hits +system.cpu1.dtb.read_misses 99102 # DTB read misses +system.cpu1.dtb.write_hits 74078403 # DTB write hits +system.cpu1.dtb.write_misses 30075 # DTB write misses +system.cpu1.dtb.flush_tlb 51867 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 20925 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 72169 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 4438 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 9782 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 81830825 # DTB read accesses +system.cpu1.dtb.write_accesses 74108478 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 155810126 # DTB hits +system.cpu1.dtb.misses 129177 # DTB misses +system.cpu1.dtb.accesses 155939303 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 434297733 # ITB inst hits +system.cpu1.itb.inst_misses 78021 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 51867 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 20925 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 53659 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 434375754 # ITB inst accesses +system.cpu1.itb.hits 434297733 # DTB hits +system.cpu1.itb.misses 78021 # DTB misses +system.cpu1.itb.accesses 434375754 # DTB accesses +system.cpu1.numCycles 51860387727 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 434015512 # Number of instructions committed +system.cpu1.committedOps 509975199 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 468434913 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 458508 # Number of float alu accesses +system.cpu1.num_func_calls 25828963 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66119194 # number of instructions that are conditional controls +system.cpu1.num_int_insts 468434913 # number of integer instructions +system.cpu1.num_fp_insts 458508 # number of float instructions +system.cpu1.num_int_register_reads 681011171 # number of times the integer registers were read +system.cpu1.num_int_register_writes 371474138 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 735722 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 396908 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 113358693 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113081851 # number of times the CC registers were written +system.cpu1.num_mem_refs 155802990 # number of memory refs +system.cpu1.num_load_insts 81728236 # Number of load instructions +system.cpu1.num_store_insts 74074754 # Number of store instructions +system.cpu1.num_idle_cycles 50263670387.895683 # Number of idle cycles +system.cpu1.num_busy_cycles 1596717339.104316 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030789 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969211 # Percentage of idle cycles +system.cpu1.Branches 96920557 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 353254188 69.23% 69.23% # Class of executed instruction +system.cpu1.op_class::IntMult 1106936 0.22% 69.45% # Class of executed instruction +system.cpu1.op_class::IntDiv 48650 0.01% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 58473 0.01% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::MemRead 81728236 16.02% 85.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 74074754 14.52% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 510271279 # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.iocache.tags.replacements 115483 # number of replacements +system.iocache.tags.tagsinuse 10.461502 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 13154061165000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.844281 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.617221 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.365268 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.288576 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653844 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 1039906 # Number of tag accesses +system.iocache.tags.data_accesses 1039906 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses +system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses +system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 5 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 5 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses +system.iocache.demand_misses::total 8877 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ethernet 40 # number of overall misses +system.iocache.overall_misses::realview.ide 8837 # number of overall misses +system.iocache.overall_misses::total 8877 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1908690112 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1914175112 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1908690112 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1914514112 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1908690112 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1914514112 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106669 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106669 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000047 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000047 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 215988.470295 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 215706.007663 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 215988.470295 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 215671.297961 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 215988.470295 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 215671.297961 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51929 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.458834 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1449081112 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1452642112 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6526726956 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6526726956 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1449081112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1452825112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1449081112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1452825112 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163978.851646 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 163696.429119 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 163978.851646 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 163661.722654 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 163978.851646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 163661.722654 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- |